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/*

 * Copyright (c) 2014, Aleksander Osman

 * All rights reserved.

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions are met:

 *

 * * Redistributions of source code must retain the above copyright notice, this

 *   list of conditions and the following disclaimer.

 *

 * * Redistributions in binary form must reproduce the above copyright notice,

 *   this list of conditions and the following disclaimer in the documentation

 *   and/or other materials provided with the distribution.

 *

 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE

 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR

 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER

 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,

 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */

`include "defines.v"

module pipeline(

    input           clk,

    input           rst_n,

    //to memory

    output              pr_reset,

    output              rd_reset,

    output              exe_reset,

    output              wr_reset,

    output              real_mode,

    //exception

    input               exc_restore_esp,

    input               exc_set_rflag,

    input               exc_debug_start,

    input               exc_init,

    input               exc_load,

    input       [31:0]  exc_eip,

    input       [7:0]   exc_vector,

    input       [15:0]  exc_error_code,

    input               exc_push_error,

    input               exc_soft_int,

    input               exc_soft_int_ib,

    input               exc_pf_read,

    input               exc_pf_write,

    input               exc_pf_code,

    input               exc_pf_check,

    //pipeline eip

    output      [31:0]  eip,

    output      [31:0]  dec_eip,

    output      [31:0]  rd_eip,

    output      [31:0]  exe_eip,

    output      [31:0]  wr_eip,

    output      [3:0]   rd_consumed,

    output      [3:0]   exe_consumed,

    output      [3:0]   wr_consumed,

    //exception reset

    input               exc_dec_reset,

    input               exc_micro_reset,

    input               exc_rd_reset,

    input               exc_exe_reset,

    input               exc_wr_reset,

    //global

    input       [31:0]  glob_param_1,

    input       [31:0]  glob_param_2,

    input       [31:0]  glob_param_3,

    input       [31:0]  glob_param_4,

    input       [31:0]  glob_param_5,

    input       [63:0]  glob_descriptor,

    input       [63:0]  glob_descriptor_2,

    input       [31:0]  glob_desc_base,

    input       [31:0]  glob_desc_limit,

    input       [31:0]  glob_desc_2_limit,

    //pipeline state

    output              rd_dec_is_front,

    output              rd_is_front,

    output              exe_is_front,

    output              wr_is_front,

    output              pipeline_after_read_empty,

    output              pipeline_after_prefetch_empty,

    //dec exceptions

    output              dec_gp_fault,

    output              dec_ud_fault,

    output              dec_pf_fault,

    //rd exception

    output              rd_io_allow_fault,

    output              rd_descriptor_gp_fault,

    output              rd_seg_gp_fault,

    output              rd_seg_ss_fault,

    output              rd_ss_esp_from_tss_fault,

    //exe exception

    output              exe_bound_fault,

    output              exe_trigger_gp_fault,

    output              exe_trigger_ts_fault,

    output              exe_trigger_ss_fault,

    output              exe_trigger_np_fault,

    output              exe_trigger_pf_fault,

    output              exe_trigger_db_fault,

    output              exe_trigger_nm_fault,

    output              exe_load_seg_gp_fault,

    output              exe_load_seg_ss_fault,

    output              exe_load_seg_np_fault,

    output              exe_div_exception,

    //wr exception

    output              wr_debug_init,

    output              wr_new_push_ss_fault,

    output              wr_string_es_fault,

    output              wr_push_ss_fault,

    //error code

    output      [15:0]  rd_error_code,

    output      [15:0]  exe_error_code,

    output      [15:0]  wr_error_code,

    //glob output

    output              glob_descriptor_set,

    output      [63:0]  glob_descriptor_value,

    output              glob_descriptor_2_set,

    output      [63:0]  glob_descriptor_2_value,

    output              glob_param_1_set,

    output      [31:0]  glob_param_1_value,

    output              glob_param_2_set,

    output      [31:0]  glob_param_2_value,

    output              glob_param_3_set,

    output      [31:0]  glob_param_3_value,

    output              glob_param_4_set,

    output      [31:0]  glob_param_4_value,

    output              glob_param_5_set,

    output      [31:0]  glob_param_5_value,

    // prefetch

    output      [1:0]   prefetch_cpl,

    output      [31:0]  prefetch_eip,

    output      [63:0]  cs_cache,

    output              cr0_pg,

    output              cr0_wp,

    output              cr0_am,

    output              cr0_cd,

    output              cr0_nw,

    output              acflag,

    output      [31:0]  cr3,

    // prefetch_fifo

    output              prefetchfifo_accept_do,

    input       [67:0]  prefetchfifo_accept_data,

    input               prefetchfifo_accept_empty,

    //io_read

    output              io_read_do,

    output      [15:0]  io_read_address,

    output      [2:0]   io_read_length,

    input       [31:0]  io_read_data,

    input               io_read_done,

    //read memory

    output              read_do,

    input               read_done,

    input               read_page_fault,

    input               read_ac_fault,

    output      [1:0]   read_cpl,

    output      [31:0]  read_address,

    output      [3:0]   read_length,

    output              read_lock,

    output              read_rmw,

    input       [63:0]  read_data,

    //tlbcheck

    output              tlbcheck_do,

    input               tlbcheck_done,

    input               tlbcheck_page_fault,

    output      [31:0]  tlbcheck_address,

    output              tlbcheck_rw,

    //tlbflushsingle

    output              tlbflushsingle_do,

    input               tlbflushsingle_done,

    output      [31:0]  tlbflushsingle_address,

    //flush tlb

    output              tlbflushall_do,

    //invd

    output              invdcode_do,

    input               invdcode_done,

    output              invddata_do,

    input               invddata_done,

    output              wbinvddata_do,

    input               wbinvddata_done,

    //interrupt

    input               interrupt_do,

    output              wr_interrupt_possible,

    output              wr_string_in_progress_final,

    output              wr_is_esp_speculative,

    //software interrupt

    output              wr_int,

    output              wr_int_soft_int,

    output              wr_int_soft_int_ib,

    output      [7:0]   wr_int_vector,

    output              wr_exception_external_set,

    output              wr_exception_finished,

    //memory page fault

    input       [31:0]  tlb_code_pf_cr2,

    input       [31:0]  tlb_write_pf_cr2,

    input       [31:0]  tlb_read_pf_cr2,

    input       [31:0]  tlb_check_pf_cr2,

    //memory write

    output              write_do,

    input               write_done,

    input               write_page_fault,

    input               write_ac_fault,

    output      [1:0]   write_cpl,

    output      [31:0]  write_address,

    output      [2:0]   write_length,

    output              write_lock,

    output              write_rmw,

    output      [31:0]  write_data,

    //io write

    output              io_write_do,

    output      [15:0]  io_write_address,

    output      [2:0]   io_write_length,

    output      [31:0]  io_write_data,

    input               io_write_done

);

//------------------------------------------------------------------------------

// synthesis translate_off

wire _unused_ok = &{ 1'b0, SW[16:7], 1'b0 };

// synthesis translate_on

//------------------------------------------------------------------------------

assign prefetch_cpl = cpl;

//------------------------------------------------------------------------------ pipeline state

wire      pipeline_dec_idle;

reg [1:0] pipeline_dec_idle_counter;

assign pipeline_dec_idle                = rd_dec_is_front && prefetchfifo_accept_empty;

always @(posedge clk or negedge rst_n) begin

    if(rst_n == 1'b0)                                               pipeline_dec_idle_counter <= 2'd0;

    else if(pipeline_dec_idle && pipeline_dec_idle_counter < 2'd3)  pipeline_dec_idle_counter <= pipeline_dec_idle_counter + 2'd1;

    else if(~(pipeline_dec_idle))                                   pipeline_dec_idle_counter <= 2'd0;

end

assign pipeline_after_read_empty        = rd_is_front;

assign pipeline_after_prefetch_empty    = pipeline_dec_idle && pipeline_dec_idle_counter == 2'd3;

//------------------------------------------------------------------------------

wire        rd_glob_descriptor_set;

wire [63:0] rd_glob_descriptor_value;

wire        rd_glob_descriptor_2_set;

wire [63:0] rd_glob_descriptor_2_value;

wire        rd_glob_param_1_set;

wire [31:0] rd_glob_param_1_value;

wire        rd_glob_param_2_set;

wire [31:0] rd_glob_param_2_value;

wire        rd_glob_param_3_set;

wire [31:0] rd_glob_param_3_value;

wire        rd_glob_param_4_set;

wire [31:0] rd_glob_param_4_value;

wire        rd_glob_param_5_set;

wire [31:0] rd_glob_param_5_value;

wire        exe_glob_descriptor_set;

wire [63:0] exe_glob_descriptor_value;

wire        exe_glob_descriptor_2_set;

wire [63:0] exe_glob_descriptor_2_value;

wire        exe_glob_param_1_set;

wire [31:0] exe_glob_param_1_value;

wire        exe_glob_param_2_set;

wire [31:0] exe_glob_param_2_value;

wire        exe_glob_param_3_set;

wire [31:0] exe_glob_param_3_value;

wire        wr_glob_param_1_set;

wire [31:0] wr_glob_param_1_value;

wire        wr_glob_param_3_set;

wire [31:0] wr_glob_param_3_value;

wire        wr_glob_param_4_set;

wire [31:0] wr_glob_param_4_value;

assign glob_descriptor_set      = rd_glob_descriptor_set | exe_glob_descriptor_set;

assign glob_descriptor_value    = (rd_glob_descriptor_set)? rd_glob_descriptor_value : exe_glob_descriptor_value;

assign glob_descriptor_2_set    = rd_glob_descriptor_2_set | exe_glob_descriptor_2_set;

assign glob_descriptor_2_value  = (rd_glob_descriptor_2_set)? rd_glob_descriptor_2_value : exe_glob_descriptor_2_value;

assign glob_param_1_set     = rd_glob_param_1_set | exe_glob_param_1_set | wr_glob_param_1_set;

assign glob_param_1_value   = (rd_glob_param_1_set)? rd_glob_param_1_value : (exe_glob_param_1_set)? exe_glob_param_1_value : wr_glob_param_1_value;

assign glob_param_2_set     = rd_glob_param_2_set | exe_glob_param_2_set;

assign glob_param_2_value   = (rd_glob_param_2_set)? rd_glob_param_2_value : exe_glob_param_2_value;

assign glob_param_3_set     = rd_glob_param_3_set | exe_glob_param_3_set | wr_glob_param_3_set;

assign glob_param_3_value   = (rd_glob_param_3_set)? rd_glob_param_3_value : (exe_glob_param_3_set)? exe_glob_param_3_value : wr_glob_param_3_value;

assign glob_param_4_set     = rd_glob_param_4_set | wr_glob_param_4_set;

assign glob_param_4_value   = (rd_glob_param_4_set)? rd_glob_param_4_value : wr_glob_param_4_value;

assign glob_param_5_set     = rd_glob_param_5_set;

assign glob_param_5_value   = rd_glob_param_5_value;

//------------------------------------------------------------------------------

wire wr_req_reset_pr;

wire wr_req_reset_dec;

wire wr_req_reset_micro;

wire wr_req_reset_rd;

wire wr_req_reset_exe;

wire dec_reset;

wire micro_reset;

assign pr_reset    =                   wr_req_reset_pr;

assign dec_reset   = exc_dec_reset   | wr_req_reset_dec;

assign micro_reset = exc_micro_reset | wr_req_reset_micro;

assign rd_reset    = exc_rd_reset    | wr_req_reset_rd;

assign exe_reset   = exc_exe_reset   | wr_req_reset_exe;

assign wr_reset    = exc_wr_reset;

//------------------------------------------------------------------------------

wire [1:0]  cpl;

wire [31:0] gdtr_base;

wire [15:0] gdtr_limit;

wire [31:0] idtr_base;

wire [15:0] idtr_limit;

wire        es_cache_valid;

wire [63:0] es_cache;

wire        cs_cache_valid;

wire        ss_cache_valid;

wire [63:0] ss_cache;

wire        ds_cache_valid;

wire [63:0] ds_cache;

wire        fs_cache_valid;

wire [63:0] fs_cache;

wire        gs_cache_valid;

wire [63:0] gs_cache;

wire        tr_cache_valid;

wire [63:0] tr_cache;

wire        ldtr_cache_valid;

wire [63:0] ldtr_cache;

wire        idflag;

wire        vmflag;

wire        rflag;

wire        ntflag;

wire [1:0]  iopl;

wire        oflag;

wire        dflag;

wire        iflag;

wire        tflag;

wire        sflag;

wire        zflag;

wire        aflag;

wire        pflag;

wire        cflag;

wire        cr0_ne;

wire        cr0_ts;

wire        cr0_em;

wire        cr0_mp;

wire        cr0_pe;

wire [31:0] cr2;

wire [31:0] eax;

wire [31:0] ebx;

wire [31:0] ecx;

wire [31:0] edx;

wire [31:0] esp;

wire [31:0] ebp;

wire [31:0] esi;

wire [31:0] edi;

wire [15:0] es;

wire [15:0] cs;

wire [15:0] ss;

wire [15:0] ds;

wire [15:0] fs;

wire [15:0] gs;

wire [15:0] ldtr;

wire [15:0] tr;

wire [31:0] dr0;

wire [31:0] dr1;

wire [31:0] dr2;

wire [31:0] dr3;

wire        dr6_bt;

wire        dr6_bs;

wire        dr6_bd;

wire        dr6_b12;

wire [3:0]  dr6_breakpoints;

wire [31:0] dr7;

//------------------------------------------------------------------------------

wire [3:0]  fetch_valid;

wire [63:0] fetch;

wire        fetch_limit;

wire        fetch_page_fault;

wire [3:0]  dec_acceptable;

fetch fetch_inst(

    .clk                        (clk),

    .rst_n                      (rst_n),

    .pr_reset                   (pr_reset),

    // get prefetch_eip

    .wr_eip                     (wr_eip),                       //input [31:0]

    .prefetch_eip               (prefetch_eip),                 //output [31:0]

    // prefetch_fifo

    .prefetchfifo_accept_do     (prefetchfifo_accept_do),       //output

    .prefetchfifo_accept_data   (prefetchfifo_accept_data),     //input [67:0]

    .prefetchfifo_accept_empty  (prefetchfifo_accept_empty),    //input

    // fetch interface to decode

    .fetch_valid                (fetch_valid),                  //output [3:0]

    .fetch                      (fetch),                        //output [63:0]

    .fetch_limit                (fetch_limit),                  //output

    .fetch_page_fault           (fetch_page_fault),             //output

    // feedback from decode

    .dec_acceptable             (dec_acceptable)                //input [3:0]

);

//------------------------------------------------------------------------------

wire        v8086_mode;

wire        protected_mode;

wire        micro_busy;

wire        dec_ready;

wire [95:0] decoder;

wire        dec_operand_32bit;

wire        dec_address_32bit;

wire [1:0]  dec_prefix_group_1_rep;

wire        dec_prefix_group_1_lock;

wire [2:0]  dec_prefix_group_2_seg;

wire        dec_prefix_2byte;

wire [3:0]  dec_consumed;

wire [2:0]  dec_modregrm_len;

wire        dec_is_8bit;

wire [6:0]  dec_cmd;

wire [3:0]  dec_cmdex;

wire        dec_is_complex;

wire [6:0]  micro_cmd;

wire [6:0]  rd_cmd;

decode decode_inst(

    .clk                (clk),

    .rst_n              (rst_n),

    .dec_reset          (dec_reset),            //input

    //global input

    .cs_cache           (cs_cache),             //input [63:0]

    .protected_mode     (protected_mode),       //input

    //eip

    .pr_reset           (pr_reset),             //input

    .prefetch_eip       (prefetch_eip),         //input [31:0]

    .eip                (eip),                  //output [31:0]

    //fetch interface

    .fetch_valid        (fetch_valid),          //input [3:0]

    .fetch              (fetch),                //input [63:0]

    .fetch_limit        (fetch_limit),          //input

    .fetch_page_fault   (fetch_page_fault),     //input

    .dec_acceptable     (dec_acceptable),       //output [3:0]

    //exceptions

    .dec_gp_fault       (dec_gp_fault),         //output

    .dec_ud_fault       (dec_ud_fault),         //output

    .dec_pf_fault       (dec_pf_fault),         //output

    //pipeline

    .micro_busy                 (micro_busy),               //input

    .dec_ready                  (dec_ready),                //output

    .decoder                    (decoder),                  //output [95:0]

    .dec_eip                    (dec_eip),                  //output [31:0]

    .dec_operand_32bit          (dec_operand_32bit),        //output

    .dec_address_32bit          (dec_address_32bit),        //output

    .dec_prefix_group_1_rep     (dec_prefix_group_1_rep),   //output [1:0]

    .dec_prefix_group_1_lock    (dec_prefix_group_1_lock),  //output

    .dec_prefix_group_2_seg     (dec_prefix_group_2_seg),   //output [2:0]

    .dec_prefix_2byte           (dec_prefix_2byte),         //output

    .dec_consumed               (dec_consumed),             //output [3:0]

    .dec_modregrm_len           (dec_modregrm_len),         //output [2:0]

    .dec_is_8bit                (dec_is_8bit),              //output

    .dec_cmd                    (dec_cmd),                  //output [6:0]

    .dec_cmdex                  (dec_cmdex),                //output [3:0]

    .dec_is_complex             (dec_is_complex)            //output

);

//------------------------------------------------------------------------------

wire [31:0] task_eip;

wire        io_allow_check_needed;

wire        rd_busy;

wire        micro_ready;

wire [87:0] micro_decoder;

wire [31:0] micro_eip;

wire        micro_operand_32bit;

wire        micro_address_32bit;

wire [1:0]  micro_prefix_group_1_rep;

wire        micro_prefix_group_1_lock;

wire [2:0]  micro_prefix_group_2_seg;

wire        micro_prefix_2byte;

wire [3:0]  micro_consumed;

wire [2:0]  micro_modregrm_len;

wire        micro_is_8bit;

wire [3:0]  micro_cmdex;

microcode microcode_inst(

    .clk                (clk),

    .rst_n              (rst_n),

    .micro_reset        (micro_reset), //input

    .exc_init                      (exc_init),                      //input

    .exc_load                      (exc_load),                      //input

    .exc_eip                       (exc_eip),                       //input [31:0]

    .task_eip                      (task_eip),                      //input [31:0]

    //command control

    .real_mode                     (real_mode),                     //input

    .v8086_mode                    (v8086_mode),                    //input

    .protected_mode                (protected_mode),                //input

    .io_allow_check_needed         (io_allow_check_needed),         //input

    .exc_push_error                (exc_push_error),                //input

    .cr0_pg                        (cr0_pg),                        //input

    .oflag                         (oflag),                         //input

    .ntflag                        (ntflag),                        //input

    .cpl                           (cpl),                           //input [1:0]

    .glob_param_1                  (glob_param_1),                  //input [31:0]

    .glob_param_3                  (glob_param_3),                  //input [31:0]

    .glob_descriptor               (glob_descriptor),               //input [63:0]

    //decoder

    .micro_busy                    (micro_busy),                    //output

    .dec_ready                     (dec_ready),                     //input

    .decoder                       (decoder),                       //input [95:0]

    .dec_eip                       (dec_eip),                       //input [31:0]

    .dec_operand_32bit             (dec_operand_32bit),             //input

    .dec_address_32bit             (dec_address_32bit),             //input

    .dec_prefix_group_1_rep        (dec_prefix_group_1_rep),        //input [1:0]

    .dec_prefix_group_1_lock       (dec_prefix_group_1_lock),       //input

    .dec_prefix_group_2_seg        (dec_prefix_group_2_seg),        //input [2:0]

    .dec_prefix_2byte              (dec_prefix_2byte),              //input

    .dec_consumed                  (dec_consumed),                  //input [3:0]

    .dec_modregrm_len              (dec_modregrm_len),              //input [2:0]

    .dec_is_8bit                   (dec_is_8bit),                   //input

    .dec_cmd                       (dec_cmd),                       //input [6:0]

    .dec_cmdex                     (dec_cmdex),                     //input [3:0]

    .dec_is_complex                (dec_is_complex),                //input

    //micro

    .rd_busy                       (rd_busy),                       //input

    .micro_ready                   (micro_ready),                   //output

    .micro_decoder                 (micro_decoder),                 //output [87:0]

    .micro_eip                     (micro_eip),                     //output [31:0]

    .micro_operand_32bit           (micro_operand_32bit),           //output

    .micro_address_32bit           (micro_address_32bit),           //output

    .micro_prefix_group_1_rep      (micro_prefix_group_1_rep),      //output [1:0]

    .micro_prefix_group_1_lock     (micro_prefix_group_1_lock),     //output

    .micro_prefix_group_2_seg      (micro_prefix_group_2_seg),      //output [2:0]

    .micro_prefix_2byte            (micro_prefix_2byte),            //output

    .micro_consumed                (micro_consumed),                //output [3:0]

    .micro_modregrm_len            (micro_modregrm_len),            //output [2:0]

    .micro_is_8bit                 (micro_is_8bit),                 //output

    .micro_cmd                     (micro_cmd),                     //output [6:0]

    .micro_cmdex                   (micro_cmdex)                    //output [3:0]

);

//------------------------------------------------------------------------------

wire [2:0]  debug_len0;

wire [2:0]  debug_len1;

wire [2:0]  debug_len2;

wire [2:0]  debug_len3;

wire [10:0] exe_mutex;

wire [10:0] wr_mutex;

wire [31:0] wr_esp_prev;

wire        exe_busy;

wire        rd_ready;

wire [87:0] rd_decoder;

wire        rd_operand_32bit;

wire        rd_address_32bit;