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alfik |
/*
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* Copyright (c) 2014, Aleksander Osman
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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`include "defines.v"
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module read_effective_address(
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input clk,
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input rst_n,
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input rd_reset,
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input rd_address_effective_do,
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input rd_ready,
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//general input
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input [31:0] eax,
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input [31:0] ebx,
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input [31:0] ecx,
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input [31:0] edx,
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input [31:0] esp,
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input [31:0] ebp,
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input [31:0] esi,
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input [31:0] edi,
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input [63:0] ss_cache,
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input [31:0] glob_param_3,
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input [31:0] wr_esp_prev,
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//rd input
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input rd_address_16bit,
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input rd_address_32bit,
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input rd_operand_16bit,
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input rd_operand_32bit,
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input [87:0] rd_decoder,
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input [2:0] rd_modregrm_rm,
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input [2:0] rd_modregrm_reg,
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input [1:0] rd_modregrm_mod,
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input [7:0] rd_sib,
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//address control
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input address_enter_init,
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input address_enter,
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input address_enter_last,
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input address_leave,
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input address_esi,
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input address_edi,
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input address_xlat_transform,
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input address_bits_transform,
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input address_stack_pop,
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input address_stack_pop_speedup,
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input address_stack_pop_next,
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input address_stack_pop_esp_prev,
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input address_stack_pop_for_call,
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input address_stack_save,
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input address_stack_add_4_to_saved,
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input address_stack_for_ret_first,
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input address_stack_for_ret_second,
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input address_stack_for_iret_first,
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input address_stack_for_iret_second,
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input address_stack_for_iret_third,
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input address_stack_for_iret_last,
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input address_stack_for_iret_to_v86,
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input address_stack_for_call_param_first,
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input address_ea_buffer,
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input address_ea_buffer_plus_2,
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input address_memoffset,
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//output
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output reg rd_address_effective_ready,
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output reg [31:0] rd_address_effective
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);
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//------------------------------------------------------------------------------ modregrm
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wire [15:0] address_disp16;
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wire [15:0] base16;
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wire [15:0] disp16;
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wire [15:0] base16_plus_disp16;
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wire [31:0] address_disp32_no_sib;
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wire [31:0] address_disp32_sib;
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wire [31:0] address_disp32;
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wire [31:0] sib_base32;
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wire [31:0] sib_index32;
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wire [31:0] sib_index32_scaled;
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wire [31:0] sib_base32_plus_index32_scaled;
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wire [31:0] base32;
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wire [31:0] disp32;
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wire [31:0] base32_plus_disp32;
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wire [31:0] address_effective_modrm;
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//------------------------------------------------------------------------------ modregrm 16-bit
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assign address_disp16 = rd_decoder[31:16];
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assign base16 =
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(rd_modregrm_rm == 3'b000)? ebx[15:0] + esi[15:0] :
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(rd_modregrm_rm == 3'b001)? ebx[15:0] + edi[15:0] :
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(rd_modregrm_rm == 3'b010)? ebp[15:0] + esi[15:0] :
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(rd_modregrm_rm == 3'b011)? ebp[15:0] + edi[15:0] :
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(rd_modregrm_rm == 3'b100)? esi[15:0] :
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(rd_modregrm_rm == 3'b101)? edi[15:0] :
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(rd_modregrm_rm == 3'b110)? ebp[15:0] :
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ebx[15:0];
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assign disp16 =
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(rd_modregrm_mod == 2'b10)? address_disp16 :
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(rd_modregrm_mod == 2'b01)? { {8{address_disp16[7]}}, address_disp16[7:0] } :
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16'd0;
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assign base16_plus_disp16 = base16 + disp16;
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//------------------------------------------------------------------------------ modregrm 32-bit
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assign address_disp32_no_sib = rd_decoder[47:16];
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assign address_disp32_sib = rd_decoder[55:24];
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assign address_disp32 = (rd_modregrm_rm == 3'b100)? address_disp32_sib : address_disp32_no_sib;
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assign sib_base32 =
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(rd_sib[2:0] == 3'b000)? eax :
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(rd_sib[2:0] == 3'b001)? ecx :
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(rd_sib[2:0] == 3'b010)? edx :
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(rd_sib[2:0] == 3'b011)? ebx :
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(rd_sib[2:0] == 3'b100)? esp :
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(rd_sib[2:0] == 3'b101 && rd_modregrm_mod == 2'b00)? address_disp32_sib :
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(rd_sib[2:0] == 3'b101)? ebp :
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(rd_sib[2:0] == 3'b110)? esi :
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edi;
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assign sib_index32 =
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(rd_sib[5:3] == 3'b000)? eax :
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(rd_sib[5:3] == 3'b001)? ecx :
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(rd_sib[5:3] == 3'b010)? edx :
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(rd_sib[5:3] == 3'b011)? ebx :
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(rd_sib[5:3] == 3'b100)? 32'd0 :
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(rd_sib[5:3] == 3'b101)? ebp :
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(rd_sib[5:3] == 3'b110)? esi :
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edi;
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assign sib_index32_scaled =
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(rd_sib[7:6] == 2'b00)? sib_index32 :
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(rd_sib[7:6] == 2'b01)? { sib_index32[30:0], 1'b0 } :
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(rd_sib[7:6] == 2'b10)? { sib_index32[29:0], 2'b0 } :
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{ sib_index32[28:0], 3'b0 };
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assign sib_base32_plus_index32_scaled = sib_base32 + sib_index32_scaled;
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assign base32 =
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(rd_modregrm_rm == 3'b000)? eax :
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(rd_modregrm_rm == 3'b001)? ecx :
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(rd_modregrm_rm == 3'b010)? edx :
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(rd_modregrm_rm == 3'b011)? ebx :
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(rd_modregrm_rm == 3'b100)? sib_base32_plus_index32_scaled :
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(rd_modregrm_rm == 3'b101)? ebp :
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(rd_modregrm_rm == 3'b110)? esi :
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edi;
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assign disp32 =
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(rd_modregrm_mod == 2'b10)? address_disp32 :
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(rd_modregrm_mod == 2'b01)? { {24{address_disp32[7]}}, address_disp32[7:0] } :
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32'd0;
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assign base32_plus_disp32 = base32 + disp32;
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//------------------------------------------------------------------------------ modregrm final
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assign address_effective_modrm =
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(rd_address_16bit && rd_modregrm_mod == 2'b00 && rd_modregrm_rm == 3'b110)? { 16'd0, address_disp16 } :
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(rd_address_32bit && rd_modregrm_mod == 2'b00 && rd_modregrm_rm == 3'b101)? address_disp32_no_sib :
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(rd_address_16bit)? { 16'd0, base16_plus_disp16 } :
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base32_plus_disp32;
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------ string
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wire [31:0] esi_offset;
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wire [31:0] edi_offset;
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assign esi_offset = (rd_address_16bit)? { 16'd0, esi[15:0] } : esi;
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assign edi_offset = (rd_address_16bit)? { 16'd0, edi[15:0] } : edi;
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//------------------------------------------------------------------------------ stack pop
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wire [31:0] pop_next;
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wire [31:0] pop_offset_speedup_next;
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wire [31:0] pop_offset;
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reg [31:0] pop_offset_speedup;
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assign pop_next =
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(address_stack_pop_speedup && rd_operand_16bit)? pop_offset_speedup + 32'd2 :
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(address_stack_pop_speedup)? pop_offset_speedup + 32'd4 :
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(rd_operand_16bit)? esp + 32'd2 :
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esp + 32'd4;
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assign pop_offset_speedup_next = (ss_cache[`DESC_BIT_D_B])? pop_next : { 16'd0, pop_next[15:0] };
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) pop_offset_speedup <= 32'd0;
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else if(rd_ready) pop_offset_speedup <= pop_offset_speedup_next;
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end
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assign pop_offset =
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(address_stack_pop_speedup)? pop_offset_speedup :
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(ss_cache[`DESC_BIT_D_B])? esp :
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{ 16'd0, esp[15:0] };
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//------------------------------------------------------------------------------ stack pop for ret
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wire [31:0] stack_initial;
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wire [31:0] stack;
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wire [31:0] stack_for_ret_first;
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wire [31:0] stack_for_ret_second_imm_offset;
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wire [31:0] stack_for_ret_second;
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wire [31:0] stack_for_iret_first;
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wire [31:0] stack_for_iret_second;
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wire [31:0] stack_for_iret_third;
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wire [31:0] stack_for_iret_to_v86;
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wire [31:0] stack_for_call_param_first;
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wire [31:0] stack_next;
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reg [31:0] stack_saved;
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wire [31:0] stack_offset;
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wire [4:0] call_gate_param;
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assign stack_initial =
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(address_stack_pop_esp_prev)? wr_esp_prev :
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esp;
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assign stack =
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(ss_cache[`DESC_BIT_D_B])? stack_initial :
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{ 16'd0, stack_initial[15:0] };
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assign stack_for_ret_first =
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(rd_operand_16bit)? stack + 32'd2 :
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stack + 32'd4;
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assign stack_for_ret_second_imm_offset =
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(rd_decoder[0] == 1'b0)? { 16'd0, rd_decoder[23:8] } :
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32'd0;
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assign stack_for_ret_second =
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(rd_operand_16bit)? stack + 32'd6 + stack_for_ret_second_imm_offset :
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stack + 32'd12 + stack_for_ret_second_imm_offset;
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assign stack_for_iret_first =
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(rd_operand_16bit)? stack + 32'd4 :
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stack + 32'd8;
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assign stack_for_iret_second =
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288 |
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(rd_operand_16bit)? stack + 32'd8 :
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stack + 32'd16;
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290 |
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291 |
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assign stack_for_iret_third =
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(rd_operand_16bit)? stack + 32'd6 :
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293 |
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stack + 32'd12;
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294 |
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295 |
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assign stack_for_iret_to_v86 = stack + 32'd12;
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296 |
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297 |
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assign call_gate_param = glob_param_3[24:20] - 5'd1;
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299 |
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300 |
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assign stack_for_call_param_first =
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(~(glob_param_3[19]))? stack + { 26'd0, call_gate_param, 1'b0 } :
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stack + { 25'd0, call_gate_param, 2'b0 };
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303 |
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assign stack_next =
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(address_stack_pop_for_call && ~(glob_param_3[19]))? stack_saved - 32'd2 :
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(address_stack_pop_for_call)? stack_saved - 32'd4 :
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(rd_operand_16bit)? stack_saved - 32'd2 :
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stack_saved - 32'd4;
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309 |
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310 |
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always @(posedge clk or negedge rst_n) begin
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311 |
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if(rst_n == 1'b0) stack_saved <= 32'd0;
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else if(rd_ready && address_stack_add_4_to_saved) stack_saved <= stack_saved + 32'd4;
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else if(rd_ready) stack_saved <= stack_next;
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else if(address_stack_save) stack_saved <= stack_offset;
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end
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316 |
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assign stack_offset =
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318 |
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(address_stack_for_ret_first)? stack_for_ret_first :
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319 |
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(address_stack_for_ret_second)? stack_for_ret_second :
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320 |
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(address_stack_for_iret_first)? stack_for_iret_first :
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321 |
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(address_stack_for_iret_second)? stack_for_iret_second :
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322 |
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(address_stack_for_iret_third)? stack_for_iret_third :
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(address_stack_for_iret_last)? stack :
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324 |
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(address_stack_for_iret_to_v86)? stack_for_iret_to_v86 :
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325 |
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(address_stack_for_call_param_first)? stack_for_call_param_first :
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326 |
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stack_saved;
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327 |
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328 |
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//------------------------------------------------------------------------------ XLAT
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329 |
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330 |
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wire [31:0] xlat_offset;
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331 |
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332 |
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assign xlat_offset = ebx + { 24'b0, eax[7:0] };
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333 |
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334 |
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//------------------------------------------------------------------------------ LEAVE
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335 |
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336 |
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wire [31:0] ebp_for_leave_offset;
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337 |
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338 |
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assign ebp_for_leave_offset = (ss_cache[`DESC_BIT_D_B])? ebp : { 16'd0, ebp[15:0] };
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339 |
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340 |
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//------------------------------------------------------------------------------ bit operations
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341 |
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342 |
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wire [31:0] address_bits_transform_reg;
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343 |
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wire [31:0] address_bits_transform_sum;
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344 |
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345 |
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assign address_bits_transform_reg =
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346 |
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(rd_modregrm_reg == 3'b000)? eax :
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347 |
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(rd_modregrm_reg == 3'b001)? ecx :
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348 |
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(rd_modregrm_reg == 3'b010)? edx :
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349 |
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(rd_modregrm_reg == 3'b011)? ebx :
|
350 |
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(rd_modregrm_reg == 3'b100)? esp :
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351 |
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(rd_modregrm_reg == 3'b101)? ebp :
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352 |
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(rd_modregrm_reg == 3'b110)? esi :
|
353 |
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edi;
|
354 |
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|
355 |
|
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assign address_bits_transform_sum =
|
356 |
|
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(rd_operand_32bit)? address_effective_modrm + { { 3{address_bits_transform_reg[31]}}, address_bits_transform_reg[31:5], 2'b0 } :
|
357 |
|
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address_effective_modrm + { {19{address_bits_transform_reg[15]}}, address_bits_transform_reg[15:4], 1'b0 };
|
358 |
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|
359 |
|
|
//------------------------------------------------------------------------------ ENTER
|
360 |
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|
361 |
|
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wire [31:0] ebp_for_enter_next;
|
362 |
|
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wire [31:0] ebp_for_enter_offset;
|
363 |
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|
364 |
|
|
reg [31:0] ebp_for_enter;
|
365 |
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|
366 |
|
|
wire [31:0] esp_for_enter_next;
|
367 |
|
|
wire [31:0] esp_for_enter_offset;
|
368 |
|
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|
369 |
|
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|
370 |
|
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assign ebp_for_enter_next = (rd_operand_16bit)? ebp_for_enter - 32'd2 : ebp_for_enter - 32'd4;
|
371 |
|
|
assign ebp_for_enter_offset = (ss_cache[`DESC_BIT_D_B])? ebp_for_enter_next : { 16'd0, ebp_for_enter_next[15:0] };
|
372 |
|
|
|
373 |
|
|
always @(posedge clk or negedge rst_n) begin
|
374 |
|
|
if(rst_n == 1'b0) ebp_for_enter <= 32'd0;
|
375 |
|
|
else if(address_enter_init) ebp_for_enter <= ebp;
|
376 |
|
|
else if(rd_ready) ebp_for_enter <= ebp_for_enter_offset;
|
377 |
|
|
end
|
378 |
|
|
|
379 |
|
|
assign esp_for_enter_next = esp - { 16'd0, rd_decoder[23:8] };
|
380 |
|
|
assign esp_for_enter_offset = (ss_cache[`DESC_BIT_D_B])? esp_for_enter_next : { 16'd0, esp_for_enter_next[15:0] };
|
381 |
|
|
|
382 |
|
|
//------------------------------------------------------------------------------ ea buffer
|
383 |
|
|
|
384 |
|
|
wire [31:0] ea_buffer_sum;
|
385 |
|
|
wire [31:0] ea_buffer_next;
|
386 |
|
|
|
387 |
|
|
reg [31:0] ea_buffer;
|
388 |
|
|
|
389 |
|
|
assign ea_buffer_sum =
|
390 |
|
|
(rd_operand_16bit || address_ea_buffer_plus_2)? rd_address_effective + 32'd2 :
|
391 |
|
|
rd_address_effective + 32'd4;
|
392 |
|
|
|
393 |
|
|
assign ea_buffer_next = (rd_address_16bit)? { 16'd0, ea_buffer_sum[15:0] } : ea_buffer_sum;
|
394 |
|
|
|
395 |
|
|
always @(posedge clk or negedge rst_n) begin
|
396 |
|
|
if(rst_n == 1'b0) ea_buffer <= 32'd0;
|
397 |
|
|
else if(rd_ready && rd_address_effective_ready) ea_buffer <= ea_buffer_next;
|
398 |
|
|
end
|
399 |
|
|
|
400 |
|
|
//------------------------------------------------------------------------------ final effective address
|
401 |
|
|
|
402 |
|
|
always @(posedge clk or negedge rst_n) begin
|
403 |
|
|
if(rst_n == 1'b0) rd_address_effective_ready <= `FALSE;
|
404 |
|
|
else if(rd_ready || rd_reset) rd_address_effective_ready <= `FALSE;
|
405 |
|
|
else if(rd_address_effective_do) rd_address_effective_ready <= `TRUE;
|
406 |
|
|
end
|
407 |
|
|
|
408 |
|
|
always @(posedge clk or negedge rst_n) begin
|
409 |
|
|
if(rst_n == 1'b0) rd_address_effective <= 32'd0;
|
410 |
|
|
else if(address_memoffset && rd_address_16bit) rd_address_effective <= { 16'd0, rd_decoder[23:8] };
|
411 |
|
|
else if(address_memoffset && rd_address_32bit) rd_address_effective <= rd_decoder[39:8];
|
412 |
|
|
else if(address_ea_buffer) rd_address_effective <= ea_buffer;
|
413 |
|
|
else if(address_enter) rd_address_effective <= ebp_for_enter_offset;
|
414 |
|
|
else if(address_enter_last) rd_address_effective <= esp_for_enter_offset;
|
415 |
|
|
else if(address_leave) rd_address_effective <= ebp_for_leave_offset;
|
416 |
|
|
else if(address_esi) rd_address_effective <= esi_offset;
|
417 |
|
|
else if(address_edi) rd_address_effective <= edi_offset;
|
418 |
|
|
else if(address_stack_pop) rd_address_effective <= pop_offset;
|
419 |
|
|
else if(address_stack_pop_next) rd_address_effective <= stack_offset;
|
420 |
|
|
else if(address_xlat_transform) rd_address_effective <= { {16{rd_address_32bit}} & xlat_offset[31:16], xlat_offset[15:0] };
|
421 |
|
|
else if(address_bits_transform) rd_address_effective <= { {16{rd_address_32bit}} & address_bits_transform_sum[31:16], address_bits_transform_sum[15:0] };
|
422 |
|
|
else rd_address_effective <= address_effective_modrm;
|
423 |
|
|
end
|
424 |
|
|
|
425 |
|
|
//------------------------------------------------------------------------------
|
426 |
|
|
|
427 |
|
|
// synthesis translate_off
|
428 |
|
|
wire _unused_ok = &{ 1'b0, ss_cache[63:55], ss_cache[53:0], glob_param_3[31:25], glob_param_3[18:0], rd_decoder[87:56], rd_decoder[7:1], address_bits_transform_reg[3:0], 1'b0 };
|
429 |
|
|
// synthesis translate_on
|
430 |
|
|
|
431 |
|
|
//------------------------------------------------------------------------------
|
432 |
|
|
|
433 |
|
|
endmodule
|