OpenCores
URL https://opencores.org/ocsvn/ao486/ao486/trunk

Subversion Repositories ao486

[/] [ao486/] [trunk/] [rtl/] [ao486/] [pipeline/] [read_mutex.v] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 alfik 
/*
2 
 * Copyright (c) 2014, Aleksander Osman
3 
 * All rights reserved.
4 
 *
5 
 * Redistribution and use in source and binary forms, with or without
6 
 * modification, are permitted provided that the following conditions are met:
7 
 *
8 
 * * Redistributions of source code must retain the above copyright notice, this
9 
 *   list of conditions and the following disclaimer.
10 
 *
11 
 * * Redistributions in binary form must reproduce the above copyright notice,
12 
 *   this list of conditions and the following disclaimer in the documentation
13 
 *   and/or other materials provided with the distribution.
14 
 *
15 
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
19 
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
22 
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
24 
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 
 */
26 
 
27 
`include "defines.v"
28 
 
29 
module read_mutex(
30 
    input           rd_req_memory,
31 
    input           rd_req_eflags,
32 
 
33 
    input           rd_req_all,
34 
    input           rd_req_reg,
35 
    input           rd_req_rm,
36 
    input           rd_req_implicit_reg,
37 
    input           rd_req_reg_not_8bit,
38 
    input           rd_req_edi,
39 
    input           rd_req_esi,
40 
    input           rd_req_ebp,
41 
    input           rd_req_esp,
42 
    input           rd_req_ebx,
43 
    input           rd_req_edx_eax,
44 
    input           rd_req_edx,
45 
    input           rd_req_ecx,
46 
    input           rd_req_eax,
47 
 
48 
    input   [87:0]  rd_decoder,
49 
    input           rd_is_8bit,
50 
    input   [1:0]   rd_modregrm_mod,
51 
    input   [2:0]   rd_modregrm_reg,
52 
    input   [2:0]   rd_modregrm_rm,
53 
    input           rd_address_16bit,
54 
    input           rd_address_32bit,
55 
    input   [7:0]   rd_sib,
56 
 
57 
    input   [10:0]  exe_mutex,
58 
    input   [10:0]  wr_mutex,
59 
 
60 
    input           address_bits_transform,
61 
    input           address_xlat_transform,
62 
    input           address_stack_pop,
63 
    input           address_stack_pop_next,
64 
    input           address_enter,
65 
    input           address_enter_last,
66 
    input           address_leave,
67 
    input           address_esi,
68 
    input           address_edi,
69 
 
70 
    output  [10:0]  rd_mutex_next,
71 
 
72 
    output          rd_mutex_busy_active,
73 
    output          rd_mutex_busy_memory,
74 
    output          rd_mutex_busy_eflags,
75 
    output          rd_mutex_busy_ebp,
76 
    output          rd_mutex_busy_esp,
77 
    output          rd_mutex_busy_edx,
78 
    output          rd_mutex_busy_ecx,
79 
    output          rd_mutex_busy_eax,
80 
    output          rd_mutex_busy_modregrm_reg,
81 
    output          rd_mutex_busy_modregrm_rm,
82 
    output          rd_mutex_busy_implicit_reg,
83 
 
84 
    output          rd_address_waiting
85 
);
86 
 
87 
//------------------------------------------------------------------------------
88 
 
89 
wire [10:0] rd_mutex_current;
90 
 
91 
//------------------------------------------------------------------------------
92 
 
93 
//------------------------------------------------------------------------------
94 
 
95 
assign rd_mutex_next = {
96 
    `TRUE, // active bit
97 
    rd_req_memory,
98 
    rd_req_eflags,
99 
 
100 
    (rd_req_reg & (rd_modregrm_reg == 3'd7 & ~(rd_is_8bit))) |
101 
    (rd_req_rm  & (rd_modregrm_rm  == 3'd7 & ~(rd_is_8bit))) |
102 
    (rd_req_implicit_reg & rd_decoder[2:0] == 3'd7 & ~(rd_is_8bit)) | rd_req_all | rd_req_edi |
103 
    (rd_req_reg_not_8bit && rd_modregrm_reg == 3'd7),
104 
 
105 
    (rd_req_reg & (rd_modregrm_reg == 3'd6 & ~(rd_is_8bit))) |
106 
    (rd_req_rm  & (rd_modregrm_rm  == 3'd6 & ~(rd_is_8bit))) |
107 
    (rd_req_implicit_reg & rd_decoder[2:0] == 3'd6 & ~(rd_is_8bit)) | rd_req_all | rd_req_esi |
108 
    (rd_req_reg_not_8bit && rd_modregrm_reg == 3'd6),
109 
 
110 
    (rd_req_reg & (rd_modregrm_reg == 3'd5 & ~(rd_is_8bit))) |
111 
    (rd_req_rm  & (rd_modregrm_rm  == 3'd5 & ~(rd_is_8bit))) |
112 
    (rd_req_implicit_reg & rd_decoder[2:0] == 3'd5 & ~(rd_is_8bit)) | rd_req_all | rd_req_ebp |
113 
    (rd_req_reg_not_8bit && rd_modregrm_reg == 3'd5),
114 
 
115 
    (rd_req_reg & (rd_modregrm_reg == 3'd4 & ~(rd_is_8bit))) |
116 
    (rd_req_rm  & (rd_modregrm_rm  == 3'd4 & ~(rd_is_8bit))) |
117 
    (rd_req_implicit_reg & rd_decoder[2:0] == 3'd4 & ~(rd_is_8bit)) | rd_req_esp | rd_req_all |
118 
    (rd_req_reg_not_8bit && rd_modregrm_reg == 3'd4),
119 
 
120 
    (rd_req_reg & (rd_modregrm_reg == 3'd3 | (rd_modregrm_reg == 3'd7 & rd_is_8bit))) |
121 
    (rd_req_rm  & (rd_modregrm_rm  == 3'd3 | (rd_modregrm_rm  == 3'd7 & rd_is_8bit))) |
122 
    (rd_req_implicit_reg & (rd_decoder[2:0] == 3'd3 | (rd_decoder[2:0] == 3'd7 & rd_is_8bit))) | rd_req_ebx | rd_req_all |
123 
    (rd_req_reg_not_8bit && rd_modregrm_reg == 3'd3),
124 
 
125 
    (rd_req_reg & (rd_modregrm_reg == 3'd2 | (rd_modregrm_reg == 3'd6 & rd_is_8bit))) |
126 
    (rd_req_rm  & (rd_modregrm_rm  == 3'd2 | (rd_modregrm_rm  == 3'd6 & rd_is_8bit))) | rd_req_edx | rd_req_edx_eax |
127 
    (rd_req_implicit_reg & (rd_decoder[2:0] == 3'd2 | (rd_decoder[2:0] == 3'd6 & rd_is_8bit))) | rd_req_all |
128 
    (rd_req_reg_not_8bit && rd_modregrm_reg == 3'd2),
129 
 
130 
    (rd_req_reg & (rd_modregrm_reg == 3'd1 | (rd_modregrm_reg == 3'd5 & rd_is_8bit))) |
131 
    (rd_req_rm  & (rd_modregrm_rm  == 3'd1 | (rd_modregrm_rm  == 3'd5 & rd_is_8bit))) |
132 
    (rd_req_implicit_reg & (rd_decoder[2:0] == 3'd1 | (rd_decoder[2:0] == 3'd5 & rd_is_8bit))) | rd_req_ecx | rd_req_all |
133 
    (rd_req_reg_not_8bit && rd_modregrm_reg == 3'd1),
134 
 
135 
    (rd_req_reg & (rd_modregrm_reg == 3'd0 | (rd_modregrm_reg == 3'd4 & rd_is_8bit))) |
136 
    (rd_req_rm  & (rd_modregrm_rm  == 3'd0 | (rd_modregrm_rm  == 3'd4 & rd_is_8bit))) | rd_req_eax | rd_req_edx_eax |
137 
    (rd_req_implicit_reg & (rd_decoder[2:0] == 3'd0 | (rd_decoder[2:0] == 3'd4 & rd_is_8bit)))  | rd_req_all |
138 
    (rd_req_reg_not_8bit && rd_modregrm_reg == 3'd0)
139 
};
140 
 
141 
assign rd_mutex_current      = exe_mutex | wr_mutex;
142 
 
143 
assign rd_mutex_busy_active   = rd_mutex_current[`MUTEX_ACTIVE_BIT];
144 
assign rd_mutex_busy_memory   = rd_mutex_current[9];
145 
assign rd_mutex_busy_eflags   = rd_mutex_current[8];
146 
assign rd_mutex_busy_ebp      = rd_mutex_current[5];
147 
assign rd_mutex_busy_esp      = rd_mutex_current[4];
148 
assign rd_mutex_busy_edx      = rd_mutex_current[2];
149 
assign rd_mutex_busy_ecx      = rd_mutex_current[1];
150 
assign rd_mutex_busy_eax      = rd_mutex_current[0];
151 
 
152 
assign rd_mutex_busy_modregrm_reg =
153 
    (rd_modregrm_reg == 3'd0 & rd_mutex_current[0]) ||
154 
    (rd_modregrm_reg == 3'd1 & rd_mutex_current[1]) ||
155 
    (rd_modregrm_reg == 3'd2 & rd_mutex_current[2]) ||
156 
    (rd_modregrm_reg == 3'd3 & rd_mutex_current[3]) ||
157 
    (rd_modregrm_reg == 3'd4 & rd_mutex_current[4] & ~(rd_is_8bit)) ||
158 
    (rd_modregrm_reg == 3'd5 & rd_mutex_current[5] & ~(rd_is_8bit)) ||
159 
    (rd_modregrm_reg == 3'd6 & rd_mutex_current[6] & ~(rd_is_8bit)) ||
160 
    (rd_modregrm_reg == 3'd7 & rd_mutex_current[7] & ~(rd_is_8bit)) ||
161 
    (rd_modregrm_reg == 3'd4 & rd_mutex_current[0] & rd_is_8bit) ||
162 
    (rd_modregrm_reg == 3'd5 & rd_mutex_current[1] & rd_is_8bit) ||
163 
    (rd_modregrm_reg == 3'd6 & rd_mutex_current[2] & rd_is_8bit) ||
164 
    (rd_modregrm_reg == 3'd7 & rd_mutex_current[3] & rd_is_8bit);
165 
 
166 
assign rd_mutex_busy_modregrm_rm =
167 
    (rd_modregrm_rm == 3'd0 & rd_mutex_current[0]) ||
168 
    (rd_modregrm_rm == 3'd1 & rd_mutex_current[1]) ||
169 
    (rd_modregrm_rm == 3'd2 & rd_mutex_current[2]) ||
170 
    (rd_modregrm_rm == 3'd3 & rd_mutex_current[3]) ||
171 
    (rd_modregrm_rm == 3'd4 & rd_mutex_current[4] & ~(rd_is_8bit)) ||
172 
    (rd_modregrm_rm == 3'd5 & rd_mutex_current[5] & ~(rd_is_8bit)) ||
173 
    (rd_modregrm_rm == 3'd6 & rd_mutex_current[6] & ~(rd_is_8bit)) ||
174 
    (rd_modregrm_rm == 3'd7 & rd_mutex_current[7] & ~(rd_is_8bit)) ||
175 
    (rd_modregrm_rm == 3'd4 & rd_mutex_current[0] & rd_is_8bit) ||
176 
    (rd_modregrm_rm == 3'd5 & rd_mutex_current[1] & rd_is_8bit) ||
177 
    (rd_modregrm_rm == 3'd6 & rd_mutex_current[2] & rd_is_8bit) ||
178 
    (rd_modregrm_rm == 3'd7 & rd_mutex_current[3] & rd_is_8bit);
179 
 
180 
assign rd_mutex_busy_implicit_reg =
181 
    (rd_decoder[2:0] == 3'd0 && rd_mutex_current[0]) ||
182 
    (rd_decoder[2:0] == 3'd1 && rd_mutex_current[1]) ||
183 
    (rd_decoder[2:0] == 3'd2 && rd_mutex_current[2]) ||
184 
    (rd_decoder[2:0] == 3'd3 && rd_mutex_current[3]) ||
185 
    (rd_decoder[2:0] == 3'd4 && rd_mutex_current[4]) ||
186 
    (rd_decoder[2:0] == 3'd5 && rd_mutex_current[5]) ||
187 
    (rd_decoder[2:0] == 3'd6 && rd_mutex_current[6]) ||
188 
    (rd_decoder[2:0] == 3'd7 && rd_mutex_current[7]);
189 
 
190 
//------------------------------------------------------------------------------ Address mutex
191 
wire address_waiting_16bit;
192 
wire address_waiting_32bit_sib;
193 
wire address_waiting_32bit;
194 
wire address_waiting_bits_transform;
195 
 
196 
assign address_waiting_16bit =
197 
    (rd_modregrm_rm == 3'b000 && (rd_mutex_current[`MUTEX_EBX_BIT] || rd_mutex_current[`MUTEX_ESI_BIT])) ||
198 
    (rd_modregrm_rm == 3'b001 && (rd_mutex_current[`MUTEX_EBX_BIT] || rd_mutex_current[`MUTEX_EDI_BIT])) ||
199 
    (rd_modregrm_rm == 3'b010 && (rd_mutex_current[`MUTEX_EBP_BIT] || rd_mutex_current[`MUTEX_ESI_BIT])) ||
200 
    (rd_modregrm_rm == 3'b011 && (rd_mutex_current[`MUTEX_EBP_BIT] || rd_mutex_current[`MUTEX_EDI_BIT])) ||
201 
    (rd_modregrm_rm == 3'b100 && (rd_mutex_current[`MUTEX_ESI_BIT])) ||
202 
    (rd_modregrm_rm == 3'b101 && (rd_mutex_current[`MUTEX_EDI_BIT])) ||
203 
    (rd_modregrm_rm == 3'b110 && (rd_mutex_current[`MUTEX_EBP_BIT])) ||
204 
    (rd_modregrm_rm == 3'b111 && (rd_mutex_current[`MUTEX_EBX_BIT]));
205 
 
206 
assign address_waiting_32bit_sib =
207 
    ((rd_sib[5:3] == 3'b000 || rd_sib[2:0] == 3'b000) && rd_mutex_current[`MUTEX_EAX_BIT]) ||
208 
    ((rd_sib[5:3] == 3'b001 || rd_sib[2:0] == 3'b001) && rd_mutex_current[`MUTEX_ECX_BIT]) ||
209 
    ((rd_sib[5:3] == 3'b010 || rd_sib[2:0] == 3'b010) && rd_mutex_current[`MUTEX_EDX_BIT]) ||
210 
    ((rd_sib[5:3] == 3'b011 || rd_sib[2:0] == 3'b011) && rd_mutex_current[`MUTEX_EBX_BIT]) ||
211 
    (rd_sib[2:0] == 3'b100 && rd_mutex_current[`MUTEX_ESP_BIT]) ||
212 
    ((rd_sib[5:3] == 3'b101 || (rd_sib[2:0] == 3'b101 && rd_modregrm_mod != 2'b00)) && rd_mutex_current[`MUTEX_EBP_BIT]) ||
213 
    ((rd_sib[5:3] == 3'b110 || rd_sib[2:0] == 3'b110) && rd_mutex_current[`MUTEX_ESI_BIT]) ||
214 
    ((rd_sib[5:3] == 3'b111 || rd_sib[2:0] == 3'b111) && rd_mutex_current[`MUTEX_EDI_BIT]);
215 
 
216 
assign address_waiting_32bit =
217 
    (rd_modregrm_rm == 3'b000 && rd_mutex_current[`MUTEX_EAX_BIT]) ||
218 
    (rd_modregrm_rm == 3'b001 && rd_mutex_current[`MUTEX_ECX_BIT]) ||
219 
    (rd_modregrm_rm == 3'b010 && rd_mutex_current[`MUTEX_EDX_BIT]) ||
220 
    (rd_modregrm_rm == 3'b011 && rd_mutex_current[`MUTEX_EBX_BIT]) ||
221 
    (rd_modregrm_rm == 3'b100 && address_waiting_32bit_sib) ||
222 
    (rd_modregrm_rm == 3'b101 && rd_mutex_current[`MUTEX_EBP_BIT]) ||
223 
    (rd_modregrm_rm == 3'b110 && rd_mutex_current[`MUTEX_ESI_BIT]) ||
224 
    (rd_modregrm_rm == 3'b111 && rd_mutex_current[`MUTEX_EDI_BIT]);
225 
 
226 
assign address_waiting_bits_transform =
227 
    (rd_modregrm_reg == 3'b000 && rd_mutex_current[`MUTEX_EAX_BIT]) ||
228 
    (rd_modregrm_reg == 3'b001 && rd_mutex_current[`MUTEX_ECX_BIT]) ||
229 
    (rd_modregrm_reg == 3'b010 && rd_mutex_current[`MUTEX_EDX_BIT]) ||
230 
    (rd_modregrm_reg == 3'b011 && rd_mutex_current[`MUTEX_EBX_BIT]) ||
231 
    (rd_modregrm_reg == 3'b100 && rd_mutex_current[`MUTEX_ESP_BIT]) ||
232 
    (rd_modregrm_reg == 3'b101 && rd_mutex_current[`MUTEX_EBP_BIT]) ||
233 
    (rd_modregrm_reg == 3'b110 && rd_mutex_current[`MUTEX_ESI_BIT]) ||
234 
    (rd_modregrm_reg == 3'b111 && rd_mutex_current[`MUTEX_EDI_BIT]);
235 
 
236 
assign rd_address_waiting =
237 
    (address_bits_transform && address_waiting_bits_transform) ||
238 
    (address_xlat_transform && (rd_mutex_current[`MUTEX_EAX_BIT] || rd_mutex_current[`MUTEX_EBX_BIT])) ||
239 
    (address_stack_pop      && rd_mutex_current[`MUTEX_ESP_BIT]) ||
240 
    (address_stack_pop_next && rd_mutex_current[`MUTEX_ESP_BIT]) ||
241 
    (address_enter_last     && rd_mutex_current[`MUTEX_ESP_BIT]) ||
242 
    (address_enter          && rd_mutex_current[`MUTEX_EBP_BIT]) ||
243 
    (address_leave          && rd_mutex_current[`MUTEX_EBP_BIT]) ||
244 
    (address_esi            && rd_mutex_current[`MUTEX_ESI_BIT]) ||
245 
    (address_edi            && rd_mutex_current[`MUTEX_EDI_BIT]) ||
246 
    (rd_address_16bit       && ~(rd_modregrm_mod == 2'b00 && rd_modregrm_rm == 3'b110) && address_waiting_16bit ) ||
247 
    (rd_address_32bit       && ~(rd_modregrm_mod == 2'b00 && rd_modregrm_rm == 3'b101) && address_waiting_32bit );
248 
 
249 
//------------------------------------------------------------------------------
250 
 
251 
// synthesis translate_off
252 
wire _unused_ok = &{ 1'b0, rd_decoder[87:3], rd_sib[7:6], 1'b0 };
253 
// synthesis translate_on
254 
 
255 
//------------------------------------------------------------------------------
256 
 
257 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.