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/*

 * Copyright (c) 2014, Aleksander Osman

 * All rights reserved.

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions are met:

 *

 * * Redistributions of source code must retain the above copyright notice, this

 *   list of conditions and the following disclaimer.

 *

 * * Redistributions in binary form must reproduce the above copyright notice,

 *   this list of conditions and the following disclaimer in the documentation

 *   and/or other materials provided with the distribution.

 *

 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE

 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR

 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER

 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,

 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */

`include "defines.v"

module write(

    input               clk,

    input               rst_n,

    input               exe_reset,

    input               wr_reset,

    //global input

    input       [63:0]  glob_descriptor,

    input       [63:0]  glob_descriptor_2,

    input       [31:0]  glob_desc_base,

    input       [31:0]  glob_desc_limit,

    input       [31:0]  glob_param_1,

    input       [31:0]  glob_param_2,

    input       [31:0]  glob_param_3,

    input       [31:0]  glob_param_4,

    input       [31:0]  glob_param_5,

    //general input

    input       [31:0]  eip,

    //registers output

    output      [31:0]  gdtr_base,

    output      [15:0]  gdtr_limit,

    output      [31:0]  idtr_base,

    output      [15:0]  idtr_limit,

    //pipeline input

    input       [31:0]  exe_buffer,

    input       [463:0] exe_buffer_shifted,

    input               dr6_bd_set,

    //interrupt input

    input               interrupt_do,

    //exception input

    input               exc_init,

    input               exc_set_rflag,

    input               exc_debug_start,

    input               exc_pf_read,

    input               exc_pf_write,

    input               exc_pf_code,

    input               exc_pf_check,

    input               exc_restore_esp,

    input               exc_push_error,

    input       [31:0]  exc_eip,

    //output

    output              real_mode,

    output              v8086_mode,

    output              protected_mode,

    output      [1:0]   cpl,

    output              io_allow_check_needed,

    output      [2:0]   debug_len0,

    output      [2:0]   debug_len1,

    output      [2:0]   debug_len2,

    output      [2:0]   debug_len3,

    //wr output

    output              wr_is_front,

    output reg          wr_interrupt_possible,

    output              wr_string_in_progress_final,

    output reg          wr_is_esp_speculative,

    output reg  [10:0]  wr_mutex,

    output reg  [31:0]  wr_stack_offset,

    output reg  [31:0]  wr_esp_prev,

    output      [1:0]   wr_task_rpl,

    output reg  [3:0]   wr_consumed,

    //software interrupt

    output              wr_int,

    output              wr_int_soft_int,

    output              wr_int_soft_int_ib,

    output      [7:0]   wr_int_vector,

    output              wr_exception_external_set,

    output              wr_exception_finished,

    output      [15:0]  wr_error_code,

    //wr exception

    output reg          wr_debug_init,

    output              wr_new_push_ss_fault,

    output              wr_string_es_fault,

    output              wr_push_ss_fault,

    //eip control

    output reg  [31:0]  wr_eip,

    //reset request

    output              wr_req_reset_pr,

    output              wr_req_reset_dec,

    output              wr_req_reset_micro,

    output              wr_req_reset_rd,

    output              wr_req_reset_exe,

    //memory page fault

    input       [31:0]  tlb_code_pf_cr2,

    input       [31:0]  tlb_write_pf_cr2,

    input       [31:0]  tlb_read_pf_cr2,

    input       [31:0]  tlb_check_pf_cr2,

    //memory write

    output              write_do,

    input               write_done,

    input               write_page_fault,

    input               write_ac_fault,

    output      [1:0]   write_cpl,

    output      [31:0]  write_address,

    output      [2:0]   write_length,

    output              write_lock,

    output              write_rmw,

    output      [31:0]  write_data,

    //flush tlb

    output              tlbflushall_do,

    //io write

    output              io_write_do,

    output      [15:0]  io_write_address,

    output      [2:0]   io_write_length,

    output      [31:0]  io_write_data,

    input               io_write_done,

    //global write

    output              wr_glob_param_1_set,

    output      [31:0]  wr_glob_param_1_value,

    output              wr_glob_param_3_set,

    output      [31:0]  wr_glob_param_3_value,

    output              wr_glob_param_4_set,

    output      [31:0]  wr_glob_param_4_value,

    //registers output

    output      [31:0]  eax,

    output      [31:0]  ebx,

    output      [31:0]  ecx,

    output      [31:0]  edx,

    output      [31:0]  esi,

    output      [31:0]  edi,

    output      [31:0]  ebp,

    output      [31:0]  esp,

    output              cr0_pe,

    output              cr0_mp,

    output              cr0_em,

    output              cr0_ts,

    output              cr0_ne,

    output              cr0_wp,

    output              cr0_am,

    output              cr0_nw,

    output              cr0_cd,

    output              cr0_pg,

    output      [31:0]  cr2,

    output      [31:0]  cr3,

    output              cflag,

    output              pflag,

    output              aflag,

    output              zflag,

    output              sflag,

    output              oflag,

    output              tflag,

    output              iflag,

    output              dflag,

    output      [1:0]   iopl,

    output              ntflag,

    output              rflag,

    output              vmflag,

    output              acflag,

    output              idflag,

    output      [31:0]  dr0,

    output      [31:0]  dr1,

    output      [31:0]  dr2,

    output      [31:0]  dr3,

    output      [3:0]   dr6_breakpoints,

    output              dr6_b12,

    output              dr6_bd,

    output              dr6_bs,

    output              dr6_bt,

    output      [31:0]  dr7,

    output      [15:0]  es,

    output      [15:0]  ds,

    output      [15:0]  ss,

    output      [15:0]  fs,

    output      [15:0]  gs,

    output      [15:0]  cs,

    output      [15:0]  ldtr,

    output      [15:0]  tr,

    output      [63:0]  es_cache,

    output      [63:0]  ds_cache,

    output      [63:0]  ss_cache,

    output      [63:0]  fs_cache,

    output      [63:0]  gs_cache,

    output      [63:0]  cs_cache,

    output      [63:0]  ldtr_cache,

    output      [63:0]  tr_cache,

    output              es_cache_valid,

    output              ds_cache_valid,

    output              ss_cache_valid,

    output              fs_cache_valid,

    output              gs_cache_valid,

    output              cs_cache_valid,

    output              ldtr_cache_valid,

    output              tr_cache_valid,

    //pipeline wr

    output              wr_busy,

    input               exe_ready,

    input       [39:0]  exe_decoder,

    input       [31:0]  exe_eip_final,

    input               exe_operand_32bit,

    input               exe_address_32bit,

    input       [1:0]   exe_prefix_group_1_rep,

    input               exe_prefix_group_1_lock,

    input       [3:0]   exe_consumed_final,

    input               exe_is_8bit_final,

    input       [6:0]   exe_cmd,

    input       [3:0]   exe_cmdex,

    input       [10:0]  exe_mutex,

    input               exe_dst_is_reg,

    input               exe_dst_is_rm,

    input               exe_dst_is_memory,

    input               exe_dst_is_eax,

    input               exe_dst_is_edx_eax,

    input               exe_dst_is_implicit_reg,

    input       [31:0]  exe_linear,

    input       [3:0]   exe_debug_read,

    input       [31:0]  exe_result,

    input       [31:0]  exe_result2,

    input       [31:0]  exe_result_push,

    input       [4:0]   exe_result_signals,

    input       [3:0]   exe_arith_index,

    input               exe_arith_sub_carry,

    input               exe_arith_add_carry,

    input               exe_arith_adc_carry,

    input               exe_arith_sbb_carry,

    input       [31:0]  src_final,

    input       [31:0]  dst_final,

    input               exe_mult_overflow,

    input       [31:0]  exe_stack_offset

);

//------------------------------------------------------------------------------

wire [31:0] tr_base;

wire [31:0] cs_base;

wire [31:0] cs_limit;

wire [31:0] es_base;

wire [31:0] es_limit;

wire [31:0] ss_base;

wire [31:0] ss_limit;

wire [31:0] ldtr_base;

assign tr_base     = {   tr_cache[63:56],   tr_cache[39:16] };

assign cs_base     = { cs_cache[63:56], cs_cache[39:16] };

assign cs_limit    = cs_cache[`DESC_BIT_G]? { cs_cache[51:48], cs_cache[15:0], 12'hFFF } : { 12'd0, cs_cache[51:48], cs_cache[15:0] };

assign es_base     = { es_cache[63:56], es_cache[39:16] };

assign es_limit    = es_cache[`DESC_BIT_G]? { es_cache[51:48], es_cache[15:0], 12'hFFF } : { 12'd0, es_cache[51:48], es_cache[15:0] };

assign ss_base     = { ss_cache[63:56], ss_cache[39:16] };

assign ss_limit    = ss_cache[`DESC_BIT_G]? { ss_cache[51:48], ss_cache[15:0], 12'hFFF } : { 12'd0, ss_cache[51:48], ss_cache[15:0] };

assign ldtr_base   = { ldtr_cache[63:56], ldtr_cache[39:16] };

//------------------------------------------------------------------------------

//------------------------------------------------------------------------------

//------------------------------------------------------------------------------

//------------------------------------------------------------------------------

//------------------------------------------------------------------------------

wire wr_ready;

wire w_load;

wire wr_waiting;

wire wr_one_cycle_wait;

//------------------------------------------------------------------------------

assign wr_ready = ~(wr_waiting) && wr_cmd != `CMD_NULL; //NOTE: do not use: wr_mutex[`MUTEX_ACTIVE_BIT];

assign wr_busy = wr_waiting || exc_init || wr_debug_prepare || wr_interrupt_possible_prepare || (wr_one_cycle_wait && wr_first_cycle);

assign w_load = exe_ready;

assign wr_is_front = wr_cmd != `CMD_NULL;

//------------------------------------------------------------------------------

wire wr_finished;

wire wr_not_finished;

wire wr_hlt_in_progress;

wire wr_inhibit_interrupts_and_debug;

wire wr_inhibit_interrupts;

wire iflag_to_reg;

wire wr_debug_prepare;

wire wr_interrupt_possible_prepare;

wire wr_clear_rflag;

wire wr_string_in_progress;

reg  wr_string_in_progress_last;

assign wr_finished =

    wr_ready && (~(wr_not_finished) || (wr_hlt_in_progress && iflag_to_reg && interrupt_do) || wr_string_in_progress);

assign wr_interrupt_possible_prepare =

    interrupt_do &&

    wr_ready && (~(wr_not_finished) || wr_hlt_in_progress || wr_string_in_progress) &&

    ~(wr_debug_prepare) &&

    ~(wr_inhibit_interrupts_and_debug) && ~(wr_inhibit_interrupts) && iflag_to_reg;

assign wr_clear_rflag = wr_finished && wr_eip <= cs_limit && ~(exc_init) && ~(wr_debug_prepare) && ~(wr_interrupt_possible_prepare);

always @(posedge clk or negedge rst_n) begin

    if(rst_n == 1'b0)   wr_interrupt_possible <= `FALSE;

    else if(wr_reset)   wr_interrupt_possible <= `FALSE;

    else                wr_interrupt_possible <= wr_interrupt_possible_prepare;

end

always @(posedge clk or negedge rst_n) begin

    if(rst_n == 1'b0)   wr_debug_init <= `FALSE;

    else                wr_debug_init <= wr_debug_prepare;

end

always @(posedge clk or negedge rst_n) begin

    if(rst_n == 1'b0)   wr_string_in_progress_last <= `FALSE;

    else                wr_string_in_progress_last <= wr_string_in_progress;

end

assign wr_string_in_progress_final = wr_string_in_progress || ((wr_debug_init || wr_interrupt_possible) && wr_string_in_progress_last);

//------------------------------------------------------------------------------

reg wr_first_cycle;

always @(posedge clk or negedge rst_n) begin

    if(rst_n == 1'b0)   wr_first_cycle <= `FALSE;

    else if(wr_reset)   wr_first_cycle <= `FALSE;

    else if(w_load)     wr_first_cycle <= `TRUE;

    else                wr_first_cycle <= `FALSE;

end

//------------------------------------------------------------------------------

reg [15:0]  wr_decoder;

reg         wr_operand_32bit;

reg         wr_address_32bit;

reg [1:0]   wr_prefix_group_1_rep;

reg         wr_prefix_group_1_lock;

reg         wr_is_8bit;

reg [6:0]   wr_cmd;

reg [3:0]   wr_cmdex;

reg         wr_dst_is_reg;

reg         wr_dst_is_rm;

reg         wr_dst_is_memory;

reg         wr_dst_is_eax;

reg         wr_dst_is_edx_eax;

reg         wr_dst_is_implicit_reg;

reg [31:0]  wr_linear;

reg [31:0]  result;

reg [31:0]  result2;

reg [4:0]   result_signals;

reg [31:0]  result_push;

reg [3:0]   wr_arith_index;

reg [31:0]  wr_src;

reg [31:0]  wr_dst;

reg         wr_arith_add_carry;

reg         wr_arith_adc_carry;

reg         wr_arith_sub_carry;

reg         wr_arith_sbb_carry;

reg         wr_mult_overflow;

always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) wr_decoder              <= 16'd0;     else if(w_load) wr_decoder              <= exe_decoder[15:0];        end

always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) wr_eip                  <= 32'd0;     else if(w_load) wr_eip                  <= exe_eip_final;            end

always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) wr_operand_32bit        <= `FALSE;    else if(w_load) wr_operand_32bit        <= exe_operand_32bit;        end

always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) wr_address_32bit        <= `FALSE;    else if(w_load) wr_address_32bit        <= exe_address_32bit;        end

always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) wr_prefix_group_1_rep   <= 2'd0;      else if(w_load) wr_prefix_group_1_rep   <= exe_prefix_group_1_rep;   end

always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) wr_prefix_group_1_lock  <= `FALSE;    else if(w_load) wr_prefix_group_1_lock  <= exe_prefix_group_1_lock;  end

always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) wr_consumed             <= 4'd0;      else if(w_load) wr_consumed             <= exe_consumed_final;       end

always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) wr_is_8bit              <= `FALSE;    else if(w_load) wr_is_8bit              <= exe_is_8bit_final;        end

always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) wr_cmdex                <= 4'd0;      else if(w_load) wr_cmdex                <= exe_cmdex;                end

always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) wr_dst_is_reg           <= `FALSE;    else if(w_load) wr_dst_is_reg           <= exe_dst_is_reg;           end

always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) wr_dst_is_rm            <= `FALSE;    else if(w_load) wr_dst_is_rm            <= exe_dst_is_rm;            end

always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) wr_dst_is_memory        <= `FALSE;    else if(w_load) wr_dst_is_memory        <= exe_dst_is_memory;        end

always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) wr_dst_is_eax           <= `FALSE;    else if(w_load) wr_dst_is_eax           <= exe_dst_is_eax;           end

always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) wr_dst_is_edx_eax       <= `FALSE;    else if(w_load) wr_dst_is_edx_eax       <= exe_dst_is_edx_eax;       end

always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) wr_dst_is_implicit_reg  <= `FALSE;    else if(w_load) wr_dst_is_implicit_reg  <= exe_dst_is_implicit_reg;  end

always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) wr_linear               <= 32'd0;     else if(w_load) wr_linear               <= exe_linear;               end

always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) result                  <= 32'd0;     else if(w_load) result                  <= exe_result;               end

always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) result2                 <= 32'd0;     else if(w_load) result2                 <= exe_result2;              end

always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) result_push             <= 32'd0;     else if(w_load) result_push             <= exe_result_push;          end

always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) result_signals          <= 5'd0;      else if(w_load) result_signals          <= exe_result_signals;       end

always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) wr_arith_index          <= 4'd0;      else if(w_load) wr_arith_index          <= exe_arith_index;          end

always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) wr_src                  <= 32'd0;     else if(w_load) wr_src                  <= src_final;                end

always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) wr_dst                  <= 32'd0;     else if(w_load) wr_dst                  <= dst_final;                end

always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) wr_arith_sub_carry      <= 1'd0;      else if(w_load) wr_arith_sub_carry      <= exe_arith_sub_carry;      end

always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) wr_arith_add_carry      <= 1'd0;      else if(w_load) wr_arith_add_carry      <= exe_arith_add_carry;      end

always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) wr_arith_adc_carry      <= 1'd0;      else if(w_load) wr_arith_adc_carry      <= exe_arith_adc_carry;      end

always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) wr_arith_sbb_carry      <= 1'd0;      else if(w_load) wr_arith_sbb_carry      <= exe_arith_sbb_carry;      end

always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) wr_mult_overflow        <= 1'd0;      else if(w_load) wr_mult_overflow        <= exe_mult_overflow;        end

always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) wr_stack_offset         <= 32'd0;     else if(w_load) wr_stack_offset         <= exe_stack_offset;         end

always @(posedge clk or negedge rst_n) begin

    if(rst_n == 1'b0)   wr_cmd <= `CMD_NULL;

    else if(wr_reset)   wr_cmd <= `CMD_NULL;

    else if(w_load)     wr_cmd <= exe_cmd;

    else if(wr_ready)   wr_cmd <= `CMD_NULL;

end

always @(posedge clk or negedge rst_n) begin

    if(rst_n == 1'b0)                                       wr_mutex <= 11'd0;

    else if(wr_reset)                                       wr_mutex <= 11'd0;

    else if(w_load)                                         wr_mutex <= exe_mutex;

    else if(wr_ready && ~(wr_interrupt_possible_prepare))   wr_mutex <= 11'd0;

end

//------------------------------------------------------------------------------

wire wr_operand_16bit;

wire wr_address_16bit;

wire [1:0] wr_modregrm_mod;

wire [2:0] wr_modregrm_reg;

wire [2:0] wr_modregrm_rm;

assign wr_operand_16bit = ~(wr_operand_32bit);

assign wr_address_16bit = ~(wr_address_32bit);

assign wr_modregrm_mod = wr_decoder[15:14];

assign wr_modregrm_reg = wr_decoder[13:11];

assign wr_modregrm_rm  = wr_decoder[10:8];

//------------------------------------------------------------------------------

wire [31:0] wr_descriptor_touch_offset;

wire [31:0] wr_descriptor_busy_tss_offset;

assign wr_descriptor_touch_offset =

    (glob_param_1[2] == 1'b0)?   gdtr_base + { 16'd0, glob_param_1[15:3], 3'd0 } + 32'd5 :

                                 ldtr_base + { 16'd0, glob_param_1[15:3], 3'd0 } + 32'd5;

assign wr_descriptor_busy_tss_offset =

                                gdtr_base + { 16'd0, glob_param_1[15:3], 3'd0 } + 32'd4;

//------------------------------------------------------------------------------ write memory

wire memory_write_system;

wire        write_for_wr_ready;

wire [31:0] wr_string_es_linear;

assign memory_write_system =

    write_system_touch || write_system_busy_tss || write_system_dword || write_system_word || write_rmw_system_dword;

assign write_cpl =

    (write_new_stack_virtual)?      glob_descriptor_2[`DESC_BITS_DPL] :

    (memory_write_system)?          2'd0 :

                                    cpl;

assign write_lock = wr_prefix_group_1_lock;

assign write_rmw = write_rmw_virtual || write_rmw_system_dword;

assign write_address =

    (write_string_es_virtual)?                  wr_string_es_linear :

    (write_stack_virtual)?                      wr_push_linear :

    (write_new_stack_virtual)?                  wr_new_push_linear :

    (write_system_touch)?                       wr_descriptor_touch_offset :

    (write_system_busy_tss)?                    wr_descriptor_busy_tss_offset :

    (write_system_dword || write_system_word)?  wr_system_linear :

                                                wr_linear; //used by write_rmw_system_dword

assign write_data =

    (write_stack_virtual || write_string_es_virtual || write_new_stack_virtual)?    result_push :

    (write_system_touch)?                                                           { 24'd0, glob_descriptor[47:41], 1'b1 } :

    (write_system_busy_tss)?                                                        glob_descriptor[63:32] | 32'h00000200 :

    (write_rmw_system_dword || write_system_dword || write_system_word)?            wr_system_dword :

                                                                                    result;

assign write_length =

    (write_stack_virtual || write_new_stack_virtual)?   wr_push_length :

    (write_system_touch)?       3'd1 :

    (write_system_busy_tss)?    3'd4 :

    (write_length_word)?        3'd2 :

    (write_rmw_system_dword)?   3'd4 :

    (write_system_dword)?       3'd4 :

    (write_system_word)?        3'd2 :

    (write_length_dword)?       3'd4 :

    wr_is_8bit?                 3'd1 : //last 3: write_string_es_virtual also

    wr_operand_16bit?           3'd2 :