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[/] [ao486/] [trunk/] [rtl/] [common/] [simple_bidir_ram.v] - Blame information for rev 2

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1 2 alfik
/*
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 * Copyright (c) 2014, Aleksander Osman
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions are met:
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 *
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 * * Redistributions of source code must retain the above copyright notice, this
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 *   list of conditions and the following disclaimer.
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 *
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 * * Redistributions in binary form must reproduce the above copyright notice,
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 *   this list of conditions and the following disclaimer in the documentation
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 *   and/or other materials provided with the distribution.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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module simple_bidir_ram(
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    input                       clk,
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    input       [widthad-1:0]   address_a,
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    input                       wren_a,
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    input       [width-1:0]     data_a,
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    output reg  [width-1:0]     q_a,
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    input       [widthad-1:0]   address_b,
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    output reg  [width-1:0]     q_b
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);
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parameter width     = 1;
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parameter widthad   = 1;
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reg [width-1:0] mem [(2**widthad)-1:0];
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always @(posedge clk) begin
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    if(wren_a) mem[address_a] <= data_a;
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    q_a <= mem[address_a];
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end
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always @(posedge clk) begin
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    q_b <= mem[address_b];
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end
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endmodule

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