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alfik |
/*
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* Copyright (c) 2014, Aleksander Osman
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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module simple_fifo(
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input clk,
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input rst_n,
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input sclr,
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input rdreq,
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input wrreq,
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input [width-1:0] data,
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output empty,
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output reg full,
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output [width-1:0] q,
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output reg [widthu-1:0] usedw
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);
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parameter width = 1;
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parameter widthu = 1;
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reg [width-1:0] mem [(2**widthu)-1:0];
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reg [widthu-1:0] rd_index = 0;
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reg [widthu-1:0] wr_index = 0;
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assign q = mem[rd_index];
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assign empty= usedw == 0 && ~(full);
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) rd_index <= 0;
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else if(sclr) rd_index <= 0;
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else if(rdreq && ~(empty)) rd_index <= rd_index + { {widthu-1{1'b0}}, 1'b1 };
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end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) wr_index <= 0;
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else if(sclr) wr_index <= 0;
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else if(wrreq && (~(full) || rdreq)) wr_index <= wr_index + { {widthu-1{1'b0}}, 1'b1 };
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end
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always @(posedge clk) begin
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if(wrreq && (~(full) || rdreq)) mem[wr_index] <= data;
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end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) full <= 1'b0;
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else if(sclr) full <= 1'b0;
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else if(rdreq && ~(wrreq) && full) full <= 1'b0;
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else if(~(rdreq) && wrreq && ~(full) && usedw == (2**widthu)-1) full <= 1'b1;
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end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) usedw <= 0;
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else if(sclr) usedw <= 0;
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else if(rdreq && ~(wrreq) && ~(empty)) usedw <= usedw - { {widthu-1{1'b0}}, 1'b1 };
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else if(~(rdreq) && wrreq && ~(full)) usedw <= usedw + { {widthu-1{1'b0}}, 1'b1 };
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else if(rdreq && wrreq && empty) usedw <= { {widthu-1{1'b0}}, 1'b1 };
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end
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endmodule
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