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[/] [ao486/] [trunk/] [rtl/] [soc/] [driver_sd/] [avalon_slave.v] - Blame information for rev 8

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1 8 alfik 
/*
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 * This file is subject to the terms and conditions of the BSD License. See
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 * the file "LICENSE" in the main directory of this archive for more details.
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 *
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 * Copyright (C) 2014 Aleksander Osman
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 */
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module avalon_slave(
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    input               clk,
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    input               rst_n,
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    //
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    input       [1:0]   avs_address,
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    input               avs_read,
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    output      [31:0]  avs_readdata,
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    input               avs_write,
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    input       [31:0]  avs_writedata,
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    //
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    output reg          operation_init,
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    output reg          operation_read,
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    output reg          operation_write,
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    input               operation_sector_update,
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    output              operation_sector_last,
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    input               operation_finished_ok,
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    input               operation_finished_with_error,
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    //
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    output reg  [31:0]  sd_address,
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    output reg  [31:0]  avalon_address_base
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);
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//------------------------------------------------------------------------------
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assign avs_readdata = (avs_address == 2'd0)? {29'd0, status[2:0]} : { 29'd0, mutex };
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reg [2:0] mutex;
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always @(posedge clk or negedge rst_n) begin
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    if(rst_n == 1'b0)                                                               mutex <= 3'd0;
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    else if(mutex == 3'd0 && avs_address == 2'd1 && avs_read)                       mutex <= 3'd1;
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    else if(mutex == 3'd0 && avs_address == 2'd2 && avs_read)                       mutex <= 3'd2;
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    else if(mutex == 3'd0 && avs_address == 2'd3 && avs_read)                       mutex <= 3'd3;
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    else if(mutex < 3'd4 && (operation_init || operation_read || operation_write))  mutex <= 3'd4;
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    else if(operation_finished_ok || operation_finished_with_error)                 mutex <= 3'd0;
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end
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//------------------------------------------------------------------------------
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wire operation_idle = ~(operation_init) && ~(operation_read) && ~(operation_write);
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localparam [1:0] CONTROL_IDLE   = 2'd0; //not used
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localparam [1:0] CONTROL_INIT   = 2'd1;
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localparam [1:0] CONTROL_READ   = 2'd2;
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localparam [1:0] CONTROL_WRITE  = 2'd3;
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always @(posedge clk or negedge rst_n) begin
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    if(rst_n == 1'b0)                                                                                   operation_init <= 1'b1;
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    else if(operation_finished_ok || operation_finished_with_error)                                     operation_init <= 1'b0;
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    else if(operation_idle && avs_write && avs_address == 2'd3 && avs_writedata[1:0] == CONTROL_INIT)   operation_init <= 1'b1;
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end
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always @(posedge clk or negedge rst_n) begin
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    if(rst_n == 1'b0)                                                                                   operation_read <= 1'b0;
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    else if(operation_finished_ok || operation_finished_with_error)                                     operation_read <= 1'b0;
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    else if(operation_idle && avs_write && avs_address == 2'd3 && avs_writedata[1:0] == CONTROL_READ)   operation_read <= 1'b1;
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end
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always @(posedge clk or negedge rst_n) begin
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    if(rst_n == 1'b0)                                                                                   operation_write <= 1'b0;
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    else if(operation_finished_ok || operation_finished_with_error)                                     operation_write <= 1'b0;
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    else if(operation_idle && avs_write && avs_address == 2'd3 && avs_writedata[1:0] == CONTROL_WRITE)  operation_write <= 1'b1;
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end
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//------------------------------------------------------------------------------
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localparam [2:0] STATUS_INIT        = 3'd0;
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localparam [2:0] STATUS_INIT_ERROR  = 3'd1;
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localparam [2:0] STATUS_IDLE        = 3'd2;
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localparam [2:0] STATUS_READ        = 3'd3;
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localparam [2:0] STATUS_WRITE       = 3'd4;
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localparam [2:0] STATUS_ERROR       = 3'd5;
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reg [2:0] status;
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always @(posedge clk or negedge rst_n) begin
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    if(rst_n == 1'b0)                                                                                   status <= STATUS_INIT;
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    else if(operation_idle && avs_write && avs_address == 2'd3 && avs_writedata[1:0] == CONTROL_INIT)   status <= STATUS_INIT;
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    else if(operation_idle && avs_write && avs_address == 2'd3 && avs_writedata[1:0] == CONTROL_READ)   status <= STATUS_READ;
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    else if(operation_idle && avs_write && avs_address == 2'd3 && avs_writedata[1:0] == CONTROL_WRITE)  status <= STATUS_WRITE;
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    else if(operation_init && operation_finished_with_error)                                            status <= STATUS_INIT_ERROR;
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    else if(operation_finished_with_error)                                                              status <= STATUS_ERROR;
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    else if(operation_finished_ok)                                                                      status <= STATUS_IDLE;
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end
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//------------------------------------------------------------------------------
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always @(posedge clk or negedge rst_n) begin
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    if(rst_n == 1'b0)                                           avalon_address_base <= 32'd0;
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    else if(operation_idle && avs_write && avs_address == 2'd0) avalon_address_base <= avs_writedata;
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end
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always @(posedge clk or negedge rst_n) begin
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    if(rst_n == 1'b0)                                           sd_address <= 32'd0;
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    else if(operation_idle && avs_write && avs_address == 2'd1) sd_address <= avs_writedata;
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end
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reg [31:0] sd_block_count;
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always @(posedge clk or negedge rst_n) begin
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    if(rst_n == 1'b0)                                           sd_block_count <= 32'd0;
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    else if(operation_sector_update)                            sd_block_count <= sd_block_count - 32'd1;
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    else if(operation_idle && avs_write && avs_address == 2'd2) sd_block_count <= avs_writedata;
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end
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assign operation_sector_last = sd_block_count == 32'd1;
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//------------------------------------------------------------------------------
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endmodule

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