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[/] [ao486/] [trunk/] [rtl/] [soc/] [driver_sd/] [card_write.v] - Blame information for rev 8

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1 8 alfik 
/*
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 * This file is subject to the terms and conditions of the BSD License. See
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 * the file "LICENSE" in the main directory of this archive for more details.
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 *
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 * Copyright (C) 2014 Aleksander Osman
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 */
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module card_write(
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    input               clk,
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    input               rst_n,
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    //
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    input               operation_write,
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    input               operation_sector_last,
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    output              operation_sector_update,
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    output              operation_finished_ok,
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    output              operation_finished_with_error,
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    //
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    output              cmd_ready,
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    output      [5:0]   cmd_index,
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    output      [31:0]  cmd_arg,
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    output      [7:0]   cmd_resp_length,
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    output              cmd_resp_has_crc7,
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    input               reply_ready,
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    input       [135:0] reply_contents,
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    input               reply_error,
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    //
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    output              read_start,
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    output              read_next,
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    input       [31:0]  read_data,
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    input               read_done,
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    //
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    output reg          wr_async_data_ready,
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    output reg  [31:0]  wr_async_data,
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    input               wr_data_done,
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    input               wr_data_last_in_sector,
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    input               wr_error,
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    input               wr_finished_sector,
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    //
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    input       [31:0]  sd_address,
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    //
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    input               current_dat0,
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    //
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    output              stop_sd_clk
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);
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//------------------------------------------------------------------------------
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localparam [2:0] S_IDLE             = 3'd0;
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localparam [2:0] S_CMD25            = 3'd1;
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localparam [2:0] S_WAIT_FOR_DATA    = 3'd2;
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localparam [2:0] S_WAIT_FOR_DAT0    = 3'd3;
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localparam [2:0] S_CMD12            = 3'd4;
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localparam [2:0] S_FAILED_CMD12     = 3'd5;
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wire prepare_cmd25 = state == S_IDLE && operation_write;
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wire valid_cmd25   = reply_contents[45:40] == 6'd25 && reply_contents[39:27] == 13'd0 && reply_contents[24:21] == 4'b0; //command index; R1[31:19] no errors; R1[16:13] no errors
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wire stop_because_of_error = (state == S_CMD25 && (reply_error || (reply_ready && ~(valid_cmd25)))) || (state == S_WAIT_FOR_DATA && operation_sector_update && wr_error);
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wire prepare_cmd12         = stop_because_of_error || (operation_sector_update && operation_sector_last);
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wire valid_cmd12_common    = reply_contents[45:40] == 6'd12 && reply_contents[39:27] == 13'd0 && reply_contents[24:21] == 4'b0; //command index; R1[31:19] no errors; R1[16:13] no errors
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wire valid_cmd12           = valid_cmd12_common && current_dat0;
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wire valid_cmd12_but_busy  = valid_cmd12_common && ~(current_dat0);
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wire prepare_failed_cmd12  = state == S_CMD12 && (reply_error || (reply_ready && ~(valid_cmd12_common)));
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reg [2:0] state;
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always @(posedge clk or negedge rst_n) begin
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    if(rst_n == 1'b0)                                                   state <= S_IDLE;
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    else if(operation_finished_with_error)                              state <= S_IDLE;
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    else if(prepare_cmd25)                                              state <= S_CMD25;
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    else if(state == S_CMD25 && reply_ready && valid_cmd25)             state <= S_WAIT_FOR_DATA;
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    else if(prepare_cmd12)                                              state <= S_CMD12;
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    else if(state == S_CMD12 && reply_ready && valid_cmd12_but_busy)    state <= S_WAIT_FOR_DAT0;
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    else if(prepare_failed_cmd12)                                       state <= S_FAILED_CMD12;
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    else if(operation_finished_ok)                                      state <= S_IDLE;
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end
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reg was_error;
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always @(posedge clk or negedge rst_n) begin
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    if(rst_n == 1'b0)                                       was_error <= 1'b0;
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    else if(prepare_cmd25)                                  was_error <= 1'b0;
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    else if(stop_because_of_error || prepare_failed_cmd12)  was_error <= 1'b1;
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end
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wire finishing = (state == S_CMD12 && reply_ready && valid_cmd12) || (state == S_WAIT_FOR_DAT0 && current_dat0) || state == S_FAILED_CMD12;
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assign operation_finished_ok         = finishing && ~(was_error);
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assign operation_finished_with_error = finishing && was_error;
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//------------------------------------------------------------------------------
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reg first_read;
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always @(posedge clk or negedge rst_n) begin
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    if(rst_n == 1'b0)       first_read <= 1'b0;
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    else if(prepare_cmd25)  first_read <= 1'b1;
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    else if(read_start)     first_read <= 1'b0;
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end
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reg [3:0] read_cnt;
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always @(posedge clk or negedge rst_n) begin
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    if(rst_n == 1'b0)                               read_cnt <= 4'd0;
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    else if(read_start || read_next)                read_cnt <= 4'd1;
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    else if(read_done)                              read_cnt <= 4'd0;
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    else if(read_cnt > 4'd0 && read_cnt < 4'd14)    read_cnt <= read_cnt + 4'd1;
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end
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assign stop_sd_clk = read_cnt == 4'd14;
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assign operation_sector_update = wr_finished_sector;
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wire read_condition = state == S_WAIT_FOR_DATA && ~(wr_async_data_ready) && read_cnt == 4'd0 && ~(read_finished);
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assign read_start   = read_condition && first_read;
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assign read_next    = read_condition && ~(first_read);
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reg read_finished;
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always @(posedge clk or negedge rst_n) begin
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    if(rst_n == 1'b0)                               read_finished <= 1'b0;
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    else if(wr_data_done && wr_data_last_in_sector) read_finished <= 1'b1;
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    else if(operation_sector_update)                read_finished <= 1'b0;
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end
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always @(posedge clk or negedge rst_n) begin
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    if(rst_n == 1'b0)       wr_async_data_ready <= 1'b0;
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    else if(wr_data_done)   wr_async_data_ready <= 1'b0;
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    else if(read_done)      wr_async_data_ready <= 1'b1;
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end
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always @(posedge clk or negedge rst_n) begin
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    if(rst_n == 1'b0)       wr_async_data <= 32'b0;
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    else if(read_done)      wr_async_data <= read_data;
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end
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//------------------------------------------------------------------------------
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assign cmd_ready = prepare_cmd25 || prepare_cmd12;
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assign cmd_index         = (prepare_cmd25)? 6'd25      : 6'd12;
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assign cmd_arg           = (prepare_cmd25)? sd_address : 32'd0; //cmd25: sector address; cmd12: stuff bits
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assign cmd_resp_length   = 8'd48;                               //cmd25: R1; cmd12: R1b
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assign cmd_resp_has_crc7 = 1'b1;
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// synthesis translate_off
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wire _unused_ok = &{ 1'b0, reply_contents[135:46], reply_contents[26:25], reply_contents[20:0], 1'b0 };
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// synthesis translate_on
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//------------------------------------------------------------------------------
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endmodule

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