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alfik |
/*
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* This file is subject to the terms and conditions of the BSD License. See
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* the file "LICENSE" in the main directory of this archive for more details.
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*
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* Copyright (C) 2014 Aleksander Osman
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*/
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module dat(
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input clk,
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input rst_n,
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//
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input sd_clk_is_one,
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//
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input wr_async_data_ready,
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input [31:0] wr_async_data,
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output reg wr_data_done,
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output reg wr_data_last_in_sector,
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output reg wr_error,
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output reg wr_finished_sector,
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//
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input rd_async_start,
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input rd_async_abort,
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output reg rd_data_done,
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output reg rd_data_last_in_sector,
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output reg [31:0] rd_data,
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output reg rd_error,
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//
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output current_dat0,
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//
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inout [3:0] sd_dat
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);
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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reg sd_dat_enable;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) sd_dat_enable <= 1'b0;
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else if(sd_clk_is_one) sd_dat_enable <= wr_start || wr_cnt > 11'd0;
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end
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reg [3:0] sd_dat_output;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) sd_dat_output <= 4'hF;
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else if(sd_clk_is_one) sd_dat_output <= (wr_start)? 4'h0 : (wr_cnt <= 11'd17 && wr_cnt >= 11'd2)? { wr_crc_3[0], wr_crc_2[0], wr_crc_1[0], wr_crc_0[0] } : { wr_val_3[7], wr_val_2[7], wr_val_1[7], wr_val_0[7] };
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end
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assign sd_dat = (sd_dat_enable)? sd_dat_output : 4'bZ;
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reg [3:0] sd_dat_input;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) sd_dat_input <= 4'b1111;
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else if(~(sd_clk_is_one)) sd_dat_input <= sd_dat;
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end
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assign current_dat0 = sd_dat_input[0];
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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/*
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input wr_async_data_ready,
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input [31:0] wr_async_data,
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output reg wr_data_done,
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output reg wr_error,
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output reg wr_finished,
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*/
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reg [1:0] wr_start_delay_cnt;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) wr_start_delay_cnt <= 2'd2;
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else if(sd_clk_is_one && wr_async_data_ready && wr_cnt == 11'd0 && ~(wr_in_progress) && wr_start_delay_cnt > 2'd0) wr_start_delay_cnt <= wr_start_delay_cnt - 2'd1;
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else if(wr_cnt > 11'd0) wr_start_delay_cnt <= 2'd2;
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end
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wire wr_start = sd_clk_is_one && wr_async_data_ready && wr_cnt == 11'd0 && ~(wr_in_progress) && wr_start_delay_cnt == 2'd0;
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wire wr_load = wr_start || (sd_clk_is_one && wr_async_data_ready && wr_cnt >= 11'd26 && wr_cnt[2:0] == 3'b010) || (wr_missed && wr_async_data_ready);
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reg wr_missed;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) wr_missed <= 1'b0;
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else if(sd_clk_is_one && ~(wr_async_data_ready) && wr_cnt >= 11'd26 && wr_cnt[2:0] == 3'b010) wr_missed <= 1'b1;
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else if(wr_async_data_ready) wr_missed <= 1'b0;
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end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) wr_data_done <= 1'b0;
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else wr_data_done <= wr_load;
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end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) wr_data_last_in_sector <= 1'b0;
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else wr_data_last_in_sector <= wr_load && (wr_cnt == 11'd26 || wr_cnt == 11'd25);
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end
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reg [10:0] wr_cnt;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) wr_cnt <= 11'd0;
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else if(wr_start) wr_cnt <= 11'd1041;
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else if(sd_clk_is_one && wr_cnt > 11'd0) wr_cnt <= wr_cnt - 11'd1;
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end
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wire wr_resp_start = sd_clk_is_one && wr_cnt == 11'd1;
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reg wr_resp_awaiting;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) wr_resp_awaiting <= 1'b0;
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else if(wr_resp_start) wr_resp_awaiting <= 1'b1;
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else if(sd_clk_is_one && wr_resp_awaiting && sd_dat_input[0] == 1'b0) wr_resp_awaiting <= 1'b0;
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end
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reg [2:0] wr_resp_cnt;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) wr_resp_cnt <= 3'd0;
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else if(sd_clk_is_one && wr_resp_awaiting && sd_dat_input[0] == 1'b0) wr_resp_cnt <= 3'd4;
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else if(sd_clk_is_one && wr_resp_cnt > 3'd0) wr_resp_cnt <= wr_resp_cnt - 3'd1;
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end
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wire wr_in_progress_end = wr_in_progress && ((sd_clk_is_one && wr_error_cnt == 27'h7FFFFFF) || (sd_clk_is_one && wr_cnt == 11'd0 && ~(wr_resp_awaiting) && wr_resp_cnt == 3'd0 && sd_dat_input[0] == 1'b1));
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reg wr_in_progress;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) wr_in_progress <= 1'b0;
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else if(wr_start) wr_in_progress <= 1'b1;
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else if(wr_in_progress_end) wr_in_progress <= 1'b0;
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end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) wr_finished_sector <= 1'b0;
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else wr_finished_sector <= wr_in_progress_end;
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end
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//------------------------------------------------------------------------------
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wire wr_resp_now_in_error = sd_clk_is_one && (
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(wr_resp_cnt == 3'd4 && sd_dat_input[0] == 1'b1) || //crc status invalid
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(wr_resp_cnt == 3'd3 && sd_dat_input[0] == 1'b0) || //crc status invalid
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(wr_resp_cnt == 3'd2 && sd_dat_input[0] == 1'b1) || //crc status invalid
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(wr_resp_cnt == 3'd1 && sd_dat_input[0] == 1'b0) //end bit is '0'
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);
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reg [26:0] wr_error_cnt;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) wr_error_cnt <= 27'd0;
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else if(~(wr_in_progress)) wr_error_cnt <= 27'd0;
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else if(wr_resp_start) wr_error_cnt <= 27'd1;
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else if(sd_clk_is_one && wr_error_cnt > 27'd0) wr_error_cnt <= wr_error_cnt + 27'd1;
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end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) wr_error <= 1'b0;
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else if(wr_start) wr_error <= 1'b0;
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else if(wr_resp_now_in_error) wr_error <= 1'b1;
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else if(sd_clk_is_one && wr_error_cnt == 27'h7FFFFFF) wr_error <= 1'b1;
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end
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//------------------------------------------------------------------------------
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reg [7:0] wr_val_0;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) wr_val_0 <= 8'd0;
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else if(wr_load) wr_val_0 <= { wr_async_data[4], wr_async_data[0], wr_async_data[12], wr_async_data[8], wr_async_data[20], wr_async_data[16], wr_async_data[28], wr_async_data[24] };
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else if(sd_clk_is_one) wr_val_0 <= { wr_val_0[6:0], 1'b1 }; //fill with 1 important
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end
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reg [7:0] wr_val_1;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) wr_val_1 <= 8'd0;
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else if(wr_load) wr_val_1 <= { wr_async_data[5], wr_async_data[1], wr_async_data[13], wr_async_data[9], wr_async_data[21], wr_async_data[17], wr_async_data[29], wr_async_data[25] };
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else if(sd_clk_is_one) wr_val_1 <= { wr_val_1[6:0], 1'b1 }; //fill with 1 important
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end
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reg [7:0] wr_val_2;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) wr_val_2 <= 8'd0;
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else if(wr_load) wr_val_2 <= { wr_async_data[6], wr_async_data[2], wr_async_data[14], wr_async_data[10], wr_async_data[22], wr_async_data[18], wr_async_data[30], wr_async_data[26] };
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else if(sd_clk_is_one) wr_val_2 <= { wr_val_2[6:0], 1'b1 }; //fill with 1 important
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end
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reg [7:0] wr_val_3;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) wr_val_3 <= 8'd0;
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else if(wr_load) wr_val_3 <= { wr_async_data[7], wr_async_data[3], wr_async_data[15], wr_async_data[11], wr_async_data[23], wr_async_data[19], wr_async_data[31], wr_async_data[27] };
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else if(sd_clk_is_one) wr_val_3 <= { wr_val_3[6:0], 1'b1 }; //fill with 1 important
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end
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reg [15:0] wr_crc_0;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) wr_crc_0 <= 16'd0;
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else if(sd_clk_is_one && wr_cnt >= 11'd18) wr_crc_0 <= { wr_val_0[7] ^ wr_crc_0[0], wr_crc_0[15:12], wr_crc_0[11] ^ wr_val_0[7] ^ wr_crc_0[0], wr_crc_0[10:5], wr_crc_0[4] ^ wr_val_0[7] ^ wr_crc_0[0], wr_crc_0[3:1] };
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else if(sd_clk_is_one) wr_crc_0 <= { 1'b0, wr_crc_0[15:1] }; //fill with 0 important
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end
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reg [15:0] wr_crc_1;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) wr_crc_1 <= 16'd0;
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else if(sd_clk_is_one && wr_cnt >= 11'd18) wr_crc_1 <= { wr_val_1[7] ^ wr_crc_1[0], wr_crc_1[15:12], wr_crc_1[11] ^ wr_val_1[7] ^ wr_crc_1[0], wr_crc_1[10:5], wr_crc_1[4] ^ wr_val_1[7] ^ wr_crc_1[0], wr_crc_1[3:1] };
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else if(sd_clk_is_one) wr_crc_1 <= { 1'b0, wr_crc_1[15:1] }; //fill with 0 important
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end
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reg [15:0] wr_crc_2;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) wr_crc_2 <= 16'd0;
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else if(sd_clk_is_one && wr_cnt >= 11'd18) wr_crc_2 <= { wr_val_2[7] ^ wr_crc_2[0], wr_crc_2[15:12], wr_crc_2[11] ^ wr_val_2[7] ^ wr_crc_2[0], wr_crc_2[10:5], wr_crc_2[4] ^ wr_val_2[7] ^ wr_crc_2[0], wr_crc_2[3:1] };
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else if(sd_clk_is_one) wr_crc_2 <= { 1'b0, wr_crc_2[15:1] }; //fill with 0 important
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end
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reg [15:0] wr_crc_3;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) wr_crc_3 <= 16'd0;
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else if(sd_clk_is_one && wr_cnt >= 11'd18) wr_crc_3 <= { wr_val_3[7] ^ wr_crc_3[0], wr_crc_3[15:12], wr_crc_3[11] ^ wr_val_3[7] ^ wr_crc_3[0], wr_crc_3[10:5], wr_crc_3[4] ^ wr_val_3[7] ^ wr_crc_3[0], wr_crc_3[3:1] };
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else if(sd_clk_is_one) wr_crc_3 <= { 1'b0, wr_crc_3[15:1] }; //fill with 0 important
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end
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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/*
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227 |
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input rd_async_start,
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input rd_async_abort,
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output reg rd_data_done,
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output reg rd_data_last_in_sector,
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output reg [31:0] rd_data,
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output reg rd_error,
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*/
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wire rd_start = sd_clk_is_one && rd_async_in_progress && ~(rd_now_in_error) && ~(rd_error) && ~(rd_awaiting) && rd_cnt <= 11'd1;
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wire rd_start_block = sd_clk_is_one && rd_awaiting && sd_dat_input == 4'h0;
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wire rd_active = sd_clk_is_one && rd_cnt > 11'd0;
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wire rd_load = sd_clk_is_one && rd_cnt >= 11'd18 && rd_cnt[2:0] == 3'b010 && ~(rd_async_abort);
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reg rd_async_in_progress;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) rd_async_in_progress <= 1'b0;
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else if(rd_async_abort) rd_async_in_progress <= 1'b0;
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else if(rd_async_start) rd_async_in_progress <= 1'b1;
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end
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reg rd_awaiting;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) rd_awaiting <= 1'b0;
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else if(rd_async_abort) rd_awaiting <= 1'b0;
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else if(rd_start) rd_awaiting <= 1'b1;
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else if(rd_start_block) rd_awaiting <= 1'b0;
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end
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reg [10:0] rd_cnt;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) rd_cnt <= 11'd0;
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else if(rd_async_abort) rd_cnt <= 11'd0;
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else if(rd_start_block) rd_cnt <= 11'd1041;
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else if(rd_active) rd_cnt <= rd_cnt - 11'd1;
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end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) rd_data_done <= 1'b0;
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else rd_data_done <= rd_load;
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end
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268 |
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always @(posedge clk or negedge rst_n) begin
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269 |
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if(rst_n == 1'b0) rd_data_last_in_sector <= 1'b0;
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270 |
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else rd_data_last_in_sector <= rd_load && rd_cnt == 11'd18;
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271 |
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end
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272 |
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|
273 |
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always @(posedge clk or negedge rst_n) begin
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274 |
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if(rst_n == 1'b0) rd_data <= 32'b0;
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275 |
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else if(rd_load) rd_data <= { rd_val[3:0], sd_dat_input, rd_val[11:4], rd_val[19:12], rd_val[27:20] };
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276 |
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end
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277 |
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|
278 |
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|
//------------------------------------------------------------------------------
|
279 |
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|
280 |
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reg [26:0] rd_error_cnt;
|
281 |
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always @(posedge clk or negedge rst_n) begin
|
282 |
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if(rst_n == 1'b0) rd_error_cnt <= 27'd0;
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283 |
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else if(rd_async_abort) rd_error_cnt <= 27'd0;
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284 |
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else if(rd_start_block) rd_error_cnt <= 27'd0;
|
285 |
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else if(rd_start) rd_error_cnt <= 27'd1;
|
286 |
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else if(sd_clk_is_one && rd_error_cnt > 27'd0) rd_error_cnt <= rd_error_cnt + 27'd1;
|
287 |
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|
end
|
288 |
|
|
|
289 |
|
|
wire rd_now_in_error = rd_active && (
|
290 |
|
|
(rd_cnt == 11'd1 && sd_dat_input != 4'hF) || //end bit is '0'
|
291 |
|
|
(rd_cnt <= 11'd17 && rd_cnt >= 11'd2 && sd_dat_input != { rd_3[0], rd_2[0], rd_1[0], rd_0[0] }) //crc16 invalid
|
292 |
|
|
);
|
293 |
|
|
|
294 |
|
|
always @(posedge clk or negedge rst_n) begin
|
295 |
|
|
if(rst_n == 1'b0) rd_error <= 1'b0;
|
296 |
|
|
else if(rd_async_abort) rd_error <= 1'b0;
|
297 |
|
|
else if(rd_now_in_error) rd_error <= 1'b1;
|
298 |
|
|
else if(sd_clk_is_one && rd_error_cnt == 27'h7FFFFFF) rd_error <= 1'b1;
|
299 |
|
|
end
|
300 |
|
|
|
301 |
|
|
//------------------------------------------------------------------------------
|
302 |
|
|
|
303 |
|
|
reg [27:0] rd_val;
|
304 |
|
|
always @(posedge clk or negedge rst_n) begin
|
305 |
|
|
if(rst_n == 1'b0) rd_val <= 28'd0;
|
306 |
|
|
else if(rd_active) rd_val <= { rd_val[23:0], sd_dat_input };
|
307 |
|
|
end
|
308 |
|
|
|
309 |
|
|
reg [15:0] rd_0;
|
310 |
|
|
always @(posedge clk or negedge rst_n) begin
|
311 |
|
|
if(rst_n == 1'b0) rd_0 <= 16'd0;
|
312 |
|
|
else if(sd_clk_is_one && rd_cnt >= 11'd18) rd_0 <= { sd_dat_input[0] ^ rd_0[0], rd_0[15:12], rd_0[11] ^ sd_dat_input[0] ^ rd_0[0], rd_0[10:5], rd_0[4] ^ sd_dat_input[0] ^ rd_0[0], rd_0[3:1] };
|
313 |
|
|
else if(sd_clk_is_one) rd_0 <= { 1'b0, rd_0[15:1] }; //fill with 0 important
|
314 |
|
|
end
|
315 |
|
|
|
316 |
|
|
reg [15:0] rd_1;
|
317 |
|
|
always @(posedge clk or negedge rst_n) begin
|
318 |
|
|
if(rst_n == 1'b0) rd_1 <= 16'd0;
|
319 |
|
|
else if(sd_clk_is_one && rd_cnt >= 11'd18) rd_1 <= { sd_dat_input[1] ^ rd_1[0], rd_1[15:12], rd_1[11] ^ sd_dat_input[1] ^ rd_1[0], rd_1[10:5], rd_1[4] ^ sd_dat_input[1] ^ rd_1[0], rd_1[3:1] };
|
320 |
|
|
else if(sd_clk_is_one) rd_1 <= { 1'b0, rd_1[15:1] }; //fill with 0 important
|
321 |
|
|
end
|
322 |
|
|
|
323 |
|
|
reg [15:0] rd_2;
|
324 |
|
|
always @(posedge clk or negedge rst_n) begin
|
325 |
|
|
if(rst_n == 1'b0) rd_2 <= 16'd0;
|
326 |
|
|
else if(sd_clk_is_one && rd_cnt >= 11'd18) rd_2 <= { sd_dat_input[2] ^ rd_2[0], rd_2[15:12], rd_2[11] ^ sd_dat_input[2] ^ rd_2[0], rd_2[10:5], rd_2[4] ^ sd_dat_input[2] ^ rd_2[0], rd_2[3:1] };
|
327 |
|
|
else if(sd_clk_is_one) rd_2 <= { 1'b0, rd_2[15:1] }; //fill with 0 important
|
328 |
|
|
end
|
329 |
|
|
|
330 |
|
|
reg [15:0] rd_3;
|
331 |
|
|
always @(posedge clk or negedge rst_n) begin
|
332 |
|
|
if(rst_n == 1'b0) rd_3 <= 16'd0;
|
333 |
|
|
else if(sd_clk_is_one && rd_cnt >= 11'd18) rd_3 <= { sd_dat_input[3] ^ rd_3[0], rd_3[15:12], rd_3[11] ^ sd_dat_input[3] ^ rd_3[0], rd_3[10:5], rd_3[4] ^ sd_dat_input[3] ^ rd_3[0], rd_3[3:1] };
|
334 |
|
|
else if(sd_clk_is_one) rd_3 <= { 1'b0, rd_3[15:1] }; //fill with 0 important
|
335 |
|
|
end
|
336 |
|
|
|
337 |
|
|
//------------------------------------------------------------------------------
|
338 |
|
|
|
339 |
|
|
endmodule
|