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alfik |
# TCL File Generated by Component Editor 13.1
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# Fri Jan 17 22:19:50 CET 2014
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# DO NOT MODIFY
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#
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# pc_dma "pc_dma" v1.0
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# 2014.01.17.22:19:50
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#
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#
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#
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# request TCL package from ACDS 13.1
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#
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package require -exact qsys 13.1
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#
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# module pc_dma
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#
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set_module_property DESCRIPTION ""
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set_module_property NAME pc_dma
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set_module_property VERSION 1.0
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property GROUP ao486
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set_module_property AUTHOR ""
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set_module_property DISPLAY_NAME pc_dma
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE true
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set_module_property ANALYZE_HDL AUTO
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set_module_property REPORT_TO_TALKBACK false
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set_module_property ALLOW_GREYBOX_GENERATION false
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#
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# file sets
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#
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add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
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set_fileset_property QUARTUS_SYNTH TOP_LEVEL pc_dma
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set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
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add_fileset_file pc_dma.v VERILOG PATH pc_dma.v TOP_LEVEL_FILE
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#
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# parameters
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#
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#
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# display items
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#
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#
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# connection point clock
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#
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add_interface clock clock end
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set_interface_property clock clockRate 0
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set_interface_property clock ENABLED true
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set_interface_property clock EXPORT_OF ""
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set_interface_property clock PORT_NAME_MAP ""
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set_interface_property clock CMSIS_SVD_VARIABLES ""
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set_interface_property clock SVD_ADDRESS_GROUP ""
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add_interface_port clock clk clk Input 1
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#
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# connection point slave
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#
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add_interface slave avalon end
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set_interface_property slave addressUnits WORDS
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set_interface_property slave associatedClock clock
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set_interface_property slave associatedReset reset_sink
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set_interface_property slave bitsPerSymbol 8
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set_interface_property slave burstOnBurstBoundariesOnly false
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set_interface_property slave burstcountUnits WORDS
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set_interface_property slave explicitAddressSpan 0
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set_interface_property slave holdTime 0
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set_interface_property slave linewrapBursts false
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set_interface_property slave maximumPendingReadTransactions 0
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set_interface_property slave readLatency 0
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set_interface_property slave readWaitTime 1
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set_interface_property slave setupTime 0
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set_interface_property slave timingUnits Cycles
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set_interface_property slave writeWaitTime 0
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set_interface_property slave ENABLED true
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set_interface_property slave EXPORT_OF ""
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set_interface_property slave PORT_NAME_MAP ""
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set_interface_property slave CMSIS_SVD_VARIABLES ""
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set_interface_property slave SVD_ADDRESS_GROUP ""
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add_interface_port slave slave_address address Input 4
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add_interface_port slave slave_read read Input 1
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add_interface_port slave slave_readdata readdata Output 8
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add_interface_port slave slave_write write Input 1
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add_interface_port slave slave_writedata writedata Input 8
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set_interface_assignment slave embeddedsw.configuration.isFlash 0
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set_interface_assignment slave embeddedsw.configuration.isMemoryDevice 0
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set_interface_assignment slave embeddedsw.configuration.isNonVolatileStorage 0
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set_interface_assignment slave embeddedsw.configuration.isPrintableDevice 0
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#
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# connection point page
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#
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add_interface page avalon end
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set_interface_property page addressUnits WORDS
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set_interface_property page associatedClock clock
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set_interface_property page associatedReset reset_sink
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set_interface_property page bitsPerSymbol 8
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set_interface_property page burstOnBurstBoundariesOnly false
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set_interface_property page burstcountUnits WORDS
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set_interface_property page explicitAddressSpan 0
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set_interface_property page holdTime 0
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set_interface_property page linewrapBursts false
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set_interface_property page maximumPendingReadTransactions 0
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set_interface_property page readLatency 0
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set_interface_property page readWaitTime 1
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set_interface_property page setupTime 0
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set_interface_property page timingUnits Cycles
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set_interface_property page writeWaitTime 0
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set_interface_property page ENABLED true
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set_interface_property page EXPORT_OF ""
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set_interface_property page PORT_NAME_MAP ""
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set_interface_property page CMSIS_SVD_VARIABLES ""
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set_interface_property page SVD_ADDRESS_GROUP ""
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add_interface_port page page_address address Input 4
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add_interface_port page page_read read Input 1
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add_interface_port page page_readdata readdata Output 8
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add_interface_port page page_write write Input 1
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add_interface_port page page_writedata writedata Input 8
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set_interface_assignment page embeddedsw.configuration.isFlash 0
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set_interface_assignment page embeddedsw.configuration.isMemoryDevice 0
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set_interface_assignment page embeddedsw.configuration.isNonVolatileStorage 0
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set_interface_assignment page embeddedsw.configuration.isPrintableDevice 0
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#
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# connection point master
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#
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add_interface master avalon end
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set_interface_property master addressUnits WORDS
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set_interface_property master associatedClock clock
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set_interface_property master associatedReset reset_sink
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set_interface_property master bitsPerSymbol 8
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set_interface_property master burstOnBurstBoundariesOnly false
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set_interface_property master burstcountUnits WORDS
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set_interface_property master explicitAddressSpan 0
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set_interface_property master holdTime 0
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set_interface_property master linewrapBursts false
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set_interface_property master maximumPendingReadTransactions 0
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set_interface_property master readLatency 0
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set_interface_property master readWaitTime 1
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set_interface_property master setupTime 0
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set_interface_property master timingUnits Cycles
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set_interface_property master writeWaitTime 0
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set_interface_property master ENABLED true
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set_interface_property master EXPORT_OF ""
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set_interface_property master PORT_NAME_MAP ""
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set_interface_property master CMSIS_SVD_VARIABLES ""
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set_interface_property master SVD_ADDRESS_GROUP ""
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add_interface_port master master_address address Input 5
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add_interface_port master master_read read Input 1
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add_interface_port master master_readdata readdata Output 8
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add_interface_port master master_write write Input 1
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add_interface_port master master_writedata writedata Input 8
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set_interface_assignment master embeddedsw.configuration.isFlash 0
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set_interface_assignment master embeddedsw.configuration.isMemoryDevice 0
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set_interface_assignment master embeddedsw.configuration.isNonVolatileStorage 0
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set_interface_assignment master embeddedsw.configuration.isPrintableDevice 0
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#
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# connection point reset_sink
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#
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add_interface reset_sink reset end
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set_interface_property reset_sink associatedClock clock
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set_interface_property reset_sink synchronousEdges DEASSERT
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set_interface_property reset_sink ENABLED true
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set_interface_property reset_sink EXPORT_OF ""
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set_interface_property reset_sink PORT_NAME_MAP ""
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set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
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set_interface_property reset_sink SVD_ADDRESS_GROUP ""
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add_interface_port reset_sink rst_n reset_n Input 1
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#
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# connection point avalon_master
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#
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add_interface avalon_master avalon start
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set_interface_property avalon_master addressUnits SYMBOLS
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set_interface_property avalon_master associatedClock clock
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set_interface_property avalon_master associatedReset reset_sink
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set_interface_property avalon_master bitsPerSymbol 8
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set_interface_property avalon_master burstOnBurstBoundariesOnly false
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set_interface_property avalon_master burstcountUnits WORDS
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set_interface_property avalon_master doStreamReads false
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set_interface_property avalon_master doStreamWrites false
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set_interface_property avalon_master holdTime 0
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set_interface_property avalon_master linewrapBursts false
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set_interface_property avalon_master maximumPendingReadTransactions 0
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set_interface_property avalon_master readLatency 0
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set_interface_property avalon_master readWaitTime 1
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set_interface_property avalon_master setupTime 0
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set_interface_property avalon_master timingUnits Cycles
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set_interface_property avalon_master writeWaitTime 0
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set_interface_property avalon_master ENABLED true
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set_interface_property avalon_master EXPORT_OF ""
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set_interface_property avalon_master PORT_NAME_MAP ""
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set_interface_property avalon_master CMSIS_SVD_VARIABLES ""
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set_interface_property avalon_master SVD_ADDRESS_GROUP ""
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add_interface_port avalon_master avm_address address Output 32
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add_interface_port avalon_master avm_waitrequest waitrequest Input 1
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add_interface_port avalon_master avm_read read Output 1
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add_interface_port avalon_master avm_readdatavalid readdatavalid Input 1
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add_interface_port avalon_master avm_readdata readdata Input 8
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add_interface_port avalon_master avm_write write Output 1
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add_interface_port avalon_master avm_writedata writedata Output 8
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#
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# connection point conduit_dma_floppy
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#
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add_interface conduit_dma_floppy conduit end
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set_interface_property conduit_dma_floppy associatedClock clock
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set_interface_property conduit_dma_floppy associatedReset reset_sink
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set_interface_property conduit_dma_floppy ENABLED true
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set_interface_property conduit_dma_floppy EXPORT_OF ""
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set_interface_property conduit_dma_floppy PORT_NAME_MAP ""
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set_interface_property conduit_dma_floppy CMSIS_SVD_VARIABLES ""
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set_interface_property conduit_dma_floppy SVD_ADDRESS_GROUP ""
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add_interface_port conduit_dma_floppy dma_floppy_req export Input 1
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add_interface_port conduit_dma_floppy dma_floppy_ack export Output 1
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add_interface_port conduit_dma_floppy dma_floppy_terminal export Output 1
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add_interface_port conduit_dma_floppy dma_floppy_readdata export Output 8
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add_interface_port conduit_dma_floppy dma_floppy_writedata export Input 8
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#
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# connection point conduit_dma_soundblaster
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#
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add_interface conduit_dma_soundblaster conduit end
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set_interface_property conduit_dma_soundblaster associatedClock clock
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set_interface_property conduit_dma_soundblaster associatedReset reset_sink
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set_interface_property conduit_dma_soundblaster ENABLED true
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set_interface_property conduit_dma_soundblaster EXPORT_OF ""
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set_interface_property conduit_dma_soundblaster PORT_NAME_MAP ""
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set_interface_property conduit_dma_soundblaster CMSIS_SVD_VARIABLES ""
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set_interface_property conduit_dma_soundblaster SVD_ADDRESS_GROUP ""
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add_interface_port conduit_dma_soundblaster dma_soundblaster_req export Input 1
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add_interface_port conduit_dma_soundblaster dma_soundblaster_ack export Output 1
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add_interface_port conduit_dma_soundblaster dma_soundblaster_terminal export Output 1
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add_interface_port conduit_dma_soundblaster dma_soundblaster_readdata export Output 8
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add_interface_port conduit_dma_soundblaster dma_soundblaster_writedata export Input 8
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