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alfik |
/*
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* Copyright (c) 2014, Aleksander Osman
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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module rtc(
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input clk,
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input rst_n,
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output reg irq,
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//io slave
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input io_address,
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input io_read,
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output reg [7:0] io_readdata,
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input io_write,
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input [7:0] io_writedata,
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//mgmt slave
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/*
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128.[26:0]: cycles in second
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129.[12:0]: cycles in 122.07031 us
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*/
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input [7:0] mgmt_address,
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input mgmt_write,
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input [31:0] mgmt_writedata
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);
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//------------------------------------------------------------------------------
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reg io_read_last;
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always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) io_read_last <= 1'b0; else if(io_read_last) io_read_last <= 1'b0; else io_read_last <= io_read; end
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wire io_read_valid = io_read && io_read_last == 1'b0;
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//------------------------------------------------------------------------------ cycle count from mgmt
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reg [26:0] cycles_in_second;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) cycles_in_second <= 27'd30303030;
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else if(mgmt_write && mgmt_address == 8'd128) cycles_in_second <= mgmt_writedata[26:0];
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end
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reg [12:0] cycles_in_122us;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) cycles_in_122us <= 13'd4069;
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else if(mgmt_write && mgmt_address == 8'd129) cycles_in_122us <= mgmt_writedata[12:0];
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end
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//------------------------------------------------------------------------------ io read
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wire [7:0] io_readdata_next =
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(io_address == 1'b0)? 8'hFF :
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(ram_address == 7'h00)? rtc_second :
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(ram_address == 7'h01)? alarm_second :
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(ram_address == 7'h02)? rtc_minute :
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(ram_address == 7'h03)? alarm_second :
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(ram_address == 7'h04)? rtc_hour :
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(ram_address == 7'h05)? alarm_hour :
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(ram_address == 7'h06)? rtc_dayofweek :
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(ram_address == 7'h07)? rtc_dayofmonth :
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(ram_address == 7'h08)? rtc_month :
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(ram_address == 7'h09)? rtc_year :
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(ram_address == 7'h0A)? { sec_state == SEC_UPDATE_IN_PROGRESS || sec_state == SEC_SECOND_START, divider, periodic_rate } :
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(ram_address == 7'h0B)? { crb_freeze, crb_int_periodic_ena, crb_int_alarm_ena, crb_int_update_ena,
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1'b0, crb_binarymode, crb_24hour, crb_daylightsaving } :
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(ram_address == 7'h0C)? { irq, periodic_interrupt, alarm_interrupt, update_interrupt, 4'd0 } :
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(ram_address == 7'h0D)? 8'h80 :
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(ram_address == 7'h32)? rtc_century :
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(ram_address == 7'h37)? rtc_century :
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ram_q;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) io_readdata <= 8'd0;
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else io_readdata <= io_readdata_next;
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end
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//------------------------------------------------------------------------------ irq
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wire interrupt_start = irq == 1'b0 && (
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(crb_int_periodic_ena && periodic_interrupt) ||
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(crb_int_alarm_ena && alarm_interrupt) ||
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(crb_int_update_ena && update_interrupt) );
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) irq <= 1'b0;
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else if(io_read_valid && io_address == 1'b1 && ram_address == 7'h0C) irq <= 1'b0;
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else if(interrupt_start) irq <= 1'b1;
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end
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//------------------------------------------------------------------------------ once per second state machine
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localparam [2:0] SEC_UPDATE_START = 3'd0;
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localparam [2:0] SEC_UPDATE_IN_PROGRESS = 3'd1;
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localparam [2:0] SEC_SECOND_START = 3'd2;
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localparam [2:0] SEC_SECOND_IN_PROGRESS = 3'd3;
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localparam [2:0] SEC_STOPPED = 3'd4;
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reg [2:0] sec_state;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) sec_state <= SEC_UPDATE_START;
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else if(crb_freeze || divider[2:1] == 2'b11) sec_state <= SEC_STOPPED;
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else if(sec_state == SEC_STOPPED) sec_state <= SEC_UPDATE_START;
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else if(sec_state == SEC_UPDATE_START) sec_state <= SEC_UPDATE_IN_PROGRESS;
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else if(sec_state == SEC_UPDATE_IN_PROGRESS && sec_timeout == 27'd0) sec_state <= SEC_SECOND_START;
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else if(sec_state == SEC_SECOND_START) sec_state <= SEC_SECOND_IN_PROGRESS;
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else if(sec_state == SEC_SECOND_IN_PROGRESS && sec_timeout == { 13'd0, cycles_in_122us, 1'b0 }) sec_state <= SEC_UPDATE_START;
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end
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reg [26:0] sec_timeout;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) sec_timeout <= 27'd8137; //4069*2 -1
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else if(crb_freeze || divider[2:1] == 2'b11) sec_timeout <= 27'd8137; //4069*2 -1
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else if(sec_timeout == 27'd0) sec_timeout <= cycles_in_second;
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else sec_timeout <= sec_timeout - 27'd1;
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end
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reg update_interrupt;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) update_interrupt <= 1'b0;
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else if(io_read_valid && io_address == 1'b1 && ram_address == 7'h0C) update_interrupt <= 1'b0;
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else if(sec_state == SEC_SECOND_START) update_interrupt <= 1'b1;
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end
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//------------------------------------------------------------------------------
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wire max_second =
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(crb_binarymode && rtc_second >= 8'd59) ||
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(~(crb_binarymode) && (rtc_second[7:4] >= 4'd6 || (rtc_second[7:4] == 4'd5 && rtc_second[3:0] >= 4'd9)));
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wire [7:0] next_second =
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(max_second)? 8'd0 :
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(~(crb_binarymode) && rtc_second[3:0] >= 4'd9)? { rtc_second[7:4] + 4'd1, 4'd0 } :
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rtc_second + 8'd1;
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wire max_minute =
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(crb_binarymode && rtc_minute >= 8'd59) ||
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(~(crb_binarymode) && (rtc_minute[7:4] >= 4'd6 || (rtc_minute[7:4] == 4'd5 && rtc_minute[3:0] >= 4'd9)));
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wire [7:0] next_minute =
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(max_minute)? 8'd0 :
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(~(crb_binarymode) && rtc_minute[3:0] >= 4'd9)? { rtc_minute[7:4] + 4'd1, 4'd0 } :
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rtc_minute + 8'd1;
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wire dst_april = crb_daylightsaving && rtc_dayofweek == 8'd1 && rtc_month == 8'd4 &&
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((crb_binarymode && rtc_dayofmonth >= 8'd24) || (~(crb_binarymode) && rtc_dayofmonth[7:4] >= 4'd2 && rtc_dayofmonth[3:0] >= 4'd4)) &&
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rtc_hour == 8'd1;
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wire dst_october = crb_daylightsaving && rtc_dayofweek == 8'd1 &&
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((crb_binarymode && rtc_month == 8'd10) || (~(crb_binarymode) && rtc_month[7:4] == 4'd1 && rtc_month[3:0] == 4'd0)) &&
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((crb_binarymode && rtc_dayofmonth >= 8'd25) || (~(crb_binarymode) && rtc_dayofmonth[7:4] >= 4'd2 && rtc_dayofmonth[3:0] >= 4'd5)) &&
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rtc_hour == 8'd1;
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wire max_hour =
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(~(crb_24hour) && crb_binarymode && rtc_hour[7] && rtc_hour[6:0] >= 7'd12) ||
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(crb_24hour && crb_binarymode && rtc_hour >= 8'd23) ||
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(~(crb_24hour) && ~(crb_binarymode) && rtc_hour[7] && (rtc_hour[6:4] >= 3'd2 || (rtc_hour[6:4] == 3'd1 && rtc_hour[3:0] >= 4'd2))) ||
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(crb_24hour && ~(crb_binarymode) && (rtc_hour[7:4] >= 4'd3 || (rtc_hour[7:4] == 4'd2 && rtc_hour[3:0] >= 4'd3)));
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wire [7:0] next_hour =
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(dst_april)? 8'd3 :
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(dst_october)? 8'd1 :
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(~(crb_24hour) && max_hour)? 8'd1 :
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(crb_24hour && max_hour)? 8'd0 :
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(~(crb_24hour) && crb_binarymode && rtc_hour[6:0] >= 7'd12)? 8'h81 :
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(~(crb_24hour) && ~(crb_binarymode) && rtc_hour[6:4] == 3'd1 && rtc_hour[3:0] >= 4'd2)? 8'h81 :
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(~(crb_24hour) && ~(crb_binarymode) && rtc_hour[6:4] == 3'd0 && rtc_hour[3:0] >= 4'd9)? { rtc_hour[7], 3'b1, 4'd0 } :
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(crb_24hour && ~(crb_binarymode) && rtc_hour[3:0] >= 4'd9)? { rtc_hour[7:4] + 4'd1, 4'd0 } :
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rtc_hour + 8'd1;
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wire max_dayofweek = rtc_dayofweek >= 8'd7;
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wire [7:0] next_dayofweek =
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(max_dayofweek)? 8'd1 :
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rtc_dayofweek + 8'd1;
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//simplified leap year condition
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wire leap_year =
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(crb_binarymode && rtc_year[1:0] == 2'b00) ||
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(~(crb_binarymode) && ((rtc_year[1:0] == 2'b00 && rtc_year[4] == 1'b0) || (rtc_year[1:0] == 2'b10 && rtc_year[4] == 1'b1)));
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wire max_dayofmonth =
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(crb_binarymode && (
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(rtc_month <= 8'd1 && rtc_dayofmonth >= 8'd31) ||
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(rtc_month == 8'd2 && ((~(leap_year) && rtc_dayofmonth >= 8'd28) || (leap_year && rtc_dayofmonth >= 8'd29))) ||
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(rtc_month == 8'd3 && rtc_dayofmonth >= 8'd31) ||
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(rtc_month == 8'd4 && rtc_dayofmonth >= 8'd30) ||
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(rtc_month == 8'd5 && rtc_dayofmonth >= 8'd31) ||
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(rtc_month == 8'd6 && rtc_dayofmonth >= 8'd30) ||
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(rtc_month == 8'd7 && rtc_dayofmonth >= 8'd31) ||
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(rtc_month == 8'd8 && rtc_dayofmonth >= 8'd31) ||
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(rtc_month == 8'd9 && rtc_dayofmonth >= 8'd30) ||
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(rtc_month == 8'd10 && rtc_dayofmonth >= 8'd31) ||
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(rtc_month == 8'd11 && rtc_dayofmonth >= 8'd30) ||
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(rtc_month >= 8'd12 && rtc_dayofmonth >= 8'd31))
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) ||
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(~(crb_binarymode) && (
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(rtc_month <= 8'h01 && (rtc_dayofmonth[7:4] >= 4'd4 || (rtc_dayofmonth[7:4] == 4'd3 && rtc_dayofmonth[3:0] >= 4'd1))) ||
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(rtc_month == 8'h02 && ((~(leap_year) && (rtc_dayofmonth[7:4] >= 4'd3 || (rtc_dayofmonth[7:4] == 4'd2 && rtc_dayofmonth[3:0] >= 4'd8))) ||
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(leap_year && (rtc_dayofmonth[7:4] >= 4'd3 || (rtc_dayofmonth[7:4] == 4'd2 && rtc_dayofmonth[3:0] >= 4'd9))))) ||
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(rtc_month == 8'h03 && (rtc_dayofmonth[7:4] >= 4'd4 || (rtc_dayofmonth[7:4] == 4'd3 && rtc_dayofmonth[3:0] >= 4'd1))) ||
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| 225 |
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(rtc_month == 8'h04 && (rtc_dayofmonth[7:4] >= 4'd4 || (rtc_dayofmonth[7:4] == 4'd3))) ||
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| 226 |
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(rtc_month == 8'h05 && (rtc_dayofmonth[7:4] >= 4'd4 || (rtc_dayofmonth[7:4] == 4'd3 && rtc_dayofmonth[3:0] >= 4'd1))) ||
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| 227 |
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(rtc_month == 8'h06 && (rtc_dayofmonth[7:4] >= 4'd4 || (rtc_dayofmonth[7:4] == 4'd3))) ||
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| 228 |
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(rtc_month == 8'h07 && (rtc_dayofmonth[7:4] >= 4'd4 || (rtc_dayofmonth[7:4] == 4'd3 && rtc_dayofmonth[3:0] >= 4'd1))) ||
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| 229 |
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(rtc_month == 8'h08 && (rtc_dayofmonth[7:4] >= 4'd4 || (rtc_dayofmonth[7:4] == 4'd3 && rtc_dayofmonth[3:0] >= 4'd1))) ||
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| 230 |
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(rtc_month == 8'h09 && (rtc_dayofmonth[7:4] >= 4'd4 || (rtc_dayofmonth[7:4] == 4'd3))) ||
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| 231 |
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(rtc_month == 8'h10 && (rtc_dayofmonth[7:4] >= 4'd4 || (rtc_dayofmonth[7:4] == 4'd3 && rtc_dayofmonth[3:0] >= 4'd1))) ||
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| 232 |
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(rtc_month == 8'h11 && (rtc_dayofmonth[7:4] >= 4'd4 || (rtc_dayofmonth[7:4] == 4'd3))) ||
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| 233 |
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(rtc_month >= 8'h12 && (rtc_dayofmonth[7:4] >= 4'd4 || (rtc_dayofmonth[7:4] == 4'd3 && rtc_dayofmonth[3:0] >= 4'd1))))
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| 234 |
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);
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| 235 |
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| 236 |
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wire [7:0] next_dayofmonth =
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| 237 |
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(max_dayofmonth)? 8'd1 :
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| 238 |
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(~(crb_binarymode) && rtc_dayofmonth[3:0] >= 4'd9)? { rtc_dayofmonth[7:4] + 4'd1, 4'd0 } :
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| 239 |
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rtc_dayofmonth + 8'd1;
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| 240 |
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| 241 |
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wire max_month =
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| 242 |
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(crb_binarymode && rtc_month >= 8'd12) || (~(crb_binarymode) && (rtc_month[7:4] >= 4'd2 || (rtc_month[7:4] == 4'd1 && rtc_month[3:0] >= 4'd2)));
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| 243 |
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| 244 |
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wire [7:0] next_month =
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| 245 |
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(max_month)? 8'd1 :
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| 246 |
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(~(crb_binarymode) && rtc_month[3:0] >= 4'd9)? { rtc_month[7:4] + 4'd1, 4'd0 } :
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| 247 |
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rtc_month + 8'd1;
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| 248 |
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| 249 |
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wire max_year =
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| 250 |
|
|
(crb_binarymode && rtc_year >= 8'd99) || (~(crb_binarymode) && (rtc_year[7:4] >= 4'd10 || (rtc_year[7:4] == 4'd9 && rtc_year[3:0] >= 4'd9)));
|
| 251 |
|
|
|
| 252 |
|
|
wire [7:0] next_year =
|
| 253 |
|
|
(max_year)? 8'd0 :
|
| 254 |
|
|
(~(crb_binarymode) && rtc_year[3:0] >= 4'd9)? { rtc_year[7:4] + 4'd1, 4'd0 } :
|
| 255 |
|
|
rtc_year + 8'd1;
|
| 256 |
|
|
|
| 257 |
|
|
wire max_century =
|
| 258 |
|
|
(crb_binarymode && rtc_century >= 8'd99) || (~(crb_binarymode) && (rtc_century[7:4] >= 4'd10 || (rtc_century[7:4] == 4'd9 && rtc_century[3:0] >= 4'd9)));
|
| 259 |
|
|
|
| 260 |
|
|
wire [7:0] next_century =
|
| 261 |
|
|
(max_century)? 8'd0 :
|
| 262 |
|
|
(~(crb_binarymode) && rtc_century[3:0] >= 4'd9)? { rtc_century[7:4] + 4'd1, 4'd0 } :
|
| 263 |
|
|
rtc_century + 8'd1;
|
| 264 |
|
|
|
| 265 |
|
|
//------------------------------------------------------------------------------
|
| 266 |
|
|
|
| 267 |
|
|
wire rtc_second_update = sec_state == SEC_SECOND_START;
|
| 268 |
|
|
wire rtc_minute_update = rtc_second_update && max_second;
|
| 269 |
|
|
wire rtc_hour_update = rtc_minute_update && max_minute;
|
| 270 |
|
|
wire rtc_day_update = rtc_hour_update && max_hour;
|
| 271 |
|
|
wire rtc_month_update = rtc_day_update && max_dayofmonth;
|
| 272 |
|
|
wire rtc_year_update = rtc_month_update && max_month;
|
| 273 |
|
|
wire rtc_century_update= rtc_year_update && max_year;
|
| 274 |
|
|
|
| 275 |
|
|
//------------------------------------------------------------------------------
|
| 276 |
|
|
|
| 277 |
|
|
reg [7:0] rtc_second;
|
| 278 |
|
|
always @(posedge clk or negedge rst_n) begin
|
| 279 |
|
|
if(rst_n == 1'b0) rtc_second <= 8'd0;
|
| 280 |
|
|
else if(mgmt_write && mgmt_address == 8'h00) rtc_second <= mgmt_writedata[7:0];
|
| 281 |
|
|
else if(io_write && io_address == 1'b1 && ram_address == 7'h00) rtc_second <= io_writedata;
|
| 282 |
|
|
else if(rtc_second_update) rtc_second <= next_second;
|
| 283 |
|
|
end
|
| 284 |
|
|
|
| 285 |
|
|
reg [7:0] rtc_minute;
|
| 286 |
|
|
always @(posedge clk or negedge rst_n) begin
|
| 287 |
|
|
if(rst_n == 1'b0) rtc_minute <= 8'd0;
|
| 288 |
|
|
else if(mgmt_write && mgmt_address == 8'h02) rtc_minute <= mgmt_writedata[7:0];
|
| 289 |
|
|
else if(io_write && io_address == 1'b1 && ram_address == 7'h02) rtc_minute <= io_writedata;
|
| 290 |
|
|
else if(rtc_minute_update) rtc_minute <= next_minute;
|
| 291 |
|
|
end
|
| 292 |
|
|
|
| 293 |
|
|
reg [7:0] rtc_hour;
|
| 294 |
|
|
always @(posedge clk or negedge rst_n) begin
|
| 295 |
|
|
if(rst_n == 1'b0) rtc_hour <= 8'd0;
|
| 296 |
|
|
else if(mgmt_write && mgmt_address == 8'h04) rtc_hour <= mgmt_writedata[7:0];
|
| 297 |
|
|
else if(io_write && io_address == 1'b1 && ram_address == 7'h04) rtc_hour <= io_writedata;
|
| 298 |
|
|
else if(rtc_hour_update) rtc_hour <= next_hour;
|
| 299 |
|
|
end
|
| 300 |
|
|
|
| 301 |
|
|
reg [7:0] rtc_dayofweek;
|
| 302 |
|
|
always @(posedge clk or negedge rst_n) begin
|
| 303 |
|
|
if(rst_n == 1'b0) rtc_dayofweek <= 8'd0;
|
| 304 |
|
|
else if(mgmt_write && mgmt_address == 8'h06) rtc_dayofweek <= mgmt_writedata[7:0];
|
| 305 |
|
|
else if(io_write && io_address == 1'b1 && ram_address == 7'h06) rtc_dayofweek <= io_writedata;
|
| 306 |
|
|
else if(rtc_day_update) rtc_dayofweek <= next_dayofweek;
|
| 307 |
|
|
end
|
| 308 |
|
|
|
| 309 |
|
|
reg [7:0] rtc_dayofmonth;
|
| 310 |
|
|
always @(posedge clk or negedge rst_n) begin
|
| 311 |
|
|
if(rst_n == 1'b0) rtc_dayofmonth <= 8'd0;
|
| 312 |
|
|
else if(mgmt_write && mgmt_address == 8'h07) rtc_dayofmonth <= mgmt_writedata[7:0];
|
| 313 |
|
|
else if(io_write && io_address == 1'b1 && ram_address == 7'h07) rtc_dayofmonth <= io_writedata;
|
| 314 |
|
|
else if(rtc_day_update) rtc_dayofmonth <= next_dayofmonth;
|
| 315 |
|
|
end
|
| 316 |
|
|
|
| 317 |
|
|
reg [7:0] rtc_month;
|
| 318 |
|
|
always @(posedge clk or negedge rst_n) begin
|
| 319 |
|
|
if(rst_n == 1'b0) rtc_month <= 8'd0;
|
| 320 |
|
|
else if(mgmt_write && mgmt_address == 8'h08) rtc_month <= mgmt_writedata[7:0];
|
| 321 |
|
|
else if(io_write && io_address == 1'b1 && ram_address == 7'h08) rtc_month <= io_writedata;
|
| 322 |
|
|
else if(rtc_month_update) rtc_month <= next_month;
|
| 323 |
|
|
end
|
| 324 |
|
|
|
| 325 |
|
|
reg [7:0] rtc_year;
|
| 326 |
|
|
always @(posedge clk or negedge rst_n) begin
|
| 327 |
|
|
if(rst_n == 1'b0) rtc_year <= 8'd0;
|
| 328 |
|
|
else if(mgmt_write && mgmt_address == 8'h09) rtc_year <= mgmt_writedata[7:0];
|
| 329 |
|
|
else if(io_write && io_address == 1'b1 && ram_address == 7'h09) rtc_year <= io_writedata;
|
| 330 |
|
|
else if(rtc_year_update) rtc_year <= next_year;
|
| 331 |
|
|
end
|
| 332 |
|
|
|
| 333 |
|
|
reg [7:0] rtc_century;
|
| 334 |
|
|
always @(posedge clk or negedge rst_n) begin
|
| 335 |
|
|
if(rst_n == 1'b0) rtc_century <= 8'd0;
|
| 336 |
|
|
else if(mgmt_write && mgmt_address == 8'h32) rtc_century <= mgmt_writedata[7:0];
|
| 337 |
|
|
else if(io_write && io_address == 1'b1 && ram_address == 7'h32) rtc_century <= io_writedata;
|
| 338 |
|
|
else if(io_write && io_address == 1'b1 && ram_address == 7'h37) rtc_century <= io_writedata;
|
| 339 |
|
|
else if(rtc_century_update) rtc_century <= next_century;
|
| 340 |
|
|
end
|
| 341 |
|
|
|
| 342 |
|
|
//------------------------------------------------------------------------------
|
| 343 |
|
|
|
| 344 |
|
|
reg [7:0] alarm_second;
|
| 345 |
|
|
always @(posedge clk or negedge rst_n) begin
|
| 346 |
|
|
if(rst_n == 1'b0) alarm_second <= 8'd0;
|
| 347 |
|
|
else if(mgmt_write && mgmt_address == 8'h01) alarm_second <= mgmt_writedata[7:0];
|
| 348 |
|
|
else if(io_write && io_address == 1'b1 && ram_address == 7'h01) alarm_second <= io_writedata;
|
| 349 |
|
|
end
|
| 350 |
|
|
|
| 351 |
|
|
reg [7:0] alarm_minute;
|
| 352 |
|
|
always @(posedge clk or negedge rst_n) begin
|
| 353 |
|
|
if(rst_n == 1'b0) alarm_minute <= 8'd0;
|
| 354 |
|
|
else if(mgmt_write && mgmt_address == 8'h03) alarm_minute <= mgmt_writedata[7:0];
|
| 355 |
|
|
else if(io_write && io_address == 1'b1 && ram_address == 7'h03) alarm_minute <= io_writedata;
|
| 356 |
|
|
end
|
| 357 |
|
|
|
| 358 |
|
|
reg [7:0] alarm_hour;
|
| 359 |
|
|
always @(posedge clk or negedge rst_n) begin
|
| 360 |
|
|
if(rst_n == 1'b0) alarm_hour <= 8'd0;
|
| 361 |
|
|
else if(mgmt_write && mgmt_address == 8'h05) alarm_hour <= mgmt_writedata[7:0];
|
| 362 |
|
|
else if(io_write && io_address == 1'b1 && ram_address == 7'h05) alarm_hour <= io_writedata;
|
| 363 |
|
|
end
|
| 364 |
|
|
|
| 365 |
|
|
wire alarm_interrupt_activate =
|
| 366 |
|
|
(alarm_second[7:6] == 2'b11 || (rtc_second_update && next_second == alarm_second)) &&
|
| 367 |
|
|
(alarm_minute[7:6] == 2'b11 || (rtc_minute_update && next_minute == alarm_minute) || (~(rtc_minute_update) && rtc_minute == alarm_minute)) &&
|
| 368 |
|
|
(alarm_hour[7:6] == 2'b11 || (rtc_hour_update && next_hour == alarm_hour) || (~(rtc_hour_update) && rtc_hour == alarm_hour));
|
| 369 |
|
|
|
| 370 |
|
|
reg alarm_interrupt;
|
| 371 |
|
|
always @(posedge clk or negedge rst_n) begin
|
| 372 |
|
|
if(rst_n == 1'b0) alarm_interrupt <= 1'b0;
|
| 373 |
|
|
else if(io_read_valid && io_address == 1'b1 && ram_address == 7'h0C) alarm_interrupt <= 1'b0;
|
| 374 |
|
|
else if(sec_state == SEC_SECOND_START && alarm_interrupt_activate) alarm_interrupt <= 1'b1;
|
| 375 |
|
|
end
|
| 376 |
|
|
|
| 377 |
|
|
//------------------------------------------------------------------------------
|
| 378 |
|
|
|
| 379 |
|
|
/*
|
| 380 |
|
|
crb_freeze 1: no update, no alarm
|
| 381 |
|
|
*/
|
| 382 |
|
|
|
| 383 |
|
|
reg crb_freeze;
|
| 384 |
|
|
always @(posedge clk or negedge rst_n) begin
|
| 385 |
|
|
if(rst_n == 1'b0) crb_freeze <= 1'b0;
|
| 386 |
|
|
else if(mgmt_write && mgmt_address == 8'h0B) crb_freeze <= mgmt_writedata[7];
|
| 387 |
|
|
else if(io_write && io_address == 1'b1 && ram_address == 7'h0B) crb_freeze <= io_writedata[7];
|
| 388 |
|
|
end
|
| 389 |
|
|
|
| 390 |
|
|
reg crb_int_periodic_ena;
|
| 391 |
|
|
always @(posedge clk or negedge rst_n) begin
|
| 392 |
|
|
if(rst_n == 1'b0) crb_int_periodic_ena <= 1'b0;
|
| 393 |
|
|
else if(mgmt_write && mgmt_address == 8'h0B) crb_int_periodic_ena <= mgmt_writedata[6];
|
| 394 |
|
|
else if(io_write && io_address == 1'b1 && ram_address == 7'h0B) crb_int_periodic_ena <= io_writedata[6];
|
| 395 |
|
|
end
|
| 396 |
|
|
|
| 397 |
|
|
reg crb_int_alarm_ena;
|
| 398 |
|
|
always @(posedge clk or negedge rst_n) begin
|
| 399 |
|
|
if(rst_n == 1'b0) crb_int_alarm_ena <= 1'b0;
|
| 400 |
|
|
else if(mgmt_write && mgmt_address == 8'h0B) crb_int_alarm_ena <= mgmt_writedata[5];
|
| 401 |
|
|
else if(io_write && io_address == 1'b1 && ram_address == 7'h0B) crb_int_alarm_ena <= io_writedata[5];
|
| 402 |
|
|
end
|
| 403 |
|
|
|
| 404 |
|
|
reg crb_int_update_ena;
|
| 405 |
|
|
always @(posedge clk or negedge rst_n) begin
|
| 406 |
|
|
if(rst_n == 1'b0) crb_int_update_ena <= 1'b0;
|
| 407 |
|
|
else if(mgmt_write && mgmt_address == 8'h0B) crb_int_update_ena <= ~(mgmt_writedata[7]) & mgmt_writedata[4];
|
| 408 |
|
|
else if(io_write && io_address == 1'b1 && ram_address == 7'h0B) crb_int_update_ena <= ~(io_writedata[7]) & io_writedata[4];
|
| 409 |
|
|
end
|
| 410 |
|
|
|
| 411 |
|
|
reg crb_binarymode;
|
| 412 |
|
|
always @(posedge clk or negedge rst_n) begin
|
| 413 |
|
|
if(rst_n == 1'b0) crb_binarymode <= 1'b0;
|
| 414 |
|
|
else if(mgmt_write && mgmt_address == 8'h0B) crb_binarymode <= mgmt_writedata[2];
|
| 415 |
|
|
else if(io_write && io_address == 1'b1 && ram_address == 7'h0B) crb_binarymode <= io_writedata[2];
|
| 416 |
|
|
end
|
| 417 |
|
|
|
| 418 |
|
|
reg crb_24hour;
|
| 419 |
|
|
always @(posedge clk or negedge rst_n) begin
|
| 420 |
|
|
if(rst_n == 1'b0) crb_24hour <= 1'b1;
|
| 421 |
|
|
else if(mgmt_write && mgmt_address == 8'h0B) crb_24hour <= mgmt_writedata[1];
|
| 422 |
|
|
else if(io_write && io_address == 1'b1 && ram_address == 7'h0B) crb_24hour <= io_writedata[1];
|
| 423 |
|
|
end
|
| 424 |
|
|
|
| 425 |
|
|
reg crb_daylightsaving;
|
| 426 |
|
|
always @(posedge clk or negedge rst_n) begin
|
| 427 |
|
|
if(rst_n == 1'b0) crb_daylightsaving <= 1'b0;
|
| 428 |
|
|
else if(mgmt_write && mgmt_address == 8'h0B) crb_daylightsaving <= mgmt_writedata[0];
|
| 429 |
|
|
else if(io_write && io_address == 1'b1 && ram_address == 7'h0B) crb_daylightsaving <= io_writedata[0];
|
| 430 |
|
|
end
|
| 431 |
|
|
|
| 432 |
|
|
//------------------------------------------------------------------------------
|
| 433 |
|
|
|
| 434 |
|
|
/*
|
| 435 |
|
|
divider 00x : no periodic
|
| 436 |
|
|
divider 11x : no update, no alarm
|
| 437 |
|
|
*/
|
| 438 |
|
|
|
| 439 |
|
|
reg [2:0] divider;
|
| 440 |
|
|
always @(posedge clk or negedge rst_n) begin
|
| 441 |
|
|
if(rst_n == 1'b0) divider <= 3'd2;
|
| 442 |
|
|
else if(mgmt_write && mgmt_address == 8'h0A) divider <= mgmt_writedata[6:4];
|
| 443 |
|
|
else if(io_write && io_address == 1'b1 && ram_address == 7'h0A) divider <= io_writedata[6:4];
|
| 444 |
|
|
end
|
| 445 |
|
|
|
| 446 |
|
|
reg [3:0] periodic_rate;
|
| 447 |
|
|
always @(posedge clk or negedge rst_n) begin
|
| 448 |
|
|
if(rst_n == 1'b0) periodic_rate <= 4'd6;
|
| 449 |
|
|
else if(mgmt_write && mgmt_address == 8'h0A) periodic_rate <= mgmt_writedata[3:0];
|
| 450 |
|
|
else if(io_write && io_address == 1'b1 && ram_address == 7'h0A) periodic_rate <= io_writedata[3:0];
|
| 451 |
|
|
end
|
| 452 |
|
|
|
| 453 |
|
|
wire periodic_enabled = divider[2:1] != 2'b00 && periodic_rate != 4'd0;
|
| 454 |
|
|
wire periodic_start = periodic_enabled && (
|
| 455 |
|
|
(periodic_minor == 13'd0 && periodic_major == 13'd0) ||
|
| 456 |
|
|
(periodic_minor == 13'd0 && periodic_major == 13'd1));
|
| 457 |
|
|
wire periodic_count = periodic_enabled && periodic_major >= 13'd1;
|
| 458 |
|
|
|
| 459 |
|
|
wire [12:0] periodic_major_initial = {
|
| 460 |
|
|
periodic_rate == 4'd15, periodic_rate == 4'd14, periodic_rate == 4'd13, periodic_rate == 4'd12,
|
| 461 |
|
|
periodic_rate == 4'd11, periodic_rate == 4'd10, periodic_rate == 4'd9 || periodic_rate == 4'd2, periodic_rate == 4'd8 || periodic_rate == 4'd1,
|
| 462 |
|
|
periodic_rate == 4'd7, periodic_rate == 4'd6, periodic_rate == 4'd5, periodic_rate == 4'd4,
|
| 463 |
|
|
periodic_rate == 4'd3 };
|
| 464 |
|
|
|
| 465 |
|
|
reg [12:0] periodic_minor;
|
| 466 |
|
|
always @(posedge clk or negedge rst_n) begin
|
| 467 |
|
|
if(rst_n == 1'b0) periodic_minor <= 13'd0;
|
| 468 |
|
|
else if(~(periodic_enabled)) periodic_minor <= 13'd0;
|
| 469 |
|
|
else if(periodic_start) periodic_minor <= cycles_in_122us;
|
| 470 |
|
|
else if(periodic_count && periodic_minor == 13'd0) periodic_minor <= cycles_in_122us;
|
| 471 |
|
|
else if(periodic_count) periodic_minor <= periodic_minor - 13'd1;
|
| 472 |
|
|
end
|
| 473 |
|
|
|
| 474 |
|
|
reg [12:0] periodic_major;
|
| 475 |
|
|
always @(posedge clk or negedge rst_n) begin
|
| 476 |
|
|
if(rst_n == 1'b0) periodic_major <= 13'd0;
|
| 477 |
|
|
else if(~(periodic_enabled)) periodic_major <= 13'd0;
|
| 478 |
|
|
else if(periodic_start) periodic_major <= periodic_major_initial;
|
| 479 |
|
|
else if(periodic_count && periodic_minor == 13'd0) periodic_major <= periodic_major - 13'd1;
|
| 480 |
|
|
end
|
| 481 |
|
|
|
| 482 |
|
|
reg periodic_interrupt;
|
| 483 |
|
|
always @(posedge clk or negedge rst_n) begin
|
| 484 |
|
|
if(rst_n == 1'b0) periodic_interrupt <= 1'b0;
|
| 485 |
|
|
else if(io_read_valid && io_address == 1'b1 && ram_address == 7'h0C) periodic_interrupt <= 1'b0;
|
| 486 |
|
|
else if(periodic_enabled && periodic_minor == 13'd0 && periodic_major == 13'd1) periodic_interrupt <= 1'b1;
|
| 487 |
|
|
end
|
| 488 |
|
|
|
| 489 |
|
|
//------------------------------------------------------------------------------
|
| 490 |
|
|
|
| 491 |
|
|
reg [6:0] ram_address;
|
| 492 |
|
|
always @(posedge clk or negedge rst_n) begin
|
| 493 |
|
|
if(rst_n == 1'b0) ram_address <= 7'd0;
|
| 494 |
|
|
else if(io_write && io_address == 1'b0) ram_address <= io_writedata[6:0];
|
| 495 |
|
|
end
|
| 496 |
|
|
|
| 497 |
|
|
//------------------------------------------------------------------------------
|
| 498 |
|
|
|
| 499 |
|
|
wire [7:0] ram_q;
|
| 500 |
|
|
|
| 501 |
|
|
simple_ram #(
|
| 502 |
|
|
.width (8),
|
| 503 |
|
|
.widthad (7)
|
| 504 |
|
|
)
|
| 505 |
|
|
rtc_ram_inst(
|
| 506 |
|
|
.clk (clk),
|
| 507 |
|
|
|
| 508 |
|
|
.wraddress ((mgmt_write && mgmt_address[7] == 1'b0)? mgmt_address[6:0] : ram_address),
|
| 509 |
|
|
.wren ((mgmt_write && mgmt_address[7] == 1'b0) || (io_write && io_address == 1'b1)),
|
| 510 |
|
|
.data ((mgmt_write && mgmt_address[7] == 1'b0)? mgmt_writedata[7:0] : io_writedata),
|
| 511 |
|
|
|
| 512 |
|
|
.rdaddress ((io_write && io_address == 1'b0)? io_writedata[6:0] : ram_address),
|
| 513 |
|
|
.q (ram_q)
|
| 514 |
|
|
);
|
| 515 |
|
|
|
| 516 |
|
|
//------------------------------------------------------------------------------
|
| 517 |
|
|
|
| 518 |
|
|
// synthesis translate_off
|
| 519 |
|
|
wire _unused_ok = &{ 1'b0, mgmt_writedata[31:27], 1'b0 };
|
| 520 |
|
|
// synthesis translate_on
|
| 521 |
|
|
|
| 522 |
|
|
//------------------------------------------------------------------------------
|
| 523 |
|
|
|
| 524 |
|
|
endmodule
|
