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[/] [ao486/] [trunk/] [rtl/] [soc/] [sound/] [sound_dsp.v] - Blame information for rev 2

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1 2 alfik 
/*
2 
 * Copyright (c) 2014, Aleksander Osman
3 
 * All rights reserved.
4 
 *
5 
 * Redistribution and use in source and binary forms, with or without
6 
 * modification, are permitted provided that the following conditions are met:
7 
 *
8 
 * * Redistributions of source code must retain the above copyright notice, this
9 
 *   list of conditions and the following disclaimer.
10 
 *
11 
 * * Redistributions in binary form must reproduce the above copyright notice,
12 
 *   this list of conditions and the following disclaimer in the documentation
13 
 *   and/or other materials provided with the distribution.
14 
 *
15 
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
19 
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
22 
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
24 
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 
 */
26 
 
27 
module sound_dsp(
28 
    input               clk,
29 
    input               rst_n,
30 
 
31 
    output reg          irq,
32 
 
33 
    //io slave 220h-22Fh
34 
    input       [3:0]   io_address,
35 
    input               io_read,
36 
    output      [7:0]   io_readdata_from_dsp,
37 
    input               io_write,
38 
    input       [7:0]   io_writedata,
39 
 
40 
    //dma
41 
    output              dma_soundblaster_req,
42 
    input               dma_soundblaster_ack,
43 
    input               dma_soundblaster_terminal,
44 
    input       [7:0]   dma_soundblaster_readdata,
45 
    output      [7:0]   dma_soundblaster_writedata,
46 
 
47 
    //sample
48 
    output              sample_from_dsp_disabled,
49 
    output              sample_from_dsp_do,
50 
    output      [7:0]   sample_from_dsp_value,
51 
 
52 
    //mgmt slave
53 
    /*
54 
    0-255.[15:0]: cycles in period
55 
    */
56 
    input       [8:0]   mgmt_address,
57 
    input               mgmt_write,
58 
    input       [31:0]  mgmt_writedata
59 
);
60 
 
61 
//------------------------------------------------------------------------------
62 
 
63 
reg io_read_last;
64 
always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) io_read_last <= 1'b0; else if(io_read_last) io_read_last <= 1'b0; else io_read_last <= io_read; end
65 
wire io_read_valid = io_read && io_read_last == 1'b0;
66 
 
67 
//------------------------------------------------------------------------------
68 
 
69 
assign io_readdata_from_dsp =
70 
    (io_address == 4'hE)?                       { read_ready, 7'h7F } :
71 
    (io_address == 4'hA && copy_cnt > 6'd0)?    copyright_byte :
72 
    (io_address == 4'hA)?                       read_buffer[15:8] :
73 
    (io_address == 4'hC)?                       { write_ready, 7'h7F } :
74 
                                                8'hFF;
75 
 
76 
//------------------------------------------------------------------------------
77 
 
78 
wire highspeed_start = cmd_high_auto_dma_out || cmd_high_single_dma_out || cmd_high_auto_dma_input || cmd_high_single_dma_input;
79 
 
80 
reg highspeed_mode;
81 
always @(posedge clk or negedge rst_n) begin
82 
    if(rst_n == 1'b0)           highspeed_mode <= 1'b0;
83 
    else if(highspeed_reset)    highspeed_mode <= 1'b0;
84 
    else if(highspeed_start)    highspeed_mode <= 1'b1;
85 
    else if(dma_finished)       highspeed_mode <= 1'b0;
86 
end
87 
 
88 
reg midi_uart_mode;
89 
always @(posedge clk or negedge rst_n) begin
90 
    if(rst_n == 1'b0)           midi_uart_mode <= 1'b0;
91 
    else if(midi_uart_reset)    midi_uart_mode <= 1'b0;
92 
    else if(cmd_midi_uart)      midi_uart_mode <= 1'b1;
93 
end
94 
 
95 
reg reset_reg;
96 
always @(posedge clk or negedge rst_n) begin
97 
    if(rst_n == 1'b0)                                               reset_reg <= 1'b0;
98 
    else if(io_write && io_address == 4'h6 && ~(highspeed_mode))    reset_reg <= io_writedata[0];
99 
end
100 
 
101 
wire highspeed_reset = io_write && io_address == 4'h6 && highspeed_mode;
102 
wire midi_uart_reset = reset_reg && io_write && io_address == 4'h6 && ~(highspeed_mode) && midi_uart_mode    && io_writedata[0] == 1'b0;
103 
wire sw_reset        = reset_reg && io_write && io_address == 4'h6 && ~(highspeed_mode) && ~(midi_uart_mode) && io_writedata[0] == 1'b0;
104 
 
105 
//------------------------------------------------------------------------------ dummy input
106 
 
107 
wire input_strobe = cmd_direct_input || dma_input;
108 
 
109 
reg input_direction;
110 
always @(posedge clk or negedge rst_n) begin
111 
    if(rst_n == 1'b0)                                                       input_direction <= 1'b0;
112 
    else if(sw_reset)                                                       input_direction <= 1'b0;
113 
    else if(input_strobe && ~(input_direction) && input_sample == 8'd254)   input_direction <= 1'b1;
114 
    else if(input_strobe && input_direction    && input_sample == 8'd1)     input_direction <= 1'b0;
115 
end
116 
 
117 
reg [7:0] input_sample;
118 
always @(posedge clk or negedge rst_n) begin
119 
    if(rst_n == 1'b0)                           input_sample <= 8'd128;
120 
    else if(sw_reset)                           input_sample <= 8'd128;
121 
    else if(input_strobe && ~(input_direction)) input_sample <= input_sample + 8'd1;
122 
    else if(input_strobe && input_direction)    input_sample <= input_sample - 8'd1;
123 
end
124 
 
125 
assign dma_soundblaster_writedata = (dma_id_active)? dma_id_value : input_sample;
126 
 
127 
//------------------------------------------------------------------------------
128 
 
129 
wire cmd_single_byte = write_left == 2'd0 && io_write && io_address == 4'hC && ~(midi_uart_mode) && ~(highspeed_mode);
130 
 
131 
wire cmd_wait_for_2byte = write_left == 2'd0 && io_write && io_address == 4'hC && ~(midi_uart_mode) && ~(highspeed_mode) && (
132 
    io_writedata == 8'h10 || //direct output
133 
    io_writedata == 8'h38 || //midi   output
134 
    io_writedata == 8'h40 || //set time constant
135 
    io_writedata == 8'hE0 || //dsp identification
136 
    io_writedata == 8'hE4 || //write test register
137 
    io_writedata == 8'hE2    //dma id
138 
);
139 
wire cmd_wait_for_3byte = write_left == 2'd0 && io_write && io_address == 4'hC && ~(midi_uart_mode) && ~(highspeed_mode) && (
140 
    io_writedata == 8'h14 ||   //single cycle dma output
141 
    io_writedata == 8'h16 ||   //single cycle dma 2 bit adpcm output
142 
    io_writedata == 8'h17 ||   //single cycle dma 2 bit adpcm output with reference
143 
    io_writedata == 8'h74 ||   //single cycle dma 4 bit adpcm output
144 
    io_writedata == 8'h75 ||   //single cycle dma 4 bit adpcm output with reference
145 
    io_writedata == 8'h76 ||   //single cycle dma 4 bit adpcm output
146 
    io_writedata == 8'h77 ||   //single cycle dma 4 bit adpcm output with reference
147 
    io_writedata == 8'h24 ||   //single cycle dma input
148 
    io_writedata == 8'h48 ||   //set block size
149 
    io_writedata == 8'h80      //pause dac
150 
);
151 
 
152 
wire cmd_multiple_byte = write_length > 2'd0 && write_left == 2'd0 && ~(midi_uart_mode) && ~(highspeed_mode);
153 
 
154 
wire cmd_dsp_version            = cmd_single_byte && io_writedata == 8'hE1;
155 
wire cmd_direct_output          = cmd_multiple_byte && write_length == 2'd2 && write_buffer[15:8] == 8'h10;
156 
wire cmd_single_dma_output      = cmd_multiple_byte && write_length == 2'd3 && write_buffer[23:16] == 8'h14;
157 
wire cmd_single_2_adpcm_out     = cmd_multiple_byte && write_length == 2'd3 && write_buffer[23:16] == 8'h16;
158 
wire cmd_single_2_adpcm_out_ref = cmd_multiple_byte && write_length == 2'd3 && write_buffer[23:16] == 8'h17;
159 
wire cmd_single_4_adpcm_out     = cmd_multiple_byte && write_length == 2'd3 && write_buffer[23:16] == 8'h74;
160 
wire cmd_single_4_adpcm_out_ref = cmd_multiple_byte && write_length == 2'd3 && write_buffer[23:16] == 8'h75;
161 
wire cmd_single_3_adpcm_out     = cmd_multiple_byte && write_length == 2'd3 && write_buffer[23:16] == 8'h76;
162 
wire cmd_single_3_adpcm_out_ref = cmd_multiple_byte && write_length == 2'd3 && write_buffer[23:16] == 8'h77;
163 
 
164 
wire cmd_single_dma_input       = cmd_multiple_byte && write_length == 2'd3 && write_buffer[23:16] == 8'h24;
165 
 
166 
wire cmd_auto_dma_out           = cmd_single_byte && io_writedata == 8'h1C;
167 
wire cmd_auto_dma_exit          = cmd_single_byte && io_writedata == 8'hDA;
168 
 
169 
wire cmd_auto_2_adpcm_out_ref   = cmd_single_byte && io_writedata == 8'h1F;
170 
wire cmd_auto_3_adpcm_out_ref   = cmd_single_byte && io_writedata == 8'h7F;
171 
wire cmd_auto_4_adpcm_out_ref   = cmd_single_byte && io_writedata == 8'h7D;
172 
 
173 
wire cmd_direct_input           = cmd_single_byte && io_writedata == 8'h20;
174 
wire cmd_auto_dma_input         = cmd_single_byte && io_writedata == 8'h2C;
175 
 
176 
//wire cmd_midi_polling_input     = cmd_single_byte && io_writedata == 8'h30;
177 
//wire cmd_midi_interrupt_input   = cmd_single_byte && io_writedata == 8'h31;
178 
 
179 
wire cmd_midi_uart              = cmd_single_byte && { io_writedata[7:2], 2'b00 } == 8'h34;
180 
//wire cmd_midi_output            = cmd_multiple_byte && write_length == 2'd2 && write_buffer[15:8] == 8'h38;
181 
 
182 
wire cmd_set_time_constant      = cmd_multiple_byte && write_length == 2'd2 && write_buffer[15:8] == 8'h40;
183 
wire cmd_set_block_size         = cmd_multiple_byte && write_length == 2'd3 && write_buffer[23:16] == 8'h48;
184 
 
185 
wire cmd_pause_dac              = cmd_multiple_byte && write_length == 2'd3 && write_buffer[23:16] == 8'h80;
186 
 
187 
wire cmd_high_auto_dma_out      = cmd_single_byte && io_writedata == 8'h90;
188 
wire cmd_high_single_dma_out    = cmd_single_byte && io_writedata == 8'h91;
189 
 
190 
wire cmd_high_auto_dma_input    = cmd_single_byte && io_writedata == 8'h98;
191 
wire cmd_high_single_dma_input  = cmd_single_byte && io_writedata == 8'h99;
192 
 
193 
wire cmd_dma_pause_start        = cmd_single_byte && io_writedata == 8'hD0;
194 
wire cmd_dma_pause_end          = cmd_single_byte && io_writedata == 8'hD4;
195 
 
196 
wire cmd_speaker_on             = cmd_single_byte && io_writedata == 8'hD1;
197 
wire cmd_speaker_off            = cmd_single_byte && io_writedata == 8'hD3;
198 
wire cmd_speaker_status         = cmd_single_byte && io_writedata == 8'hD8;
199 
 
200 
wire cmd_dsp_identification     = cmd_multiple_byte && write_length == 2'd2 && write_buffer[15:8] == 8'hE0;
201 
wire cmd_f8_zero                = cmd_single_byte && io_writedata == 8'hF8;
202 
wire cmd_trigger_irq            = cmd_single_byte && io_writedata == 8'hF2;
203 
 
204 
wire cmd_test_register_write    = cmd_multiple_byte && write_length == 2'd2 && write_buffer[15:8] == 8'hE4;
205 
wire cmd_test_register_read     = cmd_single_byte && io_writedata == 8'hE8;
206 
 
207 
wire cmd_copyright              = cmd_single_byte && io_writedata == 8'hE3;
208 
wire cmd_dma_id                 = cmd_multiple_byte && write_length == 2'd2 && write_buffer[15:8] == 8'hE2;
209 
 
210 
//------------------------------------------------------------------------------ 'weird dma identification' from DosBox
211 
 
212 
reg [1:0] dma_id_count;
213 
always @(posedge clk or negedge rst_n) begin
214 
    if(rst_n == 1'b0)   dma_id_count <= 2'd0;
215 
    else if(sw_reset)   dma_id_count <= 2'd0;
216 
    else if(cmd_dma_id) dma_id_count <= dma_id_count + 2'd1;
217 
end
218 
 
219 
reg [7:0] dma_id_value;
220 
always @(posedge clk or negedge rst_n) begin
221 
    if(rst_n == 1'b0)   dma_id_value <= 8'hAA;
222 
    else if(sw_reset)   dma_id_value <= 8'hAA;
223 
    else if(cmd_dma_id) dma_id_value <= dma_id_value + dma_id_q;
224 
end
225 
 
226 
reg dma_id_active;
227 
always @(posedge clk or negedge rst_n) begin
228 
    if(rst_n == 1'b0)               dma_id_active <= 1'b0;
229 
    else if(sw_reset)               dma_id_active <= 1'b0;
230 
    else if(cmd_dma_id)             dma_id_active <= 1'b1;
231 
    else if(dma_soundblaster_ack)   dma_id_active <= 1'b0;
232 
end
233 
 
234 
wire [7:0] dma_id_q;
235 
 
236 
simple_single_rom #(
237 
    .widthad    (10),
238 
    .width      (8),
239 
    .datafile   ("./../soc/sound/dsp_dma_identification_rom.hex")
240 
)
241 
dma_id_rom_inst (
242 
    .clk        (clk),
243 
 
244 
    .addr       ({dma_id_count, io_writedata}),
245 
    .q          (dma_id_q)
246 
);
247 
 
248 
//------------------------------------------------------------------------------ copyright
249 
 
250 
reg [5:0] copy_cnt;
251 
always @(posedge clk or negedge rst_n) begin
252 
    if(rst_n == 1'b0)                                               copy_cnt <= 6'd0;
253 
    else if(cmd_copyright)                                          copy_cnt <= 6'd45;
254 
    else if(io_read_valid && io_address == 4'hA && copy_cnt > 6'd0) copy_cnt <= copy_cnt - 6'd1;
255 
end
256 
 
257 
wire [7:0] copyright_byte =
258 
    (copy_cnt == 6'd45 || copy_cnt == 6'd34 || copy_cnt == 6'd31 || copy_cnt == 6'd20)?                     8'h43 : //C
259 
    (copy_cnt == 6'd44 || copy_cnt == 6'd17 || copy_cnt == 6'd15)?                                          8'h4F : //O
260 
    (copy_cnt == 6'd43)?                                                                                    8'h50 : //P
261 
    (copy_cnt == 6'd42 || copy_cnt == 6'd13)?                                                               8'h59 : //Y
262 
    (copy_cnt == 6'd41 || copy_cnt == 6'd30)?                                                               8'h52 : //R
263 
    (copy_cnt == 6'd40 || copy_cnt == 6'd26)?                                                               8'h49 : //I
264 
    (copy_cnt == 6'd39 || copy_cnt == 6'd14)?                                                               8'h47 : //G
265 
    (copy_cnt == 6'd38 || copy_cnt == 6'd19)?                                                               8'h48 : //H
266 
    (copy_cnt == 6'd37 || copy_cnt == 6'd27 || copy_cnt == 6'd22 || copy_cnt == 6'd10)?                     8'h54 : //T
267 
    (copy_cnt == 6'd36 || copy_cnt == 6'd32 || copy_cnt == 6'd23 || copy_cnt == 6'd12 || copy_cnt == 6'd7)? 8'h20 : //' '
268 
    (copy_cnt == 6'd35)?                                                                                    8'h28 : //(
269 
    (copy_cnt == 6'd33)?                                                                                    8'h29 : //)
270 
    (copy_cnt == 6'd29 || copy_cnt == 6'd24 || copy_cnt == 6'd21)?                                          8'h45 : //E
271 
    (copy_cnt == 6'd28)?                                                                                    8'h41 : //A
272 
    (copy_cnt == 6'd25)?                                                                                    8'h56 : //V
273 
    (copy_cnt == 6'd18)?                                                                                    8'h4E : //N
274 
    (copy_cnt == 6'd16 || copy_cnt == 6'd11)?                                                               8'h4C : //L
275 
    (copy_cnt == 6'd13)?                                                                                    8'h59 : //Y
276 
    (copy_cnt == 6'd9)?                                                                                     8'h44 : //D
277 
    (copy_cnt == 6'd8)?                                                                                     8'h2C : //,
278 
    (copy_cnt == 6'd6)?                                                                                     8'h31 : //1
279 
    (copy_cnt == 6'd5 || copy_cnt == 6'd4)?                                                                 8'h39 : //9
280 
    (copy_cnt == 6'd3)?                                                                                     8'h32 : //2
281 
    (copy_cnt == 6'd2)?                                                                                     8'h2E : //.
282 
                                                                                                            8'h00;  //for copy_cnt == 6'd1
283 
//------------------------------------------------------------------------------
284 
 
285 
reg [7:0] test_register;
286 
always @(posedge clk or negedge rst_n) begin
287 
    if(rst_n == 1'b0)                   test_register <= 8'd0;
288 
    else if(cmd_test_register_write)    test_register <= write_buffer[7:0];
289 
end
290 
 
291 
reg speaker_on;
292 
always @(posedge clk or negedge rst_n) begin
293 
    if(rst_n == 1'b0)           speaker_on <= 1'b0;
294 
    else if(sw_reset)           speaker_on <= 1'b0;
295 
    else if(cmd_speaker_on)     speaker_on <= 1'b1;
296 
    else if(cmd_speaker_off)    speaker_on <= 1'b0;
297 
end
298 
 
299 
reg [15:0] block_size;
300 
always @(posedge clk or negedge rst_n) begin
301 
    if(rst_n == 1'b0)           block_size <= 16'd0;
302 
    else if(sw_reset)           block_size <= 16'd0;
303 
    else if(cmd_set_block_size) block_size <= { write_buffer[7:0], write_buffer[15:8] };
304 
end
305 
 
306 
reg pause_dma;
307 
always @(posedge clk or negedge rst_n) begin
308 
    if(rst_n == 1'b0)                                                   pause_dma <= 1'b0;
309 
    else if(sw_reset)                                                   pause_dma <= 1'b0;
310 
    else if(cmd_dma_pause_start)                                        pause_dma <= 1'b1;
311 
    else if(cmd_dma_pause_end || dma_single_start || dma_auto_start)    pause_dma <= 1'b0;
312 
end
313 
 
314 
//------------------------------------------------------------------------------ pause dac
315 
 
316 
wire pause_interrupt = pause_counter == 16'd0 && pause_period == 16'd1;
317 
 
318 
reg pause_active;
319 
always @(posedge clk or negedge rst_n) begin
320 
    if(rst_n == 1'b0)                                           pause_active <= 1'b0;
321 
    else if(sw_reset)                                           pause_active <= 1'b0;
322 
    else if(cmd_pause_dac)                                      pause_active <= 1'b1;
323 
    else if(pause_counter == 16'd0 && pause_period == 16'd0)    pause_active <= 1'b0;
324 
end
325 
 
326 
reg [15:0] pause_counter;
327 
always @(posedge clk or negedge rst_n) begin
328 
    if(rst_n == 1'b0)                                       pause_counter <= 16'd0;
329 
    else if(sw_reset)                                       pause_counter <= 16'd0;
330 
    else if(cmd_pause_dac)                                  pause_counter <= { write_buffer[7:0], write_buffer[15:8] };
331 
    else if(pause_period == 16'd0 && pause_counter > 16'd0) pause_counter <= pause_counter - 16'd1;
332 
end
333 
 
334 
reg [15:0] pause_period;
335 
always @(posedge clk or negedge rst_n) begin
336 
    if(rst_n == 1'b0)                                       pause_period <= 16'd0;
337 
    else if(sw_reset)                                       pause_period <= 16'd0;
338 
    else if(cmd_pause_dac)                                  pause_period <= period_q;
339 
    else if(pause_period == 16'd0 && pause_counter > 16'd0) pause_period <= period_q;
340 
    else if(pause_period > 16'd0)                           pause_period <= pause_period - 16'd1;
341 
end
342 
 
343 
//------------------------------------------------------------------------------
344 
 
345 
wire write_ready = midi_uart_mode || highspeed_mode;
346 
 
347 
reg [1:0] write_length;
348 
always @(posedge clk or negedge rst_n) begin
349 
    if(rst_n == 1'b0)                           write_length <= 2'd0;
350 
    else if(sw_reset)                           write_length <= 2'd0;
351 
    else if(cmd_midi_uart || highspeed_start)   write_length <= 2'd0;
352 
    else if(cmd_wait_for_2byte)                 write_length <= 2'd2;
353 
    else if(cmd_wait_for_3byte)                 write_length <= 2'd3;
354 
    else if(write_left == 2'd0)                 write_length <= 2'd0;
355 
end
356 
 
357 
reg [1:0] write_left;
358 
always @(posedge clk or negedge rst_n) begin
359 
    if(rst_n == 1'b0)                                               write_left <= 2'd0;
360 
    else if(sw_reset)                                               write_left <= 2'd0;
361 
    else if(cmd_midi_uart || highspeed_start)                       write_left <= 2'd0;
362 
    else if(cmd_wait_for_2byte)                                     write_left <= 2'd1;
363 
    else if(cmd_wait_for_3byte)                                     write_left <= 2'd2;
364 
    else if(io_write && io_address == 4'hC && write_left > 2'd0)    write_left <= write_left - 2'd1;
365 
end
366 
 
367 
reg [23:0] write_buffer;
368 
always @(posedge clk or negedge rst_n) begin
369 
    if(rst_n == 1'b0)                                               write_buffer <= 24'd0;
370 
    else if(sw_reset)                                               write_buffer <= 24'd0;
371 
    else if(cmd_wait_for_2byte || cmd_wait_for_3byte)               write_buffer <= { write_buffer[15:0], io_writedata };
372 
    else if(io_write && io_address == 4'hC && write_left > 2'd0)    write_buffer <= { write_buffer[15:0], io_writedata };
373 
end
374 
 
375 
//------------------------------------------------------------------------------
376 
 
377 
wire read_ready = ~(midi_uart_mode) && read_buffer_size > 2'd0;
378 
 
379 
reg [1:0] read_buffer_size;
380 
always @(posedge clk or negedge rst_n) begin
381 
    if(rst_n == 1'b0)                                                   read_buffer_size <= 2'd0;
382 
    else if(sw_reset)                                                   read_buffer_size <= 2'd1;
383 
    else if(cmd_dsp_version)                                            read_buffer_size <= 2'd2;
384 
    else if(cmd_direct_input)                                           read_buffer_size <= 2'd1;
385 
    else if(cmd_midi_uart)                                              read_buffer_size <= 2'd0;
386 
    else if(cmd_speaker_status)                                         read_buffer_size <= 2'd1;
387 
    else if(cmd_dsp_identification)                                     read_buffer_size <= 2'd1;
388 
    else if(cmd_f8_zero)                                                read_buffer_size <= 2'd1;
389 
    else if(cmd_test_register_read)                                     read_buffer_size <= 2'd1;
390 
    else if(cmd_copyright)                                              read_buffer_size <= 2'd0;
391 
 
392 
    else if(io_read_valid && io_address == 4'hA && read_buffer_size > 2'd0) read_buffer_size <= read_buffer_size - 2'd1;
393 
end
394 
 
395 
reg [15:0] read_buffer;
396 
always @(posedge clk or negedge rst_n) begin
397 
    if(rst_n == 1'b0)                                                   read_buffer <= 16'd0;
398 
    else if(sw_reset)                                                   read_buffer <= { 8'hAA, 8'h00 };
399 
    else if(cmd_dsp_version)                                            read_buffer <= { 8'h02, 8'h01 };
400 
    else if(cmd_direct_input)                                           read_buffer <= { input_sample, 8'h00 };
401 
    else if(cmd_speaker_status)                                         read_buffer <= { (speaker_on)? 8'hFF : 8'h00, 8'h00 };
402 
    else if(cmd_dsp_identification)                                     read_buffer <= { ~(write_buffer[7:0]), 8'h00 };
403 
    else if(cmd_f8_zero)                                                read_buffer <= { 8'h00, 8'h00 };
404 
    else if(cmd_test_register_read)                                     read_buffer <= { test_register, 8'h00 };
405 
 
406 
    else if(io_read_valid && io_address == 4'hA && read_buffer_size > 2'd0) read_buffer <= { read_buffer[7:0], 8'd0 };
407 
end
408 
 
409 
//------------------------------------------------------------------------------ irq
410 
 
411 
always @(posedge clk or negedge rst_n) begin
412 
    if(rst_n == 1'b0)                                               irq <= 1'b0;
413 
    else if(sw_reset)                                               irq <= 1'b0;
414 
 
415 
    else if(dma_finished || dma_auto_restart || pause_interrupt)    irq <= 1'b1;
416 
    else if(cmd_trigger_irq)                                        irq <= 1'b1;
417 
 
418 
    else if(io_read_valid && io_address == 4'hE)                    irq <= 1'b0;
419 
end
420 
 
421 
//------------------------------------------------------------------------------ dma commands
422 
 
423 
localparam [4:0] S_IDLE                 = 5'd0;
424 
localparam [4:0] S_OUT_SINGLE_8_BIT     = 5'd1;
425 
localparam [4:0] S_OUT_SINGLE_4_BIT     = 5'd2;
426 
localparam [4:0] S_OUT_SINGLE_3_BIT     = 5'd3;
427 
localparam [4:0] S_OUT_SINGLE_2_BIT     = 5'd4;
428 
localparam [4:0] S_OUT_SINGLE_4_BIT_REF = 5'd5;
429 
localparam [4:0] S_OUT_SINGLE_3_BIT_REF = 5'd6;
430 
localparam [4:0] S_OUT_SINGLE_2_BIT_REF = 5'd7;
431 
localparam [4:0] S_OUT_AUTO_8_BIT       = 5'd8;
432 
localparam [4:0] S_OUT_AUTO_4_BIT_REF   = 5'd9;
433 
localparam [4:0] S_OUT_AUTO_3_BIT_REF   = 5'd10;
434 
localparam [4:0] S_OUT_AUTO_2_BIT_REF   = 5'd11;
435 
localparam [4:0] S_IN_SINGLE            = 5'd12;
436 
localparam [4:0] S_IN_AUTO              = 5'd13;
437 
localparam [4:0] S_OUT_SINGLE_HIGH      = 5'd14;
438 
localparam [4:0] S_OUT_AUTO_HIGH        = 5'd15;
439 
localparam [4:0] S_IN_SINGLE_HIGH       = 5'd16;
440 
localparam [4:0] S_IN_AUTO_HIGH         = 5'd17;
441 
 
442 
reg [4:0] dma_command;
443 
 
444 
always @(posedge clk or negedge rst_n) begin
445 
    if(rst_n == 1'b0)                           dma_command <= S_IDLE;
446 
    else if(sw_reset)                           dma_command <= S_IDLE;
447 
 
448 
    else if(cmd_single_dma_output)              dma_command <= S_OUT_SINGLE_8_BIT;
449 
    else if(cmd_single_4_adpcm_out)             dma_command <= S_OUT_SINGLE_4_BIT;
450 
    else if(cmd_single_3_adpcm_out)             dma_command <= S_OUT_SINGLE_3_BIT;
451 
    else if(cmd_single_2_adpcm_out)             dma_command <= S_OUT_SINGLE_2_BIT;
452 
 
453 
    else if(cmd_single_4_adpcm_out_ref)         dma_command <= S_OUT_SINGLE_4_BIT_REF;
454 
    else if(cmd_single_3_adpcm_out_ref)         dma_command <= S_OUT_SINGLE_3_BIT_REF;
455 
    else if(cmd_single_2_adpcm_out_ref)         dma_command <= S_OUT_SINGLE_2_BIT_REF;
456 
 
457 
    else if(cmd_auto_dma_out)                   dma_command <= S_OUT_AUTO_8_BIT;
458 
    else if(cmd_auto_4_adpcm_out_ref)           dma_command <= S_OUT_AUTO_4_BIT_REF;
459 
    else if(cmd_auto_3_adpcm_out_ref)           dma_command <= S_OUT_AUTO_3_BIT_REF;
460 
    else if(cmd_auto_2_adpcm_out_ref)           dma_command <= S_OUT_AUTO_2_BIT_REF;
461 
 
462 
    else if(cmd_single_dma_input)               dma_command <= S_IN_SINGLE;
463 
    else if(cmd_auto_dma_input)                 dma_command <= S_IN_AUTO;
464 
 
465 
    else if(cmd_high_single_dma_out)            dma_command <= S_OUT_SINGLE_HIGH;
466 
    else if(cmd_high_auto_dma_out)              dma_command <= S_OUT_AUTO_HIGH;
467 
 
468 
    else if(cmd_high_single_dma_input)          dma_command <= S_IN_SINGLE_HIGH;
469 
    else if(cmd_high_auto_dma_input)            dma_command <= S_IN_AUTO_HIGH;
470 
 
471 
    else if(dma_single_start || dma_auto_start) dma_command <= S_IDLE;
472 
end
473 
 
474 
//------------------------------------------------------------------------------ dma
475 
 
476 
wire dma_single_start = dma_restart_possible && (
477 
    dma_command == S_OUT_SINGLE_8_BIT || dma_command == S_OUT_SINGLE_4_BIT     || dma_command == S_OUT_SINGLE_3_BIT     || dma_command == S_OUT_SINGLE_2_BIT     ||
478 
                                         dma_command == S_OUT_SINGLE_4_BIT_REF || dma_command == S_OUT_SINGLE_3_BIT_REF || dma_command == S_OUT_SINGLE_2_BIT_REF ||
479 
    dma_command == S_IN_SINGLE ||
480 
    dma_command == S_OUT_SINGLE_HIGH || dma_command == S_IN_SINGLE_HIGH
481 
);
482 
 
483 
wire dma_auto_start = dma_restart_possible && (
484 
    dma_command == S_OUT_AUTO_8_BIT || dma_command == S_OUT_AUTO_4_BIT_REF || dma_command == S_OUT_AUTO_3_BIT_REF || dma_command == S_OUT_AUTO_2_BIT_REF ||
485 
    dma_command == S_IN_AUTO ||
486 
    dma_command == S_OUT_AUTO_HIGH || dma_command == S_IN_AUTO_HIGH
487 
);
488 
 
489 
wire dma_normal_req = dma_in_progress && dma_wait == 16'd0 && adpcm_wait == 2'd0 && ~(pause_dma);
490 
 
491 
assign dma_soundblaster_req = dma_id_active || dma_normal_req;
492 
 
493 
wire dma_valid  = dma_normal_req && dma_soundblaster_ack && ~(dma_id_active);
494 
wire dma_output = ~(dma_is_input) && dma_valid;
495 
wire dma_input  = dma_is_input    && dma_valid;
496 
 
497 
wire dma_finished = dma_in_progress && ~(dma_autoinit) && (
498 
    (dma_valid && dma_left == 17'd1 && adpcm_type == ADPCM_NONE) ||
499 
    (adpcm_output && dma_left == 17'd0 && adpcm_type != ADPCM_NONE && adpcm_wait == 2'd1)
500 
);
501 
 
502 
wire dma_auto_restart = dma_in_progress && dma_autoinit && (
503 
    (dma_valid && dma_left == 17'd1 && adpcm_type == ADPCM_NONE) ||
504 
    (adpcm_output && dma_left == 17'd0 && adpcm_type != ADPCM_NONE && adpcm_wait == 2'd1)
505 
);
506 
 
507 
wire dma_restart_possible = dma_wait == 16'd0 && (adpcm_wait == 2'd0 || (adpcm_type != ADPCM_NONE && adpcm_wait == 2'd1)) && (~(dma_in_progress) || dma_auto_restart || pause_dma);
508 
 
509 
reg [16:0] dma_left;
510 
always @(posedge clk or negedge rst_n) begin
511 
    if(rst_n == 1'b0)                           dma_left <= 17'd0;
512 
    else if(sw_reset)                           dma_left <= 17'd0;
513 
    else if(dma_single_start)                   dma_left <= { write_buffer[7:0], write_buffer[15:8] } + 16'd1;
514 
    else if(dma_auto_start || dma_auto_restart) dma_left <= block_size + 16'd1;
515 
    else if(dma_valid && dma_left > 17'd0)      dma_left <= dma_left - 17'd1;
516 
    else if(dma_finished)                       dma_left <= 17'd0;
517 
end
518 
 
519 
reg dma_in_progress;
520 
always @(posedge clk or negedge rst_n) begin
521 
    if(rst_n == 1'b0)                           dma_in_progress <= 1'b0;
522 
    else if(sw_reset)                           dma_in_progress <= 1'b0;
523 
    else if(dma_single_start || dma_auto_start) dma_in_progress <= 1'b1;
524 
    else if(dma_finished)                       dma_in_progress <= 1'b0;
525 
end
526 
 
527 
reg dma_is_input;
528 
always @(posedge clk or negedge rst_n) begin
529 
    if(rst_n == 1'b0)                                                                                                                                                               dma_is_input <= 1'b0;
530 
    else if(sw_reset)                                                                                                                                                               dma_is_input <= 1'b0;
531 
    else if((dma_single_start || dma_auto_start) && (dma_command == S_IN_SINGLE || dma_command == S_IN_AUTO || dma_command == S_IN_SINGLE_HIGH || dma_command == S_IN_AUTO_HIGH))   dma_is_input <= 1'b1;
532 
    else if(dma_single_start || dma_auto_start)                                                                                                                                     dma_is_input <= 1'b0;
533 
end
534 
 
535 
reg dma_autoinit;
536 
always @(posedge clk or negedge rst_n) begin
537 
    if(rst_n == 1'b0)           dma_autoinit <= 1'b0;
538 
    else if(sw_reset)           dma_autoinit <= 1'b0;
539 
    else if(dma_single_start)   dma_autoinit <= 1'b0;
540 
    else if(dma_auto_start)     dma_autoinit <= 1'b1;
541 
    else if(cmd_auto_dma_exit)  dma_autoinit <= 1'b0;
542 
end
543 
 
544 
reg [15:0] dma_wait;
545 
always @(posedge clk or negedge rst_n) begin
546 
    if(rst_n == 1'b0)                                                                                                   dma_wait <= 16'd0;
547 
    else if(sw_reset)                                                                                                   dma_wait <= 16'd0;
548 
    else if(dma_finished || dma_valid || adpcm_output || (~(dma_in_progress) && (dma_single_start || dma_auto_start)))  dma_wait <= period_q;
549 
    else if(dma_wait > 16'd0)                                                                                           dma_wait <= dma_wait - 16'd1;
550 
end
551 
 
552 
//------------------------------------------------------------------------------ adpcm
553 
 
554 
localparam [1:0] ADPCM_NONE = 2'd0;
555 
localparam [1:0] ADPCM_4BIT = 2'd1;
556 
localparam [1:0] ADPCM_3BIT = 2'd2;
557 
localparam [1:0] ADPCM_2BIT = 2'd3;
558 
 
559 
wire adpcm_reference_start =
560 
    (dma_single_start || dma_auto_start) && (
561 
    dma_command == S_OUT_SINGLE_2_BIT_REF || dma_command == S_OUT_SINGLE_3_BIT_REF || dma_command == S_OUT_SINGLE_4_BIT_REF ||
562 
    dma_command == S_OUT_AUTO_2_BIT_REF   || dma_command == S_OUT_AUTO_3_BIT_REF   || dma_command == S_OUT_AUTO_4_BIT_REF
563 
);
564 
 
565 
wire adpcm_output = dma_wait == 16'd0 && adpcm_wait > 2'd0;
566 
 
567 
reg adpcm_reference_awaiting;
568 
always @(posedge clk or negedge rst_n) begin
569 
    if(rst_n == 1'b0)                               adpcm_reference_awaiting <= 1'b0;
570 
    else if(sw_reset)                               adpcm_reference_awaiting <= 1'b0;
571 
    else if(adpcm_reference_start)                  adpcm_reference_awaiting <= 1'b1;
572 
    else if(dma_single_start || dma_auto_start)     adpcm_reference_awaiting <= 1'b0;
573 
    else if(adpcm_reference_awaiting && dma_output) adpcm_reference_awaiting <= 1'b0;
574 
    else if(dma_finished)                           adpcm_reference_awaiting <= 1'b0;
575 
end
576 
 
577 
reg adpcm_reference_output;
578 
always @(posedge clk or negedge rst_n) begin
579 
    if(rst_n == 1'b0)   adpcm_reference_output <= 1'b0;
580 
    else                adpcm_reference_output <= adpcm_reference_awaiting;
581 
end
582 
 
583 
reg [1:0] adpcm_wait;
584 
always @(posedge clk or negedge rst_n) begin
585 
    if(rst_n == 1'b0)                               adpcm_wait <= 2'd0;
586 
    else if(sw_reset)                               adpcm_wait <= 2'd0;
587 
    else if(dma_single_start || dma_auto_start)     adpcm_wait <= 2'd0;
588 
    else if(adpcm_reference_awaiting && dma_output) adpcm_wait <= 2'd0;
589 
    else if(dma_output && adpcm_type == ADPCM_2BIT) adpcm_wait <= 2'd3;
590 
    else if(dma_output && adpcm_type == ADPCM_3BIT) adpcm_wait <= 2'd2;
591 
    else if(dma_output && adpcm_type == ADPCM_4BIT) adpcm_wait <= 2'd1;
592 
    else if(adpcm_output && adpcm_wait > 2'd0)      adpcm_wait <= adpcm_wait - 2'd1;
593 
end
594 
 
595 
reg [7:0] adpcm_sample;
596 
always @(posedge clk or negedge rst_n) begin
597 
    if(rst_n == 1'b0)                                   adpcm_sample <= 8'd0;
598 
    else if(sw_reset)                                   adpcm_sample <= 8'd0;
599 
    else if(dma_output)                                 adpcm_sample <= dma_soundblaster_readdata;
600 
    else if(adpcm_output && adpcm_type == ADPCM_2BIT)   adpcm_sample <= { adpcm_sample[5:0], 2'b0 };
601 
    else if(adpcm_output && adpcm_type == ADPCM_3BIT)   adpcm_sample <= { adpcm_sample[4:0], 3'b0 };
602 
    else if(adpcm_output && adpcm_type == ADPCM_4BIT)   adpcm_sample <= { adpcm_sample[3:0], 4'b0 };
603 
end
604 
 
605 
reg adpcm_active;
606 
always @(posedge clk or negedge rst_n) begin
607 
    if(rst_n == 1'b0)                                   adpcm_active <= 1'b0;
608 
    else if(sw_reset)                                   adpcm_active <= 1'b0;
609 
    else if(adpcm_reference_awaiting && dma_output)     adpcm_active <= 1'b0;
610 
    else if(adpcm_type != ADPCM_NONE && dma_output)     adpcm_active <= 1'b1;
611 
    else if(adpcm_output)                               adpcm_active <= 1'b1;
612 
    else                                                adpcm_active <= 1'b0;
613 
end
614 
 
615 
wire [7:0] adpcm_active_value =
616 
    (adpcm_type == ADPCM_2BIT)?     adpcm_2bit_reference_next :
617 
    (adpcm_type == ADPCM_3BIT)?     adpcm_3bit_reference_next :
618 
                                    adpcm_4bit_reference_next;
619 
 
620 
reg [1:0] adpcm_type;
621 
always @(posedge clk or negedge rst_n) begin
622 
    if(rst_n == 1'b0)                                                                                                                                                       adpcm_type <= ADPCM_NONE;
623 
    else if(sw_reset)                                                                                                                                                       adpcm_type <= ADPCM_NONE;
624 
    else if((dma_single_start || dma_auto_start) && (dma_command == S_OUT_SINGLE_2_BIT_REF || dma_command == S_OUT_SINGLE_2_BIT || dma_command == S_OUT_AUTO_2_BIT_REF))    adpcm_type <= ADPCM_2BIT;
625 
    else if((dma_single_start || dma_auto_start) && (dma_command == S_OUT_SINGLE_3_BIT_REF || dma_command == S_OUT_SINGLE_3_BIT || dma_command == S_OUT_AUTO_3_BIT_REF))    adpcm_type <= ADPCM_3BIT;
626 
    else if((dma_single_start || dma_auto_start) && (dma_command == S_OUT_SINGLE_4_BIT_REF || dma_command == S_OUT_SINGLE_4_BIT || dma_command == S_OUT_AUTO_4_BIT_REF))    adpcm_type <= ADPCM_4BIT;
627 
    else if((dma_single_start || dma_auto_start))                                                                                                                           adpcm_type <= ADPCM_NONE;
628 
    else if(dma_finished)                                                                                                                                                   adpcm_type <= ADPCM_NONE;
629 
end
630 
 
631 
reg [2:0] adpcm_step;
632 
always @(posedge clk or negedge rst_n) begin
633 
    if(rst_n == 1'b0)                                   adpcm_step <= 3'd0;
634 
    else if(sw_reset)                                   adpcm_step <= 3'd0;
635 
    else if(adpcm_active && adpcm_type == ADPCM_2BIT)   adpcm_step <= adpcm_2bit_step_next;
636 
    else if(adpcm_active && adpcm_type == ADPCM_3BIT)   adpcm_step <= adpcm_3bit_step_next;
637 
    else if(adpcm_active && adpcm_type == ADPCM_4BIT)   adpcm_step <= adpcm_4bit_step_next;
638 
    else if(adpcm_reference_awaiting && dma_output)     adpcm_step <= 3'd0;
639 
end
640 
 
641 
reg [7:0] adpcm_reference;
642 
always @(posedge clk or negedge rst_n) begin
643 
    if(rst_n == 1'b0)                                   adpcm_reference <= 8'd0;
644 
    else if(sw_reset)                                   adpcm_reference <= 8'd0;
645 
    else if(adpcm_active && adpcm_type == ADPCM_2BIT)   adpcm_reference <= adpcm_2bit_reference_next;
646 
    else if(adpcm_active && adpcm_type == ADPCM_3BIT)   adpcm_reference <= adpcm_3bit_reference_next;
647 
    else if(adpcm_active && adpcm_type == ADPCM_4BIT)   adpcm_reference <= adpcm_4bit_reference_next;
648 
    else if(adpcm_reference_awaiting && dma_output)     adpcm_reference <= dma_soundblaster_readdata;
649 
end
650 
 
651 
//------------------------------------------------------------------------------ adpcm 2 bit
652 
 
653 
wire [1:0] adpcm_2bit_sample = adpcm_sample[7:6];
654 
 
655 
wire [7:0] adpcm_2bit_reference_adjust =
656 
    (adpcm_step[2:0] == 3'd0)?      { 7'd0, adpcm_2bit_sample[0] } :
657 
    (adpcm_step[2:0] == 3'd1)?      { 6'd0, adpcm_2bit_sample[0], 1'b1 } :
658 
    (adpcm_step[2:0] == 3'd2)?      { 5'd0, adpcm_2bit_sample[0], 2'b10 } :
659 
    (adpcm_step[2:0] == 3'd3)?      { 4'd0, adpcm_2bit_sample[0], 3'b100 } :
660 
    (adpcm_step[2:0] == 3'd4)?      { 3'd0, adpcm_2bit_sample[0], 4'b1000 } :
661 
                                    { 2'd0, adpcm_2bit_sample[0], 5'b10000 }; //adpcm_step[2:0] == 3'd5
662 
 
663 
wire [8:0] adpcm_2bit_reference_sum = adpcm_reference + adpcm_2bit_reference_adjust;
664 
wire [8:0] adpcm_2bit_reference_sub = adpcm_reference - adpcm_2bit_reference_adjust;
665 
 
666 
wire [7:0] adpcm_2bit_reference_next =
667 
    (adpcm_2bit_sample[1] && adpcm_2bit_reference_sub[8])?  8'd0 :
668 
    (adpcm_2bit_sample[1])?                                 adpcm_2bit_reference_sub[7:0] :
669 
    (adpcm_2bit_reference_sum[8])?                          8'd255 :
670 
                                                            adpcm_2bit_reference_sum[7:0];
671 
wire [2:0] adpcm_2bit_step_next =
672 
    (adpcm_step < 3'd5 && adpcm_2bit_sample[0] == 1'b1)?    adpcm_step + 3'd1 :
673 
    (adpcm_step > 3'd0 && adpcm_2bit_sample[0] == 1'b0)?    adpcm_step - 3'd1 :
674 
                                                            adpcm_step;
675 
 
676 
//------------------------------------------------------------------------------ adpcm 3 bit
677 
 
678 
wire [2:0] adpcm_3bit_sample = adpcm_sample[7:5];
679 
 
680 
wire [7:0] adpcm_3bit_reference_adjust =
681 
    (adpcm_step[2:0] == 3'd0)?                                  { 6'd0, adpcm_3bit_sample[1:0] } :
682 
    (adpcm_step[2:0] == 3'd1)?                                  { 5'd0, adpcm_3bit_sample[1:0], 1'b1 } :
683 
    (adpcm_step[2:0] == 3'd2)?                                  { 4'd0, adpcm_3bit_sample[1:0], 2'b10 } :
684 
    (adpcm_step[2:0] == 3'd3)?                                  { 3'd0, adpcm_3bit_sample[1:0], 3'b100 } :
685 
    (adpcm_step[2:0] == 3'd4 && adpcm_3bit_sample == 3'd0)?     8'd5 :
686 
    (adpcm_step[2:0] == 3'd4 && adpcm_3bit_sample == 3'd1)?     8'd15 :
687 
    (adpcm_step[2:0] == 3'd4 && adpcm_3bit_sample == 3'd2)?     8'd25 :
688 
                                                                8'd35;
689 
 
690 
wire [8:0] adpcm_3bit_reference_sum = adpcm_reference + adpcm_3bit_reference_adjust;
691 
wire [8:0] adpcm_3bit_reference_sub = adpcm_reference - adpcm_3bit_reference_adjust;
692 
 
693 
wire [7:0] adpcm_3bit_reference_next =
694 
    (adpcm_3bit_sample[2] && adpcm_3bit_reference_sub[8])?  8'd0 :
695 
    (adpcm_3bit_sample[2])?                                 adpcm_3bit_reference_sub[7:0] :
696 
    (adpcm_3bit_reference_sum[8])?                          8'd255 :
697 
                                                            adpcm_3bit_reference_sum[7:0];
698 
wire [2:0] adpcm_3bit_step_next =
699 
    (adpcm_step < 3'd4 && adpcm_3bit_sample[1:0] == 2'b11)? adpcm_step + 3'd1 :
700 
    (adpcm_step > 3'd0 && adpcm_3bit_sample[1:0] == 2'b00)? adpcm_step - 3'd1 :
701 
                                                            adpcm_step;
702 
 
703 
//------------------------------------------------------------------------------ adpcm 4 bit
704 
 
705 
wire [3:0] adpcm_4bit_sample = adpcm_sample[7:4];
706 
 
707 
wire [7:0] adpcm_4bit_reference_adjust =
708 
    (adpcm_step[2:0] == 3'd0)?      { 5'd0, adpcm_4bit_sample[2:0] } :
709 
    (adpcm_step[2:0] == 3'd1)?      { 4'd0, adpcm_4bit_sample[2:0], 1'b1 } :
710 
    (adpcm_step[2:0] == 3'd2)?      { 3'd0, adpcm_4bit_sample[2:0], 2'b10 } :
711 
                                    { 2'd0, adpcm_4bit_sample[2:0], 3'b100 }; //adpcm_step[2:0] == 3'd3
712 
 
713 
wire [8:0] adpcm_4bit_reference_sum = adpcm_reference + adpcm_4bit_reference_adjust;
714 
wire [8:0] adpcm_4bit_reference_sub = adpcm_reference - adpcm_4bit_reference_adjust;
715 
 
716 
wire [7:0] adpcm_4bit_reference_next =
717 
    (adpcm_4bit_sample[3] && adpcm_4bit_reference_sub[8])?  8'd0 :
718 
    (adpcm_4bit_sample[3])?                                 adpcm_4bit_reference_sub[7:0] :
719 
    (adpcm_4bit_reference_sum[8])?                          8'd255 :
720 
                                                            adpcm_4bit_reference_sum[7:0];
721 
wire [2:0] adpcm_4bit_step_next =
722 
    (adpcm_step < 3'd3 && adpcm_4bit_sample[2:0] >= 3'd5)?  adpcm_step + 3'd1 :
723 
    (adpcm_step > 3'd0 && adpcm_4bit_sample[2:0] == 3'd0)?  adpcm_step - 3'd1 :
724 
                                                            adpcm_step;
725 
 
726 
//------------------------------------------------------------------------------
727 
 
728 
reg [7:0] period_address;
729 
always @(posedge clk or negedge rst_n) begin
730 
    if(rst_n == 1'b0)               period_address <= 8'd128;
731 
    else if(sw_reset)               period_address <= 8'd128;
732 
    else if(cmd_set_time_constant)  period_address <= write_buffer[7:0];
733 
end
734 
 
735 
wire [15:0] period_q;
736 
 
737 
simple_ram #(
738 
    .widthad    (8),
739 
    .width      (16)
740 
)
741 
period_ram_inst(
742 
    .clk                (clk),
743 
 
744 
    .wraddress          (mgmt_address[7:0]),
745 
    .wren               (mgmt_write && mgmt_address[8] == 1'b0),
746 
    .data               (mgmt_writedata[15:0]),
747 
 
748 
    .rdaddress          (period_address),
749 
    .q                  (period_q)
750 
);
751 
 
752 
//------------------------------------------------------------------------------
753 
 
754 
assign sample_from_dsp_disabled = ~(speaker_on) || pause_active;
755 
assign sample_from_dsp_do = ~(sample_from_dsp_disabled) && ((dma_output && adpcm_type == ADPCM_NONE) || cmd_direct_output || adpcm_active || (~(adpcm_reference_awaiting) && adpcm_reference_output));
756 
 
757 
assign sample_from_dsp_value =
758 
    (adpcm_reference_output)?   adpcm_sample :
759 
    (adpcm_active)?             adpcm_active_value :
760 
    (dma_output)?               dma_soundblaster_readdata :
761 
                                write_buffer[7:0];
762 
 
763 
//------------------------------------------------------------------------------
764 
 
765 
// synthesis translate_off
766 
wire _unused_ok = &{ 1'b0, mgmt_writedata[31:16], dma_soundblaster_terminal, 1'b0 };
767 
// synthesis translate_on
768 
 
769 
//------------------------------------------------------------------------------
770 
 
771 
endmodule

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