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[/] [ao486/] [trunk/] [sim/] [iverilog/] [rtc/] [tb_rtc.v] - Blame information for rev 2

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1 2 alfik
 
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`timescale 1 ps / 1 ps
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module tb_rtc();
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reg clk;
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reg rst_n;
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wire interrupt;
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reg         io_address      = 1'b0;
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reg         io_read         = 1'b0;
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wire [7:0]  io_readdata;
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reg         io_write        = 1'b0;
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reg  [7:0]  io_writedata    = 8'd0;
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reg  [7:0]  mgmt_address    = 8'd0;
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reg         mgmt_write      = 1'b0;
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reg  [31:0] mgmt_writedata  = 32'd0;
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rtc rtc_inst(
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    .clk                (clk),
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    .rst_n              (rst_n),
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    .interrupt          (interrupt),      //output
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    //io slave
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    .io_address         (io_address),     //input
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    .io_read            (io_read),        //input
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    .io_readdata        (io_readdata),    //output [7:0]
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    .io_write           (io_write),       //input
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    .io_writedata       (io_writedata),   //input [7:0]
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    //mgmt slave
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    /*
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    128.[26:0]: cycles in second
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    129.[12:0]: cycles in 122.07031 us
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    */
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    .mgmt_address       (mgmt_address),       //input [7:0]
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    .mgmt_write         (mgmt_write),         //input
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    .mgmt_writedata     (mgmt_writedata)      //input [31:0]
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);
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//------------------------------------------------------------------------------
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initial begin
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    clk = 1'b0;
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    forever #5 clk = ~clk;
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end
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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integer finished = 0;
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reg [255:0] dumpfile_name;
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initial begin
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    if( $value$plusargs("dumpfile=%s", dumpfile_name) == 0 ) begin
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        dumpfile_name = "default.vcd";
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    end
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    $dumpfile(dumpfile_name);
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    $dumpvars(0);
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    $dumpon();
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    $display("START");
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    rst_n = 1'b0;
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    #10 rst_n = 1'b1;
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    while(finished == 0) begin
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        if($time > 200000) $finish_and_return(-1);
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        #10;
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        //$dumpflush();
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    end
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    #60;
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    $dumpoff();
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    $finish_and_return(0);
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end
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//------------------------------------------------------------------------------
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endmodule

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