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/*

// vga mode 0x04 40x25 320x200

wire seq_9pixel_char = 1'b0;

wire seq_dotclock_divided = 1'b1;

wire [7:0] crtc_horizontal_total          = 8'd45; // +5 real value

wire [7:0] crtc_horizontal_display_size   = 8'd39; // +1 for full display size

wire [7:0] crtc_horizontal_blanking_start = 8'd40; // start on this character

wire [5:0] crtc_horizontal_blanking_end   = 6'd48; // blank for 8 character clocks (one side); last 47; 48 first after

wire [7:0] crtc_horizontal_retrace_start  = 8'd43; // start on this

wire [4:0] crtc_horizontal_retrace_end    = 5'd0;  // retrace for 21 character clocks (one side); last 63; 64 first after

wire [9:0] crtc_vertical_total            = 10'd447;

wire [9:0] crtc_vertical_display_size     = 10'd399; // 0-399 active display = 400 lines

wire [9:0] crtc_vertical_blanking_start   = 10'd406; // starts on this line

wire [6:0] crtc_vertical_blanking_end     = 7'd57;  // 35 lines (one side); last 440; 441 first after

wire [9:0] crtc_vertical_retrace_start    = 10'd412; // starts on this line

wire [3:0] crtc_vertical_retrace_end      = 4'd14;  // 2 lines (one side); last 413; 414 first after

wire       crtc_vertical_doublescan       = 1'b1;

wire general_vsync = 1'b0; //pusle is ~(general_vsync)

wire general_hsync = 1'b1; //pusle is ~(general_vsync)

*/

/*

// vga mode 0x06 640x200

wire seq_9pixel_char = 1'b0;

wire seq_dotclock_divided = 1'b0;

wire [7:0] crtc_horizontal_total          = 8'd95; // +5 real value

wire [7:0] crtc_horizontal_display_size   = 8'd79; // +1 for full display size

wire [7:0] crtc_horizontal_blanking_start = 8'd80; // start on this character

wire [5:0] crtc_horizontal_blanking_end   = 6'd34; // blank for 18 character clocks (one side); last 97; 98 first after

wire [7:0] crtc_horizontal_retrace_start  = 8'd84; // start on this

wire [4:0] crtc_horizontal_retrace_end    = 5'd0;  // retrace for 12 character clocks (one side); last 95; 96 first after

wire [9:0] crtc_vertical_total            = 10'd447;

wire [9:0] crtc_vertical_display_size     = 10'd399; // 0-399 active display = 400 lines

wire [9:0] crtc_vertical_blanking_start   = 10'd406; // starts on this line

wire [6:0] crtc_vertical_blanking_end     = 7'd57;  // 35 lines (one side); last 440; 441 first after

wire [9:0] crtc_vertical_retrace_start    = 10'd412; // starts on this line

wire [3:0] crtc_vertical_retrace_end      = 4'd14;  // 2 lines (one side); last 413; 414 first after

wire       crtc_vertical_doublescan       = 1'b1;

wire general_vsync = 1'b0; //pusle is ~(general_vsync)

wire general_hsync = 1'b1; //pusle is ~(general_vsync)

*/

/*

// vga mode 0x07 720x400

wire seq_9pixel_char = 1'b1;

wire seq_dotclock_divided = 1'b0;

wire [7:0] crtc_horizontal_total          = 8'd95; // +5 real value

wire [7:0] crtc_horizontal_display_size   = 8'd79; // +1 for full display size

wire [7:0] crtc_horizontal_blanking_start = 8'd80; // start on this character

wire [5:0] crtc_horizontal_blanking_end   = 6'd34; // blank for 18 character clocks (one side); last 97; 98 first after

wire [7:0] crtc_horizontal_retrace_start  = 8'd85; // start on this

wire [4:0] crtc_horizontal_retrace_end    = 5'd1;  // retrace for 12 character clocks (one side); last 96; 97 first after

wire [9:0] crtc_vertical_total            = 10'd447;

wire [9:0] crtc_vertical_display_size     = 10'd399; // 0-399 active display = 400 lines

wire [9:0] crtc_vertical_blanking_start   = 10'd406; // starts on this line

wire [6:0] crtc_vertical_blanking_end     = 7'd57;  // 35 lines (one side); last 440; 441 first after

wire [9:0] crtc_vertical_retrace_start    = 10'd412; // starts on this line

wire [3:0] crtc_vertical_retrace_end      = 4'd14;  // 2 lines (one side); last 413; 414 first after

wire       crtc_vertical_doublescan       = 1'b0;

wire general_vsync = 1'b0; //pusle is ~(general_vsync)

wire general_hsync = 1'b1; //pusle is ~(general_vsync)

*/

/*

// vga mode 0x0d 320x200

wire seq_9pixel_char = 1'b0;

wire seq_dotclock_divided = 1'b1;

wire [7:0] crtc_horizontal_total          = 8'd45; // +5 real value

wire [7:0] crtc_horizontal_display_size   = 8'd39; // +1 for full display size

wire [7:0] crtc_horizontal_blanking_start = 8'd40; // start on this character

wire [5:0] crtc_horizontal_blanking_end   = 6'd48; // blank for 8 character clocks (one side); last 47; 48 first after

wire [7:0] crtc_horizontal_retrace_start  = 8'd43; // start on this

wire [4:0] crtc_horizontal_retrace_end    = 5'd0;  // retrace for 21 character clocks (one side); last 63; 64 first after

wire [9:0] crtc_vertical_total            = 10'd447;

wire [9:0] crtc_vertical_display_size     = 10'd399; // 0-399 active display = 400 lines

wire [9:0] crtc_vertical_blanking_start   = 10'd406; // starts on this line

wire [6:0] crtc_vertical_blanking_end     = 7'd57;  // 35 lines (one side); last 440; 441 first after

wire [9:0] crtc_vertical_retrace_start    = 10'd412; // starts on this line

wire [3:0] crtc_vertical_retrace_end      = 4'd14;  // 2 lines (one side); last 413; 414 first after

wire       crtc_vertical_doublescan       = 1'b1;

wire general_vsync = 1'b0; //pusle is ~(general_vsync)

wire general_hsync = 1'b1; //pusle is ~(general_vsync)

*/

/*

// vga mode 0x0e 640x200

wire seq_9pixel_char = 1'b0;

wire seq_dotclock_divided = 1'b0;

wire [7:0] crtc_horizontal_total          = 8'd95; // +5 real value

wire [7:0] crtc_horizontal_display_size   = 8'd79; // +1 for full display size

wire [7:0] crtc_horizontal_blanking_start = 8'd80; // start on this character

wire [5:0] crtc_horizontal_blanking_end   = 6'd34; // blank for 18 character clocks (one side); last 97; 98 first after

wire [7:0] crtc_horizontal_retrace_start  = 8'd84; // start on this

wire [4:0] crtc_horizontal_retrace_end    = 5'd0;  // retrace for 12 character clocks (one side); last 95; 96 first after

wire [9:0] crtc_vertical_total            = 10'd447;

wire [9:0] crtc_vertical_display_size     = 10'd399; // 0-399 active display = 400 lines

wire [9:0] crtc_vertical_blanking_start   = 10'd406; // starts on this line

wire [6:0] crtc_vertical_blanking_end     = 7'd57;  // 35 lines (one side); last 440; 441 first after

wire [9:0] crtc_vertical_retrace_start    = 10'd412; // starts on this line

wire [3:0] crtc_vertical_retrace_end      = 4'd14;  // 2 lines (one side); last 413; 414 first after

wire       crtc_vertical_doublescan       = 1'b1;

wire general_vsync = 1'b0; //pusle is ~(general_vsync)

wire general_hsync = 1'b1; //pusle is ~(general_vsync)

*/

/*

// vga mode 0x0f 640x350

wire seq_9pixel_char = 1'b0;

wire seq_dotclock_divided = 1'b0;

wire [7:0] crtc_horizontal_total          = 8'd95; // +5 real value

wire [7:0] crtc_horizontal_display_size   = 8'd79; // +1 for full display size

wire [7:0] crtc_horizontal_blanking_start = 8'd80; // start on this character

wire [5:0] crtc_horizontal_blanking_end   = 6'd34; // blank for 18 character clocks (one side); last 97; 98 first after

wire [7:0] crtc_horizontal_retrace_start  = 8'd84; // start on this

wire [4:0] crtc_horizontal_retrace_end    = 5'd0;  // retrace for 12 character clocks (one side); last 95; 96 first after

wire [9:0] crtc_vertical_total            = 10'd447;

wire [9:0] crtc_vertical_display_size     = 10'd349; // 0-349 active display = 350 lines

wire [9:0] crtc_vertical_blanking_start   = 10'd355; // starts on this line

wire [6:0] crtc_vertical_blanking_end     = 7'd58;  // 87 lines (one side); last 441; 442 first after

wire [9:0] crtc_vertical_retrace_start    = 10'd387; // starts on this line

wire [3:0] crtc_vertical_retrace_end      = 4'd5;  // 2 lines (one side); last 388; 389 first after

wire       crtc_vertical_doublescan       = 1'b0;

wire general_vsync = 1'b1; //pusle is ~(general_vsync)

wire general_hsync = 1'b0; //pusle is ~(general_vsync)

*/

/*

// vga mode 0x10 640x350

wire seq_9pixel_char = 1'b0;

wire seq_dotclock_divided = 1'b0;

wire [7:0] crtc_horizontal_total          = 8'd95; // +5 real value

wire [7:0] crtc_horizontal_display_size   = 8'd79; // +1 for full display size

wire [7:0] crtc_horizontal_blanking_start = 8'd80; // start on this character

wire [5:0] crtc_horizontal_blanking_end   = 6'd34; // blank for 18 character clocks (one side); last 97; 98 first after

wire [7:0] crtc_horizontal_retrace_start  = 8'd84; // start on this

wire [4:0] crtc_horizontal_retrace_end    = 5'd0;  // retrace for 12 character clocks (one side); last 95; 96 first after

wire [9:0] crtc_vertical_total            = 10'd447;

wire [9:0] crtc_vertical_display_size     = 10'd349; // 0-349 active display = 350 lines

wire [9:0] crtc_vertical_blanking_start   = 10'd355; // starts on this line

wire [6:0] crtc_vertical_blanking_end     = 7'd58;  // 87 lines (one side); last 441; 442 first after

wire [9:0] crtc_vertical_retrace_start    = 10'd387; // starts on this line

wire [3:0] crtc_vertical_retrace_end      = 4'd5;  // 2 lines (one side); last 388; 389 first after

wire       crtc_vertical_doublescan       = 1'b0;

wire general_vsync = 1'b1; //pusle is ~(general_vsync)

wire general_hsync = 1'b0; //pusle is ~(general_vsync)

*/

/*

// vga mode 0x01 360x400

wire seq_9pixel_char = 1'b1;

wire seq_dotclock_divided = 1'b1;

wire [7:0] crtc_horizontal_total          = 8'd45; // +5 real value

wire [7:0] crtc_horizontal_display_size   = 8'd39; // +1 for full display size

wire [7:0] crtc_horizontal_blanking_start = 8'd40; // start on this character

wire [5:0] crtc_horizontal_blanking_end   = 6'd48; // blank for 8 character clocks (one side); last 47; 48 first after

wire [7:0] crtc_horizontal_retrace_start  = 8'd43; // start on this

wire [4:0] crtc_horizontal_retrace_end    = 5'd0;  // retrace for 21 character clocks (one side); last 63; 64 first after

wire [9:0] crtc_vertical_total            = 10'd447;

wire [9:0] crtc_vertical_display_size     = 10'd399; // 0-399 active display = 400 lines

wire [9:0] crtc_vertical_blanking_start   = 10'd406; // starts on this line

wire [6:0] crtc_vertical_blanking_end     = 7'd57;  // 35 lines (one side); last 440; 441 first after

wire [9:0] crtc_vertical_retrace_start    = 10'd412; // starts on this line

wire [3:0] crtc_vertical_retrace_end      = 4'd14;  // 2 lines (one side); last 413; 414 first after

wire       crtc_vertical_doublescan       = 1'b0;

wire general_vsync = 1'b0; //pusle is ~(general_vsync)

wire general_hsync = 1'b1; //pusle is ~(general_vsync)

*/

/*

// vga mode 0x03 720x400

wire seq_9pixel_char = 1'b1;

wire seq_dotclock_divided = 1'b0;

wire [7:0] crtc_horizontal_total          = 8'd95; // +5 real value

wire [7:0] crtc_horizontal_display_size   = 8'd79; // +1 for full display size

wire [7:0] crtc_horizontal_blanking_start = 8'd80; // start on this character

wire [5:0] crtc_horizontal_blanking_end   = 6'd34; // blank for 18 character clocks (one side); last 97; 98 first after

wire [7:0] crtc_horizontal_retrace_start  = 8'd85; // start on this

wire [4:0] crtc_horizontal_retrace_end    = 5'd1;  // retrace for 12 character clocks (one side); last 96; 97 first after

wire [9:0] crtc_vertical_total            = 10'd447;

wire [9:0] crtc_vertical_display_size     = 10'd399; // 0-399 active display = 400 lines

wire [9:0] crtc_vertical_blanking_start   = 10'd406; // starts on this line

wire [6:0] crtc_vertical_blanking_end     = 7'd57;  // 35 lines (one side); last 440; 441 first after

wire [9:0] crtc_vertical_retrace_start    = 10'd412; // starts on this line

wire [3:0] crtc_vertical_retrace_end      = 4'd14;  // 2 lines (one side); last 413; 414 first after

wire       crtc_vertical_doublescan       = 1'b0;

wire general_vsync = 1'b0; //pusle is ~(general_vsync)

wire general_hsync = 1'b1; //pusle is ~(general_vsync)

*/

/*

// vga mode 0x07 720x400

wire seq_9pixel_char = 1'b1;

wire seq_dotclock_divided = 1'b0;

wire [7:0] crtc_horizontal_total          = 8'd95; // +5 real value

wire [7:0] crtc_horizontal_display_size   = 8'd79; // +1 for full display size

wire [7:0] crtc_horizontal_blanking_start = 8'd80; // start on this character

wire [5:0] crtc_horizontal_blanking_end   = 6'd34; // blank for 18 character clocks (one side); last 97; 98 first after

wire [7:0] crtc_horizontal_retrace_start  = 8'd85; // start on this

wire [4:0] crtc_horizontal_retrace_end    = 5'd1;  // retrace for 12 character clocks (one side); last 96; 97 first after

wire [9:0] crtc_vertical_total            = 10'd447;

wire [9:0] crtc_vertical_display_size     = 10'd399; // 0-399 active display = 400 lines

wire [9:0] crtc_vertical_blanking_start   = 10'd406; // starts on this line

wire [6:0] crtc_vertical_blanking_end     = 7'd57;  // 35 lines (one side); last 440; 441 first after

wire [9:0] crtc_vertical_retrace_start    = 10'd412; // starts on this line

wire [3:0] crtc_vertical_retrace_end      = 4'd14;  // 2 lines (one side); last 413; 414 first after

wire       crtc_vertical_doublescan       = 1'b0;

wire general_vsync = 1'b0; //pusle is ~(general_vsync)

wire general_hsync = 1'b1; //pusle is ~(general_vsync)

*/

/*

// vga mode 0x11 640x480

wire seq_9pixel_char = 1'b0;

wire seq_dotclock_divided = 1'b0;

wire [7:0] crtc_horizontal_total          = 8'd95; // +5 real value

wire [7:0] crtc_horizontal_display_size   = 8'd79; // +1 for full display size

wire [7:0] crtc_horizontal_blanking_start = 8'd80; // start on this character

wire [5:0] crtc_horizontal_blanking_end   = 6'd34; // blank for 18 character clocks (one side); last 97; 98 first after

wire [7:0] crtc_horizontal_retrace_start  = 8'd84; // start on this

wire [4:0] crtc_horizontal_retrace_end    = 5'd0;  // retrace for 12 character clocks (one side); last 95; 96 first after

wire [9:0] crtc_vertical_total            = 10'd523;

wire [9:0] crtc_vertical_display_size     = 10'd479; // 0-479 active display = 480 lines

wire [9:0] crtc_vertical_blanking_start   = 10'd487; // starts on this line

wire [6:0] crtc_vertical_blanking_end     = 7'd4;  // 29 lines (one side); last 515; 516 first after

wire [9:0] crtc_vertical_retrace_start    = 10'd490; // starts on this line

wire [3:0] crtc_vertical_retrace_end      = 4'd12;  // 2 lines (one side); last 491; 492 first after

wire       crtc_vertical_doublescan       = 1'b0;

wire general_vsync = 1'b1; //pusle is ~(general_vsync)

wire general_hsync = 1'b1; //pusle is ~(general_vsync)

*/

/*

// vga mode 0x12 640x480

wire seq_9pixel_char = 1'b0;

wire seq_dotclock_divided = 1'b0;

wire [7:0] crtc_horizontal_total          = 8'd95; // +5 real value

wire [7:0] crtc_horizontal_display_size   = 8'd79; // +1 for full display size

wire [7:0] crtc_horizontal_blanking_start = 8'd80; // start on this character

wire [5:0] crtc_horizontal_blanking_end   = 6'd34; // blank for 18 character clocks (one side); last 97; 98 first after

wire [7:0] crtc_horizontal_retrace_start  = 8'd84; // start on this

wire [4:0] crtc_horizontal_retrace_end    = 5'd0;  // retrace for 12 character clocks (one side); last 95; 96 first after

wire [9:0] crtc_vertical_total            = 10'd523;

wire [9:0] crtc_vertical_display_size     = 10'd479; // 0-479 active display = 480 lines

wire [9:0] crtc_vertical_blanking_start   = 10'd487; // starts on this line

wire [6:0] crtc_vertical_blanking_end     = 7'd4;  // 29 lines (one side); last 515; 516 first after

wire [9:0] crtc_vertical_retrace_start    = 10'd490; // starts on this line

wire [3:0] crtc_vertical_retrace_end      = 4'd12;  // 2 lines (one side); last 491; 492 first after

wire       crtc_vertical_doublescan       = 1'b0;

wire general_vsync = 1'b1; //pusle is ~(general_vsync)

wire general_hsync = 1'b1; //pusle is ~(general_vsync)

*/

/*

// vga mode 0x13 320x200

wire seq_9pixel_char = 1'b0;

wire seq_dotclock_divided = 1'b0;

wire [7:0] crtc_horizontal_total          = 8'd95; // +5 real value

wire [7:0] crtc_horizontal_display_size   = 8'd79; // +1 for full display size

wire [7:0] crtc_horizontal_blanking_start = 8'd80; // start on this character

wire [5:0] crtc_horizontal_blanking_end   = 6'd34; // blank for 18 character clocks (one side); last 97; 98 first after

wire [7:0] crtc_horizontal_retrace_start  = 8'd84; // start on this

wire [4:0] crtc_horizontal_retrace_end    = 5'd0;  // retrace for 12 character clocks (one side); last 95; 96 first after

wire [9:0] crtc_vertical_total            = 10'd447;

wire [9:0] crtc_vertical_display_size     = 10'd399; // 0-399 active display = 400 lines

wire [9:0] crtc_vertical_blanking_start   = 10'd406; // starts on this line

wire [6:0] crtc_vertical_blanking_end     = 7'd57;  // 35 lines (one side); last 440; 441 first after

wire [9:0] crtc_vertical_retrace_start    = 10'd412; // starts on this line

wire [3:0] crtc_vertical_retrace_end      = 4'd14;  // 2 lines (one side); last 413; 414 first after

wire       crtc_vertical_doublescan       = 1'b0;

wire general_vsync = 1'b0; //pusle is ~(general_vsync)

wire general_hsync = 1'b1; //pusle is ~(general_vsync)

*/

/*

// vga mode 0x6a 800x600

wire seq_9pixel_char = 1'b0;

wire seq_dotclock_divided = 1'b0;

wire [7:0] crtc_horizontal_total          = 8'd127; // +5 real value

wire [7:0] crtc_horizontal_display_size   = 8'd99; // +1 for full display size

wire [7:0] crtc_horizontal_blanking_start = 8'd99; // start on this character

wire [5:0] crtc_horizontal_blanking_end   = 6'd3; // blank for 32 character clocks (one side); last 130; 131 first after

wire [7:0] crtc_horizontal_retrace_start  = 8'd107; // start on this

wire [4:0] crtc_horizontal_retrace_end    = 5'd27;  // retrace for 16 character clocks (one side); last 122; 123 first after

wire [9:0] crtc_vertical_total            = 10'd626;

wire [9:0] crtc_vertical_display_size     = 10'd599; // 0-599 active display = 600 lines

wire [9:0] crtc_vertical_blanking_start   = 10'd599; // starts on this line

wire [6:0] crtc_vertical_blanking_end     = 7'd115;  // 28 lines (one side); last 626; 627 first after

wire [9:0] crtc_vertical_retrace_start    = 10'd601; // starts on this line

wire [3:0] crtc_vertical_retrace_end      = 4'd13;  // 4 lines (one side); last 604; 605 first after

wire       crtc_vertical_doublescan       = 1'b0;

wire general_vsync = 1'b1; //pusle is ~(general_vsync)

wire general_hsync = 1'b1; //pusle is ~(general_vsync)

*/