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alfik |
module main(
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input clk,
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input rst_n,
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//--------------------------------------------------------------------------
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input interrupt_do,
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input [7:0] interrupt_vector,
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output interrupt_done,
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//-------------------------------------------------------------------------- Altera Avalon io bus
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output [15:0] avalon_io_address,
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output [3:0] avalon_io_byteenable,
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output avalon_io_read,
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input avalon_io_readdatavalid,
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input [31:0] avalon_io_readdata,
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output avalon_io_write,
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output [31:0] avalon_io_writedata,
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input avalon_io_waitrequest,
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//memory master
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output [31:0] sdram_address,
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output [3:0] sdram_byteenable,
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output sdram_read,
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input [31:0] sdram_readdata,
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output sdram_write,
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output [31:0] sdram_writedata,
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input sdram_waitrequest,
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input sdram_readdatavalid,
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output [2:0] sdram_burstcount,
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//vga master
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output [31:0] vga_address,
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output [3:0] vga_byteenable,
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output vga_read,
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input [31:0] vga_readdata,
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output vga_write,
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output [31:0] vga_writedata,
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input vga_waitrequest,
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input vga_readdatavalid,
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output [2:0] vga_burstcount,
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//----------------------- debug
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output tb_finish_instr,
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//SW
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output [15:0] dbg_io_address,
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output [3:0] dbg_io_byteenable,
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output dbg_io_write,
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output dbg_io_read,
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output [31:0] dbg_io_data,
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output [7:0] dbg_int_vector,
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output dbg_int,
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output [7:0] dbg_exc_vector,
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output dbg_exc,
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output [31:0] dbg_mem_address,
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output [3:0] dbg_mem_byteenable,
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output dbg_mem_write,
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output dbg_mem_read,
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output [31:0] dbg_mem_data
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);
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//------------------------------------------------------------------------------
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wire [31:0] avm_address;
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wire [31:0] avm_writedata;
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wire [3:0] avm_byteenable;
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wire [2:0] avm_burstcount;
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wire avm_write;
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wire avm_read;
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wire avm_waitrequest = mem_waitrequest;
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wire avm_readdatavalid = mem_readdatavalid;
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wire [31:0] avm_readdata = mem_readdata;
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wire [31:0] mem_readdata;
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wire mem_waitrequest;
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wire mem_readdatavalid;
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wire [29:0] mem_address = avm_address[31:2];
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wire [3:0] mem_byteenable = avm_byteenable;
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wire mem_read = avm_read;
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wire mem_write = avm_write;
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wire [31:0] mem_writedata = avm_writedata;
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wire [2:0] mem_burstcount = avm_burstcount;
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//------------------------------------------------------------------------------
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wire [17:0] SW = 18'h0007F;
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ao486 ao486_inst(
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.clk (clk), //input
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.rst_n (rst_n), //input
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.rst_internal_n (rst_n), //input
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//--------------------------------------------------------------------------
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.interrupt_do (interrupt_do), //input
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.interrupt_vector (interrupt_vector), //input [7:0]
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.interrupt_done (interrupt_done), //output
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//-------------------------------------------------------------------------- Altera Avalon memory bus
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.avm_address (avm_address), //output [31:0]
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.avm_writedata (avm_writedata), //output [31:0]
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.avm_byteenable (avm_byteenable), //output [3:0]
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.avm_burstcount (avm_burstcount), //output [2:0]
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.avm_write (avm_write), //output
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.avm_read (avm_read), //output
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.avm_waitrequest (avm_waitrequest), //input
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.avm_readdatavalid (avm_readdatavalid), //input
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.avm_readdata (avm_readdata), //input [31:0]
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//-------------------------------------------------------------------------- Altera Avalon io bus
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.avalon_io_address (avalon_io_address), //output [15:0]
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.avalon_io_byteenable (avalon_io_byteenable), //output [3:0]
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.avalon_io_read (avalon_io_read), //output
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.avalon_io_readdatavalid (avalon_io_readdatavalid), //input
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.avalon_io_readdata (avalon_io_readdata), //input [31:0]
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.avalon_io_write (avalon_io_write), //output
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.avalon_io_writedata (avalon_io_writedata), //output [31:0]
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.avalon_io_waitrequest (avalon_io_waitrequest), //input
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//-------------------------------------------------------------------------- debug
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.SW (SW), //input [17:0]
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.tb_finish_instr (tb_finish_instr),
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.dbg_io_address (dbg_io_address),
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.dbg_io_byteenable (dbg_io_byteenable),
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.dbg_io_write (dbg_io_write),
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.dbg_io_read (dbg_io_read),
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.dbg_io_data (dbg_io_data),
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.dbg_int_vector (dbg_int_vector),
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.dbg_int (dbg_int),
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.dbg_exc_vector (dbg_exc_vector),
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.dbg_exc (dbg_exc),
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.dbg_mem_address (dbg_mem_address),
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.dbg_mem_byteenable (dbg_mem_byteenable),
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.dbg_mem_write (dbg_mem_write),
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.dbg_mem_read (dbg_mem_read),
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.dbg_mem_data (dbg_mem_data)
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);
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//------------------------------------------------------------------------------
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wire [1:0] ctrl_address = 2'd0;
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wire ctrl_write = 1'b0;
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wire [31:0] ctrl_writedata = 32'd0;
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pc_bus pc_bus_inst(
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.clk (clk), //input
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.rst_n (rst_n), //input
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//control slave
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.ctrl_address (ctrl_address), //input [1:0]
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.ctrl_write (ctrl_write), //input
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.ctrl_writedata (ctrl_writedata), //input [31:0]
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//memory slave
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.mem_address (mem_address), //input [29:0]
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.mem_byteenable (mem_byteenable), //input [3:0]
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.mem_read (mem_read), //input
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.mem_readdata (mem_readdata), //output [31:0]
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.mem_write (mem_write), //input
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.mem_writedata (mem_writedata), //input [31:0]
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.mem_waitrequest (mem_waitrequest), //output
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.mem_readdatavalid (mem_readdatavalid), //output
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.mem_burstcount (mem_burstcount), //input [2:0]
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//memory master
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.sdram_address (sdram_address), //output [31:0]
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.sdram_byteenable (sdram_byteenable), //output [3:0]
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.sdram_read (sdram_read), //output
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.sdram_readdata (sdram_readdata), //input [31:0]
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.sdram_write (sdram_write), //output
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.sdram_writedata (sdram_writedata), //output [31:0]
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.sdram_waitrequest (sdram_waitrequest), //input
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.sdram_readdatavalid(sdram_readdatavalid), //input
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.sdram_burstcount (sdram_burstcount), //output [2:0]
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//vga master
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.vga_address (vga_address), //output [31:0]
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.vga_byteenable (vga_byteenable), //output [3:0]
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.vga_read (vga_read), //output
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.vga_readdata (vga_readdata), //input [31:0]
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.vga_write (vga_write), //output
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.vga_writedata (vga_writedata), //output [31:0]
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.vga_waitrequest (vga_waitrequest), //input
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.vga_readdatavalid (vga_readdatavalid), //input
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.vga_burstcount (vga_burstcount) //output [2:0]
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);
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//------------------------------------------------------------------------------
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wire _unused_ok = &{ 1'b0, avm_address[1:0], 1'b0 };
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//------------------------------------------------------------------------------
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endmodule
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