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alfik |
#include <cstdio>
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#include <cstdlib>
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#include <dlfcn.h>
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#include <sys/mman.h>
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#include <sys/types.h>
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#include <sys/stat.h>
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#include <fcntl.h>
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#include <unistd.h>
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#include "Vhdd.h"
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#include "verilated.h"
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#include "verilated_vcd_c.h"
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#include "shared_mem.h"
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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volatile shared_mem_t *shared_ptr = NULL;
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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uint32 hd_cylinders = 1024;
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uint32 hd_heads = 16;
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uint32 hd_spt = 63;
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uint32 hd_total_sectors = hd_cylinders * hd_heads * hd_spt;
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unsigned int identify[256] = {
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0x0040, //word 0
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(hd_cylinders > 16383)? 16383 : hd_cylinders, //word 1
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0x0000, //word 2 reserved
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hd_heads, //word 3
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(unsigned short)(512 * hd_spt), //word 4
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512, //word 5
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hd_spt, //word 6
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0x0000, //word 7 vendor specific
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0x0000, //word 8 vendor specific
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0x0000, //word 9 vendor specific
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('B' << 8) | 'X', //word 10
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('H' << 8) | 'D', //word 11
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('0' << 8) | '0', //word 12
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('0' << 8) | '1', //word 13
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('1' << 8) | ' ', //word 14
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(' ' << 8) | ' ', //word 15
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(' ' << 8) | ' ', //word 16
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(' ' << 8) | ' ', //word 17
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(' ' << 8) | ' ', //word 18
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(' ' << 8) | ' ', //word 19
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3, //word 20 buffer type
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512, //word 21 cache size
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4, //word 22 number of ecc bytes
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0,0,0,0, //words 23..26 firmware revision
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('H' << 8) | 'D', //words 27..46 model number
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('m' << 8) | 'o',
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('d' << 8) | 'e',
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('l' << 8) | ' ',
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(' ' << 8) | ' ',
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(' ' << 8) | ' ',
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(' ' << 8) | ' ',
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(' ' << 8) | ' ',
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(' ' << 8) | ' ',
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(' ' << 8) | ' ',
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(' ' << 8) | ' ',
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(' ' << 8) | ' ',
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(' ' << 8) | ' ',
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(' ' << 8) | ' ',
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(' ' << 8) | ' ',
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(' ' << 8) | ' ',
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(' ' << 8) | ' ',
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(' ' << 8) | ' ',
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(' ' << 8) | ' ',
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(' ' << 8) | ' ',
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16, //word 47 max multiple sectors
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1, //word 48 dword io
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1<<9, //word 49 lba supported
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0x0000, //word 50 reserved
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0x0200, //word 51 pio timing
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0x0200, //word 52 pio timing
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0x0007, //word 53 valid fields
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(hd_cylinders > 16383)? 16383 : hd_cylinders, //word 54
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hd_heads, //word 55
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hd_spt, //word 56
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hd_total_sectors & 0xFFFF, //word 57
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hd_total_sectors >> 16, //word 58
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0x0000, //word 59 multiple sectors
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hd_total_sectors & 0xFFFF, //word 60
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hd_total_sectors >> 16, //word 61
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0x0000, //word 62 single word dma modes
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0x0000, //word 63 multiple word dma modes
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0x0000, //word 64 pio modes
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120,120,120,120, //word 65..68
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0,0,0,0,0,0,0,0,0,0,0, //word 69..79
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0x007E, //word 80 ata modes
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0x0000, //word 81 minor version number
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1<<14, //word 82 supported commands
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(1<<14) | (1<<13) | (1<<12) | (1<<10), //word 83
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1<<14, //word 84
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1<<14, //word 85
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(1<<14) | (1<<13) | (1<<12) | (1<<10), //word 86
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1<<14, //word 87
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0x0000, //word 88
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0,0,0,0, //word 89..92
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1 | (1<<14) | 0x2000, //word 93
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0,0,0,0,0,0, //word 94..99
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hd_total_sectors & 0xFFFF, //word 100
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hd_total_sectors >> 16, //word 101
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0, //word 102
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0, //word 103
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0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,//word 104..127
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0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, //word 128..255
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0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
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};
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//------------------------------------------------------------------------------
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uint32 sd_address;
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uint32 sd_sector_count;
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uint32 sd_command;
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bool sd_mutex = false;
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uint32 sd_waiting = 0;
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int main(int argc, char **argv) {
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//map shared memory
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int fd = open("./../../../sim_pc/shared_mem.dat", O_RDWR, S_IRUSR | S_IWUSR);
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if(fd == -1) {
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perror("open() failed for shared_mem.dat");
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return -1;
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}
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shared_ptr = (shared_mem_t *)mmap(NULL, sizeof(shared_mem_t), PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
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if(shared_ptr == MAP_FAILED) {
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perror("mmap() failed");
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close(fd);
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return -2;
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}
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Verilated::commandArgs(argc, argv);
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Verilated::traceEverOn(true);
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VerilatedVcdC* tracer = new VerilatedVcdC;
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Vhdd *top = new Vhdd();
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top->trace (tracer, 99);
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//tracer->rolloverMB(1000000);
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tracer->open("hdd.vcd");
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bool dump = false;
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//reset
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top->clk = 0; top->rst_n = 1; top->eval();
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top->clk = 1; top->rst_n = 1; top->eval();
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top->clk = 1; top->rst_n = 0; top->eval();
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top->clk = 0; top->rst_n = 0; top->eval();
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top->clk = 0; top->rst_n = 1; top->eval();
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uint64 cycle = 0;
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bool read_cycle = false;
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/*
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0x00.[31:0]: identify write
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0x01.[16:0]: media cylinders
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0x02.[4:0]: media heads
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0x03.[8:0]: media spt
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0x04.[13:0]: media sectors per cylinder = spt * heads
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0x05.[31:0]: media sectors total
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0x06.[31:0]: media sd base
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*/
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for(uint32 i=0; i<128; i++) {
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top->mgmt_address = 0;
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top->mgmt_write = 1;
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top->mgmt_writedata = ((unsigned int)identify[2*i+1] << 16) | (unsigned int)identify[2*i+0];
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top->clk = 0;
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top->eval();
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if(dump) tracer->dump(cycle++);
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top->clk = 1;
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top->eval();
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if(dump) tracer->dump(cycle++);
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tracer->flush();
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}
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for(uint32 i=0; i<6; i++) {
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top->mgmt_address = i+1;
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top->mgmt_write = 1;
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top->mgmt_writedata = (i==0)? hd_cylinders : (i==1)? hd_heads : (i==2)? hd_spt : (i==3)? hd_heads * hd_spt : (i==4)? hd_total_sectors : 0;
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top->clk = 0;
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top->eval();
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if(dump) tracer->dump(cycle++);
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| 211 |
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top->clk = 1;
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top->eval();
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if(dump) tracer->dump(cycle++);
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| 215 |
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tracer->flush();
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}
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top->mgmt_write = 0;
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| 219 |
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printf("hdd main_plugin.cpp\n");
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while(!Verilated::gotFinish()) {
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//----------------------------------------------------------------------
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/*
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uint32 combined.io_address;
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uint32 combined.io_data;
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uint32 combined.io_byteenable;
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uint32 combined.io_is_write;
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step_t combined.io_step;
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//avalon slave
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input io_address,
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input [3:0] io_byteenable,
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input io_read,
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output reg [31:0] io_readdata,
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input io_write,
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input [31:0] io_writedata,
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//ide shared port 0x3F6
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input ide_3f6_read,
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output reg [7:0] ide_3f6_readdata,
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input ide_3f6_write,
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input [7:0] ide_3f6_writedata,
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*/
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top->io_read = 0;
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top->io_write = 0;
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| 248 |
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| 249 |
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top->ide_3f6_read = 0;
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| 250 |
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top->ide_3f6_write= 0;
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| 251 |
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if(shared_ptr->combined.io_step == STEP_REQ && shared_ptr->combined.io_is_write && (shared_ptr->combined.io_address == 0x01F0 || shared_ptr->combined.io_address == 0x01F4)) {
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top->io_address = (shared_ptr->combined.io_address == 0x01F0)? 0 : 1;
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| 254 |
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top->io_byteenable = shared_ptr->combined.io_byteenable;
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top->io_writedata = shared_ptr->combined.io_data;
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| 257 |
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top->io_read = 0;
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top->io_write = 1;
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| 259 |
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| 260 |
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shared_ptr->combined.io_step = STEP_ACK;
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| 261 |
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}
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| 262 |
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| 263 |
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if(shared_ptr->combined.io_step == STEP_REQ && shared_ptr->combined.io_is_write && shared_ptr->combined.io_address == 0x03F4 && shared_ptr->combined.io_byteenable == 0x4) {
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top->ide_3f6_writedata = (shared_ptr->combined.io_data >> 16) & 0xFF;
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| 265 |
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| 266 |
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top->ide_3f6_read = 0;
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| 267 |
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top->ide_3f6_write= 1;
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| 268 |
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| 269 |
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shared_ptr->combined.io_step = STEP_ACK;
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| 270 |
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}
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| 271 |
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| 272 |
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if(read_cycle == false) {
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| 273 |
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if(shared_ptr->combined.io_step == STEP_REQ && shared_ptr->combined.io_is_write == 0 && (shared_ptr->combined.io_address == 0x01F0 || shared_ptr->combined.io_address == 0x01F4)) {
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| 274 |
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top->io_address = (shared_ptr->combined.io_address == 0x01F0)? 0 : 1;
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| 275 |
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top->io_byteenable = shared_ptr->combined.io_byteenable;
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| 276 |
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top->io_writedata = 0;
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| 277 |
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| 278 |
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top->io_read = 1;
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| 279 |
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top->io_write = 0;
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| 280 |
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| 281 |
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read_cycle = true;
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| 282 |
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}
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| 283 |
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| 284 |
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if(shared_ptr->combined.io_step == STEP_REQ && shared_ptr->combined.io_is_write == 0 && shared_ptr->combined.io_address == 0x03F4 && shared_ptr->combined.io_byteenable == 0x4) {
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| 285 |
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top->ide_3f6_writedata = 0;
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| 286 |
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| 287 |
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top->ide_3f6_read = 1;
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| 288 |
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top->ide_3f6_write= 0;
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| 289 |
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| 290 |
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read_cycle = true;
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| 291 |
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}
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| 292 |
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}
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| 293 |
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else {
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| 294 |
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if(shared_ptr->combined.io_step == STEP_REQ && shared_ptr->combined.io_is_write == 0 && (shared_ptr->combined.io_address == 0x01F0 || shared_ptr->combined.io_address == 0x01F4)) {
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| 295 |
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uint32 val = top->io_readdata;
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| 296 |
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| 297 |
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if((shared_ptr->combined.io_byteenable & 1) == 0) val &= 0xFFFFFF00;
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| 298 |
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if((shared_ptr->combined.io_byteenable & 2) == 0) val &= 0xFFFF00FF;
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| 299 |
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if((shared_ptr->combined.io_byteenable & 4) == 0) val &= 0xFF00FFFF;
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| 300 |
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if((shared_ptr->combined.io_byteenable & 8) == 0) val &= 0x00FFFFFF;
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| 301 |
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| 302 |
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shared_ptr->combined.io_data = val;
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| 303 |
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| 304 |
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read_cycle = false;
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| 305 |
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shared_ptr->combined.io_step = STEP_ACK;
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| 306 |
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}
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| 307 |
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| 308 |
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if(shared_ptr->combined.io_step == STEP_REQ && shared_ptr->combined.io_is_write == 0 && shared_ptr->combined.io_address == 0x03F4 && shared_ptr->combined.io_byteenable == 0x4) {
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| 309 |
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uint32 val = (top->ide_3f6_readdata & 0xFF) << 16;
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| 310 |
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| 311 |
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shared_ptr->combined.io_data = val;
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| 312 |
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| 313 |
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read_cycle = false;
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| 314 |
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shared_ptr->combined.io_step = STEP_ACK;
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| 315 |
|
|
}
|
| 316 |
|
|
}
|
| 317 |
|
|
|
| 318 |
|
|
//----------------------------------------------------------------------
|
| 319 |
|
|
|
| 320 |
|
|
if(top->irq) {
|
| 321 |
|
|
printf("ERROR: hdd irq set.\n");
|
| 322 |
|
|
exit(-1);
|
| 323 |
|
|
}
|
| 324 |
|
|
|
| 325 |
|
|
//----------------------------------------------------------------------
|
| 326 |
|
|
|
| 327 |
|
|
top->sd_master_waitrequest = 0;
|
| 328 |
|
|
top->sd_master_readdatavalid = 0;
|
| 329 |
|
|
|
| 330 |
|
|
if(top->sd_master_read) {
|
| 331 |
|
|
sd_mutex = true;
|
| 332 |
|
|
top->sd_master_readdata = 2;
|
| 333 |
|
|
}
|
| 334 |
|
|
else if(sd_mutex) {
|
| 335 |
|
|
top->sd_master_readdatavalid = 1;
|
| 336 |
|
|
sd_mutex = false;
|
| 337 |
|
|
}
|
| 338 |
|
|
|
| 339 |
|
|
if(top->sd_master_write) {
|
| 340 |
|
|
printf("sd_master %08x %08x\n", top->sd_master_address, top->sd_master_writedata);
|
| 341 |
|
|
|
| 342 |
|
|
if(top->sd_master_address == 0x00000004) sd_address = top->sd_master_writedata;
|
| 343 |
|
|
if(top->sd_master_address == 0x00000008) sd_sector_count = top->sd_master_writedata;
|
| 344 |
|
|
if(top->sd_master_address == 0x0000000C) sd_command = top->sd_master_writedata;
|
| 345 |
|
|
|
| 346 |
|
|
sd_waiting = 1000; //10000;
|
| 347 |
|
|
}
|
| 348 |
|
|
else if(sd_command != 0) {
|
| 349 |
|
|
|
| 350 |
|
|
if(sd_waiting > 0) {
|
| 351 |
|
|
sd_waiting--;
|
| 352 |
|
|
}
|
| 353 |
|
|
else if(sd_command == 2) { //read
|
| 354 |
|
|
|
| 355 |
|
|
FILE *fp = fopen("/home/alek/temp/bochs-run/hd_copy_for_sim.img", "rb");
|
| 356 |
|
|
|
| 357 |
|
|
//usleep(500*1000);
|
| 358 |
|
|
|
| 359 |
|
|
for(uint32 i=0; i<sd_sector_count*128; i++) {
|
| 360 |
|
|
|
| 361 |
|
|
fseek(fp, (sd_address*512)+(i*4), SEEK_SET);
|
| 362 |
|
|
|
| 363 |
|
|
uint32 val;
|
| 364 |
|
|
fread(&val, 4, 1, fp);
|
| 365 |
|
|
|
| 366 |
|
|
top->sd_slave_write = 1;
|
| 367 |
|
|
top->sd_slave_writedata = val;
|
| 368 |
|
|
|
| 369 |
|
|
top->clk = 0;
|
| 370 |
|
|
top->eval();
|
| 371 |
|
|
if(dump) tracer->dump(cycle++);
|
| 372 |
|
|
|
| 373 |
|
|
top->clk = 1;
|
| 374 |
|
|
top->eval();
|
| 375 |
|
|
if(dump) tracer->dump(cycle++);
|
| 376 |
|
|
|
| 377 |
|
|
tracer->flush();
|
| 378 |
|
|
}
|
| 379 |
|
|
|
| 380 |
|
|
top->sd_slave_write = 0;
|
| 381 |
|
|
sd_command = 0;
|
| 382 |
|
|
|
| 383 |
|
|
for(uint32 i=0; i<30; i++) {
|
| 384 |
|
|
top->clk = 0;
|
| 385 |
|
|
top->eval();
|
| 386 |
|
|
if(dump) tracer->dump(cycle++);
|
| 387 |
|
|
|
| 388 |
|
|
top->clk = 1;
|
| 389 |
|
|
top->eval();
|
| 390 |
|
|
if(dump) tracer->dump(cycle++);
|
| 391 |
|
|
|
| 392 |
|
|
tracer->flush();
|
| 393 |
|
|
}
|
| 394 |
|
|
|
| 395 |
|
|
fclose(fp);
|
| 396 |
|
|
}
|
| 397 |
|
|
else if(sd_command == 3) { //write
|
| 398 |
|
|
|
| 399 |
|
|
FILE *fp = fopen("/home/alek/temp/bochs-run/hd_copy_for_sim.img", "r+b");
|
| 400 |
|
|
|
| 401 |
|
|
//usleep(500*1000);
|
| 402 |
|
|
|
| 403 |
|
|
bool wait = false;
|
| 404 |
|
|
for(uint32 i=0; i<sd_sector_count*128*2; i++) {
|
| 405 |
|
|
|
| 406 |
|
|
top->sd_slave_read = (wait == false)? 1 : 0;
|
| 407 |
|
|
|
| 408 |
|
|
top->clk = 0;
|
| 409 |
|
|
top->eval();
|
| 410 |
|
|
if(dump) tracer->dump(cycle++);
|
| 411 |
|
|
|
| 412 |
|
|
top->clk = 1;
|
| 413 |
|
|
top->eval();
|
| 414 |
|
|
if(dump) tracer->dump(cycle++);
|
| 415 |
|
|
|
| 416 |
|
|
tracer->flush();
|
| 417 |
|
|
|
| 418 |
|
|
if(wait) {
|
| 419 |
|
|
wait = (wait == false)? true : false;
|
| 420 |
|
|
continue;
|
| 421 |
|
|
}
|
| 422 |
|
|
|
| 423 |
|
|
//--- write
|
| 424 |
|
|
|
| 425 |
|
|
fseek(fp, (sd_address*512)+(i*4/2), SEEK_SET);
|
| 426 |
|
|
|
| 427 |
|
|
uint32 val = top->sd_slave_readdata;
|
| 428 |
|
|
fwrite(&val, 4, 1, fp);
|
| 429 |
|
|
|
| 430 |
|
|
wait = (wait == false)? true : false;
|
| 431 |
|
|
}
|
| 432 |
|
|
|
| 433 |
|
|
top->sd_slave_read = 0;
|
| 434 |
|
|
sd_command = 0;
|
| 435 |
|
|
|
| 436 |
|
|
for(uint32 i=0; i<30; i++) {
|
| 437 |
|
|
top->clk = 0;
|
| 438 |
|
|
top->eval();
|
| 439 |
|
|
if(dump) tracer->dump(cycle++);
|
| 440 |
|
|
|
| 441 |
|
|
top->clk = 1;
|
| 442 |
|
|
top->eval();
|
| 443 |
|
|
if(dump) tracer->dump(cycle++);
|
| 444 |
|
|
|
| 445 |
|
|
tracer->flush();
|
| 446 |
|
|
}
|
| 447 |
|
|
|
| 448 |
|
|
fclose(fp);
|
| 449 |
|
|
}
|
| 450 |
|
|
}
|
| 451 |
|
|
|
| 452 |
|
|
//----------------------------------------------------------------------
|
| 453 |
|
|
|
| 454 |
|
|
top->clk = 0;
|
| 455 |
|
|
top->eval();
|
| 456 |
|
|
if(dump) tracer->dump(cycle++);
|
| 457 |
|
|
|
| 458 |
|
|
top->clk = 1;
|
| 459 |
|
|
top->eval();
|
| 460 |
|
|
if(dump) tracer->dump(cycle++);
|
| 461 |
|
|
|
| 462 |
|
|
tracer->flush();
|
| 463 |
|
|
|
| 464 |
|
|
usleep(10);
|
| 465 |
|
|
}
|
| 466 |
|
|
tracer->close();
|
| 467 |
|
|
delete tracer;
|
| 468 |
|
|
delete top;
|
| 469 |
|
|
|
| 470 |
|
|
return 0;
|
| 471 |
|
|
}
|
| 472 |
|
|
|
| 473 |
|
|
//------------------------------------------------------------------------------
|
| 474 |
|
|
|
| 475 |
|
|
/*
|
| 476 |
|
|
input clk,
|
| 477 |
|
|
input rst_n,
|
| 478 |
|
|
|
| 479 |
|
|
//irq
|
| 480 |
|
|
output reg irq,
|
| 481 |
|
|
|
| 482 |
|
|
//avalon slave
|
| 483 |
|
|
input io_address,
|
| 484 |
|
|
input [3:0] io_byteenable,
|
| 485 |
|
|
input io_read,
|
| 486 |
|
|
output reg [31:0] io_readdata,
|
| 487 |
|
|
input io_write,
|
| 488 |
|
|
input [31:0] io_writedata,
|
| 489 |
|
|
|
| 490 |
|
|
//ide shared port 0x3F6
|
| 491 |
|
|
input ide_3f6_read,
|
| 492 |
|
|
output reg [7:0] ide_3f6_readdata,
|
| 493 |
|
|
input ide_3f6_write,
|
| 494 |
|
|
input [7:0] ide_3f6_writedata,
|
| 495 |
|
|
|
| 496 |
|
|
//master to control sd
|
| 497 |
|
|
output [31:0] sd_master_address,
|
| 498 |
|
|
input sd_master_waitrequest,
|
| 499 |
|
|
output sd_master_read,
|
| 500 |
|
|
input sd_master_readdatavalid,
|
| 501 |
|
|
input [31:0] sd_master_readdata,
|
| 502 |
|
|
output sd_master_write,
|
| 503 |
|
|
output [31:0] sd_master_writedata,
|
| 504 |
|
|
|
| 505 |
|
|
//slave with data from/to sd
|
| 506 |
|
|
input [8:0] sd_slave_address,
|
| 507 |
|
|
input sd_slave_read,
|
| 508 |
|
|
output reg [31:0] sd_slave_readdata,
|
| 509 |
|
|
input sd_slave_write,
|
| 510 |
|
|
input [31:0] sd_slave_writedata,
|
| 511 |
|
|
|
| 512 |
|
|
//management slave
|
| 513 |
|
|
//0x00.[31:0]: identify write
|
| 514 |
|
|
//0x01.[16:0]: media cylinders
|
| 515 |
|
|
//0x02.[4:0]: media heads
|
| 516 |
|
|
//0x03.[8:0]: media spt
|
| 517 |
|
|
//0x04.[13:0]: media sectors per cylinder = spt * heads
|
| 518 |
|
|
//0x05.[31:0]: media sectors total
|
| 519 |
|
|
//0x06.[31:0]: media sd base
|
| 520 |
|
|
|
| 521 |
|
|
input [2:0] mgmt_address,
|
| 522 |
|
|
input mgmt_write,
|
| 523 |
|
|
input [31:0] mgmt_writedata
|
| 524 |
|
|
*/
|
