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[/] [ao486/] [trunk/] [sim/] [verilator/] [soc/] [pc_dma/] [main.cpp] - Blame information for rev 2

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#include <cstdio>
#include <cstdlib>
 
#include "Vpc_dma.h"
#include "verilated.h"
#include "verilated_vcd_c.h"
 
//------------------------------------------------------------------------------
 
typedef unsigned int uint32;
typedef unsigned char uint8;
 
//------------------------------------------------------------------------------
 
enum state_t {
    S_IDLE,
 
    S_IO_READ_1,
    S_IO_READ_2,
    S_IO_READ_3,
 
    S_IO_WRITE_1,
    S_IO_WRITE_2,
    S_IO_WRITE_3,
 
    S_DELAY
};
 
uint32  address_base;
uint32  address;
uint32  byteena;
uint32  value_base;
uint32  value;
state_t state = S_IDLE;
uint32  shifted;
uint32  shifted_read;
uint32  length;
uint32  value_read;
 
uint32  delay;
 
void check_byteena(uint32 byteena) {
    if(byteena == 0 || byteena == 5 || byteena == 9 || byteena == 10 || byteena == 11 || byteena == 13) {
        printf("ERROR: invalid byteena: %x\n", byteena);
        exit(-1);
    }
 
    value_read = 0;
    address_base = address;
    value_base = value;
    shifted_read = 0;
 
    shifted = 0;
    for(uint32 i=0; i<4; i++) {
        if(byteena & 1) break;
 
        shifted++;
        address++;
        byteena >>= 1;
        value >>= 8;
    }
 
    length = 0;
    for(uint32 i=0; i<4; i++) {
        if(byteena & 1) length++;
 
        byteena >>= 1;
    }
}
 
bool is_address_ok(uint32 address) {
//000h - 00Fh for slave DMA
//080h - 08Fh for DMA page
//0C0h - 0DFh for master DMA
    if(address >= 0x0000 && address <= 0x00F) return true;
    if(address >= 0x0080 && address <= 0x08F) return true;
    if(address >= 0x00C0 && address <= 0x0DF) return true;
 
    return false;
}
 
bool next_record() {
    static FILE *fp = NULL;
 
    if(fp == NULL) {
        fp = fopen("./../../../../backup/run-3/track.txt", "rb");
        if(fp == NULL) {
            printf("ERROR: can not open file.\n");
            exit(-1);
        }
    }
 
    do {
        char line[256];
        memset(line, 0, sizeof(line));
 
        char *res = fgets(line, sizeof(line), fp);
        if(res == NULL) {
            fclose(fp);
            fp = NULL;
            return false;
        }
 
//printf("line: %s\n", line);
 
        int count;
 
        count = sscanf(line, "io rd %x %x %x", &address, &byteena, &value);
        if(count == 3 && is_address_ok(address)) {
            check_byteena(byteena);
            state = S_IO_READ_1;
printf("line: %s", line);
            return true;
        }
        count = sscanf(line, "io wr %x %x %x", &address, &byteena, &value);
        if(count == 3 && is_address_ok(address)) {
            check_byteena(byteena);
            state = S_IO_WRITE_1;
printf("line: %s", line);
            return true;
        }
 
    } while(true);
 
    return false;
}
 
//------------------------------------------------------------------------------
 
int main(int argc, char **argv) {
    Verilated::commandArgs(argc, argv);
 
    Verilated::traceEverOn(true);
    VerilatedVcdC* tracer = new VerilatedVcdC;
 
    Vpc_dma *top = new Vpc_dma();
    top->trace (tracer, 99);
    //tracer->rolloverMB(1000000);
    tracer->open("pc_dma.vcd");
 
    bool dump = true;
 
    //reset
    top->clk = 0; top->rst_n = 1; top->eval();
    top->clk = 1; top->rst_n = 1; top->eval();
    top->clk = 1; top->rst_n = 0; top->eval();
    top->clk = 0; top->rst_n = 0; top->eval();
    top->clk = 0; top->rst_n = 1; top->eval();
 
    uint32 cycle = 0;
    while(!Verilated::gotFinish()) {
 
        //----------------------------------------------------------------------
 
        if(state == S_IDLE) {
            bool res = next_record();
            if(res == false) {
                printf("End of file.\n");
                break;
            }
        }
 
        //----------------------------------------------------------------------
 
        if(state == S_DELAY) {
            delay--;
 
            if(delay == 0) {
                state = S_IDLE;
            }
        }
        else if(state == S_IO_READ_1) {
            if(address >= 0x0000 && address <= 0x000F) {
                top->slave_address = address & 0xF;
                top->slave_read = 1;
            }
            else if(address >= 0x0080 && address <= 0x08F) {
                top->page_address = address & 0xF;
                top->page_read = 1;
            }
            else if(address >= 0x00C0 && address <= 0x00DF) {
                top->master_address = address & 0x1F;
                top->master_read = 1;
            }
            else {
                printf("ERROR: invalid io rd address: %08x\n", address);
                exit(-1);
            }
            state = S_IO_READ_2;
        }
        else if(state == S_IO_READ_2) {
            length--;
            shifted_read++;
 
            uint32 top_readdata = 0;
 
            if(address >= 0x0000 && address <= 0x000F)      top_readdata = top->slave_readdata & 0xFF;
            else if(address >= 0x0080 && address <= 0x008F) top_readdata = top->page_readdata & 0xFF;
            else if(address >= 0x00C0 && address <= 0x00DF) top_readdata = top->master_readdata & 0xFF;
 
            if(length > 0) {
                address++;
 
                if(address >= 0x0000 && address <= 0x000F)      top->slave_address  = address & 0xF;
                else if(address >= 0x0080 && address <= 0x008F) top->page_address   = address & 0xF;
                else if(address >= 0x00C0 && address <= 0x00DF) top->master_address = address & 0x1F;
                else {
                    printf("ERROR: invalid io rd address: %08x\n", address);
                    exit(-1);
                }
 
                value_read |= (top_readdata & 0xFF) << 24;
                value_read >>= 8;
 
                top->slave_read = 0;
                top->page_read = 0;
                top->master_read = 0;
                state = S_IO_READ_3;
            }
            else {
                top->slave_read = 0;
                top->page_read = 0;
                top->master_read = 0;
 
                value_read |= (top_readdata & 0xFF) << 24;
                value_read >>= 8*(4 - shifted_read - shifted);
 
                if(value_read != value_base) {
                    printf("mismatch io rd %08x %x %08x != %08x\n", address_base, byteena, value_base, value_read);
 
//if(! ((address_base ==  && byteena == )))
exit(0);
                }
 
                delay = 5;
                state = S_DELAY;
            }
        }
        else if(state == S_IO_READ_3) {
            if(address >= 0x0000 && address <= 0x000F)      top->slave_read = 1;
            else if(address >= 0x0080 && address <= 0x008F) top->page_read = 1;
            else if(address >= 0x00C0 && address <= 0x00DF) top->master_read = 1;
 
            state = S_IO_READ_2;
        }
        else if(state == S_IO_WRITE_1) {
            if(address >= 0x0000 && address <= 0x000F) {
                top->slave_address = address & 0xF;
                top->slave_write = 1;
                top->slave_writedata = value & 0xFF;
            }
            else if(address >= 0x0080 && address <= 0x008F) {
                top->page_address = address & 0xF;
                top->page_write = 1;
                top->page_writedata = value & 0xFF;
            }
            else if(address >= 0x00C0 && address <= 0x00DF) {
                top->master_address = address & 0x1F;
                top->master_write = 1;
                top->master_writedata = value & 0xFF;
            }
            else {
                printf("ERROR: invalid io wr address: %08x\n", address);
                exit(-1);
            }
            state = S_IO_WRITE_2;
        }
        else if(state == S_IO_WRITE_2) {
            length--;
 
            if(length > 0) {
                address++;
                value >>= 8;
 
                if(address >= 0x0000 && address <= 0x000F) {
                    top->slave_address = address & 0xF;
                    top->slave_writedata = value & 0xFF;
                }
                else if(address >= 0x0080 && address <= 0x008F) {
                    top->page_address = address & 0xF;
                    top->page_writedata = value & 0xFF;
                }
                else if(address >= 0x00C0 && address <= 0x00DF) {
                    top->master_address = address & 0x1F;
                    top->master_writedata = value & 0xFF;
                }
                else {
                    printf("ERROR: invalid io wr address: %08x\n", address);
                    exit(-1);
                }
 
                top->slave_write = 0;
                top->page_write = 0;
                top->master_write = 0;
                state = S_IO_WRITE_3;
            }
            else {
                top->slave_write = 0;
                top->page_write = 0;
                top->master_write = 0;
 
                delay = 5;
                state = S_DELAY;
            }
        }
        else if(state == S_IO_WRITE_3) {
            if(address >= 0x0000 && address <= 0x000F)      top->slave_write = 1;
            else if(address >= 0x0080 && address <= 0x008F) top->page_write = 1;
            else if(address >= 0x00C0 && address <= 0x00DF) top->master_write = 1;
 
            state = S_IO_WRITE_2;
        }
 
        //----------------------------------------------------------------------
 
        top->clk = 0;
        top->eval();
        if(dump) tracer->dump(cycle++);
 
        top->clk = 1;
        top->eval();
        if(dump) tracer->dump(cycle++);
 
        tracer->flush();
 
        if(top->avm_read || top->avm_write) {
            printf("ERROR: dma activated !\n");
            exit(-1);
        }
    }
    tracer->close();
    delete tracer;
    delete top;
 
    return 0;
}
 
//------------------------------------------------------------------------------
 
/*
    input               clk,
    input               rst_n,
 
    //000h - 00Fh for slave DMA
    input       [3:0]   slave_address,
    input               slave_read,
    output reg  [7:0]   slave_readdata,
    input               slave_write,
    input       [7:0]   slave_writedata,
 
    //080h - 08Fh for DMA page
    input       [3:0]   page_address,
    input               page_read,
    output reg  [7:0]   page_readdata,
    input               page_write,
    input       [7:0]   page_writedata,
 
    //0C0h - 0DFh for master DMA
    input       [4:0]   master_address,
    input               master_read,
    output reg  [7:0]   master_readdata,
    input               master_write,
    input       [7:0]   master_writedata,
 
    //master
    output reg  [31:0]  avm_address,
    input               avm_waitrequest,
    output reg          avm_read,
    input               avm_readdatavalid,
    input       [7:0]   avm_readdata,
    output reg          avm_write,
    output reg  [7:0]   avm_writedata,
 
    //floppy 8-bit dma channel
    input               dma_floppy_req,
    output reg          dma_floppy_ack,
    output reg          dma_floppy_terminal,
    output reg  [7:0]   dma_floppy_readdata,
    input       [7:0]   dma_floppy_writedata,
 
    //soundblaster 8-bit dma channel
    input               dma_soundblaster_req,
    output reg          dma_soundblaster_ack,
    output reg          dma_soundblaster_terminal,
    output reg  [7:0]   dma_soundblaster_readdata,
    input       [7:0]   dma_soundblaster_writedata
*/

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Subversion Repositories ao486

[/] [ao486/] [trunk/] [sim/] [verilator/] [soc/] [pc_dma/] [main.cpp] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	alfik	`#include <cstdio>`
2			`#include <cstdlib>`
3
4			`#include "Vpc_dma.h"`
5			`#include "verilated.h"`
6			`#include "verilated_vcd_c.h"`
7
8			`//------------------------------------------------------------------------------`
9
10			`typedef unsigned int uint32;`
11			`typedef unsigned char uint8;`
12
13			`//------------------------------------------------------------------------------`
14
15			`enum state_t {`
16			`S_IDLE,`
17
18			`S_IO_READ_1,`
19			`S_IO_READ_2,`
20			`S_IO_READ_3,`
21
22			`S_IO_WRITE_1,`
23			`S_IO_WRITE_2,`
24			`S_IO_WRITE_3,`
25
26			`S_DELAY`
27			`};`
28
29			`uint32 address_base;`
30			`uint32 address;`
31			`uint32 byteena;`
32			`uint32 value_base;`
33			`uint32 value;`
34			`state_t state = S_IDLE;`
35			`uint32 shifted;`
36			`uint32 shifted_read;`
37			`uint32 length;`
38			`uint32 value_read;`
39
40			`uint32 delay;`
41
42			`void check_byteena(uint32 byteena) {`
43			`if(byteena == 0 \|\| byteena == 5 \|\| byteena == 9 \|\| byteena == 10 \|\| byteena == 11 \|\| byteena == 13) {`
44			`printf("ERROR: invalid byteena: %x\n", byteena);`
45			`exit(-1);`
46			`}`
47
48			`value_read = 0;`
49			`address_base = address;`
50			`value_base = value;`
51			`shifted_read = 0;`
52
53			`shifted = 0;`
54			`for(uint32 i=0; i<4; i++) {`
55			`if(byteena & 1) break;`
56
57			`shifted++;`
58			`address++;`
59			`byteena >>= 1;`
60			`value >>= 8;`
61			`}`
62
63			`length = 0;`
64			`for(uint32 i=0; i<4; i++) {`
65			`if(byteena & 1) length++;`
66
67			`byteena >>= 1;`
68			`}`
69			`}`
70
71			`bool is_address_ok(uint32 address) {`
72			`//000h - 00Fh for slave DMA`
73			`//080h - 08Fh for DMA page`
74			`//0C0h - 0DFh for master DMA`
75			`if(address >= 0x0000 && address <= 0x00F) return true;`
76			`if(address >= 0x0080 && address <= 0x08F) return true;`
77			`if(address >= 0x00C0 && address <= 0x0DF) return true;`
78
79			`return false;`
80			`}`
81
82			`bool next_record() {`
83			`static FILE *fp = NULL;`
84
85			`if(fp == NULL) {`
86			`fp = fopen("./../../../../backup/run-3/track.txt", "rb");`
87			`if(fp == NULL) {`
88			`printf("ERROR: can not open file.\n");`
89			`exit(-1);`
90			`}`
91			`}`
92
93			`do {`
94			`char line[256];`
95			`memset(line, 0, sizeof(line));`
96
97			`char *res = fgets(line, sizeof(line), fp);`
98			`if(res == NULL) {`
99			`fclose(fp);`
100			`fp = NULL;`
101			`return false;`
102			`}`
103
104			`//printf("line: %s\n", line);`
105
106			`int count;`
107
108			`count = sscanf(line, "io rd %x %x %x", &address, &byteena, &value);`
109			`if(count == 3 && is_address_ok(address)) {`
110			`check_byteena(byteena);`
111			`state = S_IO_READ_1;`
112			`printf("line: %s", line);`
113			`return true;`
114			`}`
115			`count = sscanf(line, "io wr %x %x %x", &address, &byteena, &value);`
116			`if(count == 3 && is_address_ok(address)) {`
117			`check_byteena(byteena);`
118			`state = S_IO_WRITE_1;`
119			`printf("line: %s", line);`
120			`return true;`
121			`}`
122
123			`} while(true);`
124
125			`return false;`
126			`}`
127
128			`//------------------------------------------------------------------------------`
129
130			`int main(int argc, char **argv) {`
131			`Verilated::commandArgs(argc, argv);`
132
133			`Verilated::traceEverOn(true);`
134			`VerilatedVcdC* tracer = new VerilatedVcdC;`
135
136			`Vpc_dma *top = new Vpc_dma();`
137			`top->trace (tracer, 99);`
138			`//tracer->rolloverMB(1000000);`
139			`tracer->open("pc_dma.vcd");`
140
141			`bool dump = true;`
142
143			`//reset`
144			`top->clk = 0; top->rst_n = 1; top->eval();`
145			`top->clk = 1; top->rst_n = 1; top->eval();`
146			`top->clk = 1; top->rst_n = 0; top->eval();`
147			`top->clk = 0; top->rst_n = 0; top->eval();`
148			`top->clk = 0; top->rst_n = 1; top->eval();`
149
150			`uint32 cycle = 0;`
151			`while(!Verilated::gotFinish()) {`
152
153			`//----------------------------------------------------------------------`
154
155			`if(state == S_IDLE) {`
156			`bool res = next_record();`
157			`if(res == false) {`
158			`printf("End of file.\n");`
159			`break;`
160			`}`
161			`}`
162
163			`//----------------------------------------------------------------------`
164
165			`if(state == S_DELAY) {`
166			`delay--;`
167
168			`if(delay == 0) {`
169			`state = S_IDLE;`
170			`}`
171			`}`
172			`else if(state == S_IO_READ_1) {`
173			`if(address >= 0x0000 && address <= 0x000F) {`
174			`top->slave_address = address & 0xF;`
175			`top->slave_read = 1;`
176			`}`
177			`else if(address >= 0x0080 && address <= 0x08F) {`
178			`top->page_address = address & 0xF;`
179			`top->page_read = 1;`
180			`}`
181			`else if(address >= 0x00C0 && address <= 0x00DF) {`
182			`top->master_address = address & 0x1F;`
183			`top->master_read = 1;`
184			`}`
185			`else {`
186			`printf("ERROR: invalid io rd address: %08x\n", address);`
187			`exit(-1);`
188			`}`
189			`state = S_IO_READ_2;`
190			`}`
191			`else if(state == S_IO_READ_2) {`
192			`length--;`
193			`shifted_read++;`
194
195			`uint32 top_readdata = 0;`
196
197			`if(address >= 0x0000 && address <= 0x000F) top_readdata = top->slave_readdata & 0xFF;`
198			`else if(address >= 0x0080 && address <= 0x008F) top_readdata = top->page_readdata & 0xFF;`
199			`else if(address >= 0x00C0 && address <= 0x00DF) top_readdata = top->master_readdata & 0xFF;`
200
201			`if(length > 0) {`
202			`address++;`
203
204			`if(address >= 0x0000 && address <= 0x000F) top->slave_address = address & 0xF;`
205			`else if(address >= 0x0080 && address <= 0x008F) top->page_address = address & 0xF;`
206			`else if(address >= 0x00C0 && address <= 0x00DF) top->master_address = address & 0x1F;`
207			`else {`
208			`printf("ERROR: invalid io rd address: %08x\n", address);`
209			`exit(-1);`
210			`}`
211
212			`value_read \|= (top_readdata & 0xFF) << 24;`
213			`value_read >>= 8;`
214
215			`top->slave_read = 0;`
216			`top->page_read = 0;`
217			`top->master_read = 0;`
218			`state = S_IO_READ_3;`
219			`}`
220			`else {`
221			`top->slave_read = 0;`
222			`top->page_read = 0;`
223			`top->master_read = 0;`
224
225			`value_read \|= (top_readdata & 0xFF) << 24;`
226			`value_read >>= 8*(4 - shifted_read - shifted);`
227
228			`if(value_read != value_base) {`
229			`printf("mismatch io rd %08x %x %08x != %08x\n", address_base, byteena, value_base, value_read);`
230
231			`//if(! ((address_base == && byteena == )))`
232			`exit(0);`
233			`}`
234
235			`delay = 5;`
236			`state = S_DELAY;`
237			`}`
238			`}`
239			`else if(state == S_IO_READ_3) {`
240			`if(address >= 0x0000 && address <= 0x000F) top->slave_read = 1;`
241			`else if(address >= 0x0080 && address <= 0x008F) top->page_read = 1;`
242			`else if(address >= 0x00C0 && address <= 0x00DF) top->master_read = 1;`
243
244			`state = S_IO_READ_2;`
245			`}`
246			`else if(state == S_IO_WRITE_1) {`
247			`if(address >= 0x0000 && address <= 0x000F) {`
248			`top->slave_address = address & 0xF;`
249			`top->slave_write = 1;`
250			`top->slave_writedata = value & 0xFF;`
251			`}`
252			`else if(address >= 0x0080 && address <= 0x008F) {`
253			`top->page_address = address & 0xF;`
254			`top->page_write = 1;`
255			`top->page_writedata = value & 0xFF;`
256			`}`
257			`else if(address >= 0x00C0 && address <= 0x00DF) {`
258			`top->master_address = address & 0x1F;`
259			`top->master_write = 1;`
260			`top->master_writedata = value & 0xFF;`
261			`}`
262			`else {`
263			`printf("ERROR: invalid io wr address: %08x\n", address);`
264			`exit(-1);`
265			`}`
266			`state = S_IO_WRITE_2;`
267			`}`
268			`else if(state == S_IO_WRITE_2) {`
269			`length--;`
270
271			`if(length > 0) {`
272			`address++;`
273			`value >>= 8;`
274
275			`if(address >= 0x0000 && address <= 0x000F) {`
276			`top->slave_address = address & 0xF;`
277			`top->slave_writedata = value & 0xFF;`
278			`}`
279			`else if(address >= 0x0080 && address <= 0x008F) {`
280			`top->page_address = address & 0xF;`
281			`top->page_writedata = value & 0xFF;`
282			`}`
283			`else if(address >= 0x00C0 && address <= 0x00DF) {`
284			`top->master_address = address & 0x1F;`
285			`top->master_writedata = value & 0xFF;`
286			`}`
287			`else {`
288			`printf("ERROR: invalid io wr address: %08x\n", address);`
289			`exit(-1);`
290			`}`
291
292			`top->slave_write = 0;`
293			`top->page_write = 0;`
294			`top->master_write = 0;`
295			`state = S_IO_WRITE_3;`
296			`}`
297			`else {`
298			`top->slave_write = 0;`
299			`top->page_write = 0;`
300			`top->master_write = 0;`
301
302			`delay = 5;`
303			`state = S_DELAY;`
304			`}`
305			`}`
306			`else if(state == S_IO_WRITE_3) {`
307			`if(address >= 0x0000 && address <= 0x000F) top->slave_write = 1;`
308			`else if(address >= 0x0080 && address <= 0x008F) top->page_write = 1;`
309			`else if(address >= 0x00C0 && address <= 0x00DF) top->master_write = 1;`
310
311			`state = S_IO_WRITE_2;`
312			`}`
313
314			`//----------------------------------------------------------------------`
315
316			`top->clk = 0;`
317			`top->eval();`
318			`if(dump) tracer->dump(cycle++);`
319
320			`top->clk = 1;`
321			`top->eval();`
322			`if(dump) tracer->dump(cycle++);`
323
324			`tracer->flush();`
325
326			`if(top->avm_read \|\| top->avm_write) {`
327			`printf("ERROR: dma activated !\n");`
328			`exit(-1);`
329			`}`
330			`}`
331			`tracer->close();`
332			`delete tracer;`
333			`delete top;`
334
335			`return 0;`
336			`}`
337
338			`//------------------------------------------------------------------------------`
339
340			`/*`
341			`input clk,`
342			`input rst_n,`
343
344			`//000h - 00Fh for slave DMA`
345			`input [3:0] slave_address,`
346			`input slave_read,`
347			`output reg [7:0] slave_readdata,`
348			`input slave_write,`
349			`input [7:0] slave_writedata,`
350
351			`//080h - 08Fh for DMA page`
352			`input [3:0] page_address,`
353			`input page_read,`
354			`output reg [7:0] page_readdata,`
355			`input page_write,`
356			`input [7:0] page_writedata,`
357
358			`//0C0h - 0DFh for master DMA`
359			`input [4:0] master_address,`
360			`input master_read,`
361			`output reg [7:0] master_readdata,`
362			`input master_write,`
363			`input [7:0] master_writedata,`
364
365			`//master`
366			`output reg [31:0] avm_address,`
367			`input avm_waitrequest,`
368			`output reg avm_read,`
369			`input avm_readdatavalid,`
370			`input [7:0] avm_readdata,`
371			`output reg avm_write,`
372			`output reg [7:0] avm_writedata,`
373
374			`//floppy 8-bit dma channel`
375			`input dma_floppy_req,`
376			`output reg dma_floppy_ack,`
377			`output reg dma_floppy_terminal,`
378			`output reg [7:0] dma_floppy_readdata,`
379			`input [7:0] dma_floppy_writedata,`
380
381			`//soundblaster 8-bit dma channel`
382			`input dma_soundblaster_req,`
383			`output reg dma_soundblaster_ack,`
384			`output reg dma_soundblaster_terminal,`
385			`output reg [7:0] dma_soundblaster_readdata,`
386			`input [7:0] dma_soundblaster_writedata`
387			`*/`