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[/] [ao486/] [trunk/] [sim/] [verilator/] [soc/] [pit/] [main.cpp] - Blame information for rev 2

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#include <cstdio>
#include <cstdlib>
 
#include "Vpit.h"
#include "verilated.h"
#include "verilated_vcd_c.h"
 
//------------------------------------------------------------------------------
 
typedef unsigned int uint32;
typedef unsigned char uint8;
 
//------------------------------------------------------------------------------
 
enum state_t {
    S_IDLE,
 
    S_IO_READ_1,
    S_IO_READ_2,
    S_IO_READ_3,
 
    S_IO_WRITE_1,
    S_IO_WRITE_2,
    S_IO_WRITE_3,
 
    S_DELAY
};
 
uint32  address_base;
uint32  address;
uint32  byteena;
uint32  value_base;
uint32  value;
state_t state = S_IDLE;
uint32  shifted;
uint32  shifted_read;
uint32  length;
uint32  value_read;
 
uint32  delay;
 
uint32  irq = 0;
 
void check_byteena(uint32 byteena) {
    if(byteena == 0 || byteena == 5 || byteena == 9 || byteena == 10 || byteena == 11 || byteena == 13) {
        printf("ERROR: invalid byteena: %x\n", byteena);
        exit(-1);
    }
 
    value_read = 0;
    address_base = address;
    value_base = value;
    shifted_read = 0;
 
    shifted = 0;
    for(uint32 i=0; i<4; i++) {
        if(byteena & 1) break;
 
        shifted++;
        address++;
        byteena >>= 1;
        value >>= 8;
    }
 
    length = 0;
    for(uint32 i=0; i<4; i++) {
        if(byteena & 1) length++;
 
        byteena >>= 1;
    }
}
 
bool is_address_ok(uint32 address) {
    if(address >= 0x0040 && address <= 0x043) return true;
 
    if(address == 0x0060 && (byteena & 0x2) == 0x2) {
        printf("ERROR: 0x61 port not implemented.\n");
        exit(-1);
    }
 
    return false;
}
 
bool next_record() {
    static FILE *fp = NULL;
 
    if(fp == NULL) {
        fp = fopen("./../../../../backup/run-3/track.txt", "rb");
        if(fp == NULL) {
            printf("ERROR: can not open file.\n");
            exit(-1);
        }
    }
 
    do {
        char line[256];
        memset(line, 0, sizeof(line));
 
        char *res = fgets(line, sizeof(line), fp);
        if(res == NULL) {
            fclose(fp);
            fp = NULL;
            return false;
        }
 
//printf("line: %s\n", line);
 
        int count;
 
        count = sscanf(line, "io rd %x %x %x", &address, &byteena, &value);
        if(count == 3 && is_address_ok(address)) {
            check_byteena(byteena);
            state = S_IO_READ_1;
printf("line: %s", line);
            return true;
        }
        count = sscanf(line, "io wr %x %x %x", &address, &byteena, &value);
        if(count == 3 && is_address_ok(address)) {
            check_byteena(byteena);
            state = S_IO_WRITE_1;
printf("line: %s", line);
            return true;
        }
 
        uint32 irq_val = 0;
        count = sscanf(line, "raise_irq %d", &irq_val);
        if(count == 1 && irq_val == 0) {
            irq = 1;
 
printf("line: %s", line);
            delay = 5;
            state = S_DELAY;
            return true;
        }
 
        count = sscanf(line, "lower_irq %d", &irq_val);
        if(count == 1 && irq_val == 0) {
            irq = 0;
 
printf("line: %s", line);
            delay = 5;
            state = S_DELAY;
            return true;
 
        }
 
 
    } while(true);
 
    return false;
}
 
//------------------------------------------------------------------------------
 
int main(int argc, char **argv) {
    Verilated::commandArgs(argc, argv);
 
    Verilated::traceEverOn(true);
    VerilatedVcdC* tracer = new VerilatedVcdC;
 
    Vpit *top = new Vpit();
    top->trace (tracer, 99);
    //tracer->rolloverMB(1000000);
    tracer->open("pit.vcd");
 
    bool dump = true;
 
    //reset
    top->clk = 0; top->rst_n = 1; top->eval();
    top->clk = 1; top->rst_n = 1; top->eval();
    top->clk = 1; top->rst_n = 0; top->eval();
    top->clk = 0; top->rst_n = 0; top->eval();
    top->clk = 0; top->rst_n = 1; top->eval();
 
    uint32 cycle = 0;
    while(!Verilated::gotFinish()) {
 
        //----------------------------------------------------------------------
 
        if(state == S_IDLE) {
            bool res = next_record();
            if(res == false) {
                printf("End of file.\n");
                break;
            }
 
 
        }
 
        //----------------------------------------------------------------------
 
        if(state == S_DELAY) {
            delay--;
 
            if(delay == 0) {
                state = S_IDLE;
            }
        }
        else if(state == S_IO_READ_1) {
            if(address >= 0x0040 && address <= 0x0043) {
                top->io_address = address & 0x3;
                top->io_read = 1;
            }
            else {
                printf("ERROR: invalid io rd address: %08x\n", address);
                exit(-1);
            }
            state = S_IO_READ_2;
        }
        else if(state == S_IO_READ_2) {
            length--;
            shifted_read++;
 
            uint32 top_readdata = 0;
 
            if(address >= 0x0040 && address <= 0x0043)      top_readdata = top->io_readdata & 0xFF;
 
            if(length > 0) {
                address++;
 
                if(address >= 0x0040 && address <= 0x0043) top->io_address = address & 0x3;
                else {
                    printf("ERROR: invalid io rd address: %08x\n", address);
                    exit(-1);
                }
 
                value_read |= (top_readdata & 0xFF) << 24;
                value_read >>= 8;
 
                top->io_read = 0;
                state = S_IO_READ_3;
            }
            else {
                top->io_read = 0;
 
                value_read |= (top_readdata & 0xFF) << 24;
                value_read >>= 8*(4 - shifted_read - shifted);
 
                if(value_read != value_base) {
                    printf("mismatch io rd %08x %x %08x != %08x\n", address_base, byteena, value_base, value_read);
 
if(! ((address_base == 0x0040 && byteena == 1)))
exit(0);
                }
 
                delay = 5;
                state = S_DELAY;
            }
        }
        else if(state == S_IO_READ_3) {
            if(address >= 0x0040 && address <= 0x0043) top->io_read = 1;
 
            state = S_IO_READ_2;
        }
        else if(state == S_IO_WRITE_1) {
            if(address >= 0x0040 && address <= 0x0043) {
                top->io_address = address & 0x3;
                top->io_write = 1;
                top->io_writedata = value & 0xFF;
            }
            else {
                printf("ERROR: invalid io wr address: %08x\n", address);
                exit(-1);
            }
            state = S_IO_WRITE_2;
        }
        else if(state == S_IO_WRITE_2) {
            length--;
 
            if(length > 0) {
                address++;
                value >>= 8;
 
                if(address >= 0x0040 && address <= 0x0043) {
                    top->io_address = address & 0x3;
                    top->io_writedata = value & 0xFF;
                }
                else {
                    printf("ERROR: invalid io wr address: %08x\n", address);
                    exit(-1);
                }
 
                top->io_write = 0;
                state = S_IO_WRITE_3;
            }
            else {
                top->io_write = 0;
 
                delay = 5;
                state = S_DELAY;
            }
        }
        else if(state == S_IO_WRITE_3) {
            if(address >= 0x0040 && address <= 0x0043) top->io_write = 1;
 
            state = S_IO_WRITE_2;
        }
 
        //----------------------------------------------------------------------
 
        top->clk = 0;
        top->eval();
        if(dump) tracer->dump(cycle++);
 
        top->clk = 1;
        top->eval();
        if(dump) tracer->dump(cycle++);
 
        tracer->flush();
    }
    tracer->close();
    delete tracer;
    delete top;
 
    return 0;
}
 
//------------------------------------------------------------------------------
 
/*
    input               clk,
    input               rst_n,
 
    output              irq,
 
    //io slave 040h-043h
    input       [1:0]   io_address,
    input               io_read,
    output reg  [7:0]   io_readdata,
    input               io_write,
    input       [7:0]   io_writedata,
 
    //speaker port 61h
    input               speaker_61h_read,
    output      [7:0]   speaker_61h_readdata,
    input               speaker_61h_write,
    input       [7:0]   speaker_61h_writedata,
 
    //speaker output
    output reg          speaker_enable,
    output              speaker_out,
 
    //mgmt slave
    //0.[7:0]: cycles in sysclock 1193181 Hz
 
    input               mgmt_address,
    input               mgmt_write,
    input       [31:0]  mgmt_writedata
*/

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[/] [ao486/] [trunk/] [sim/] [verilator/] [soc/] [pit/] [main.cpp] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	alfik	`#include <cstdio>`
2			`#include <cstdlib>`
3
4			`#include "Vpit.h"`
5			`#include "verilated.h"`
6			`#include "verilated_vcd_c.h"`
7
8			`//------------------------------------------------------------------------------`
9
10			`typedef unsigned int uint32;`
11			`typedef unsigned char uint8;`
12
13			`//------------------------------------------------------------------------------`
14
15			`enum state_t {`
16			`S_IDLE,`
17
18			`S_IO_READ_1,`
19			`S_IO_READ_2,`
20			`S_IO_READ_3,`
21
22			`S_IO_WRITE_1,`
23			`S_IO_WRITE_2,`
24			`S_IO_WRITE_3,`
25
26			`S_DELAY`
27			`};`
28
29			`uint32 address_base;`
30			`uint32 address;`
31			`uint32 byteena;`
32			`uint32 value_base;`
33			`uint32 value;`
34			`state_t state = S_IDLE;`
35			`uint32 shifted;`
36			`uint32 shifted_read;`
37			`uint32 length;`
38			`uint32 value_read;`
39
40			`uint32 delay;`
41
42			`uint32 irq = 0;`
43
44			`void check_byteena(uint32 byteena) {`
45			`if(byteena == 0 \|\| byteena == 5 \|\| byteena == 9 \|\| byteena == 10 \|\| byteena == 11 \|\| byteena == 13) {`
46			`printf("ERROR: invalid byteena: %x\n", byteena);`
47			`exit(-1);`
48			`}`
49
50			`value_read = 0;`
51			`address_base = address;`
52			`value_base = value;`
53			`shifted_read = 0;`
54
55			`shifted = 0;`
56			`for(uint32 i=0; i<4; i++) {`
57			`if(byteena & 1) break;`
58
59			`shifted++;`
60			`address++;`
61			`byteena >>= 1;`
62			`value >>= 8;`
63			`}`
64
65			`length = 0;`
66			`for(uint32 i=0; i<4; i++) {`
67			`if(byteena & 1) length++;`
68
69			`byteena >>= 1;`
70			`}`
71			`}`
72
73			`bool is_address_ok(uint32 address) {`
74			`if(address >= 0x0040 && address <= 0x043) return true;`
75
76			`if(address == 0x0060 && (byteena & 0x2) == 0x2) {`
77			`printf("ERROR: 0x61 port not implemented.\n");`
78			`exit(-1);`
79			`}`
80
81			`return false;`
82			`}`
83
84			`bool next_record() {`
85			`static FILE *fp = NULL;`
86
87			`if(fp == NULL) {`
88			`fp = fopen("./../../../../backup/run-3/track.txt", "rb");`
89			`if(fp == NULL) {`
90			`printf("ERROR: can not open file.\n");`
91			`exit(-1);`
92			`}`
93			`}`
94
95			`do {`
96			`char line[256];`
97			`memset(line, 0, sizeof(line));`
98
99			`char *res = fgets(line, sizeof(line), fp);`
100			`if(res == NULL) {`
101			`fclose(fp);`
102			`fp = NULL;`
103			`return false;`
104			`}`
105
106			`//printf("line: %s\n", line);`
107
108			`int count;`
109
110			`count = sscanf(line, "io rd %x %x %x", &address, &byteena, &value);`
111			`if(count == 3 && is_address_ok(address)) {`
112			`check_byteena(byteena);`
113			`state = S_IO_READ_1;`
114			`printf("line: %s", line);`
115			`return true;`
116			`}`
117			`count = sscanf(line, "io wr %x %x %x", &address, &byteena, &value);`
118			`if(count == 3 && is_address_ok(address)) {`
119			`check_byteena(byteena);`
120			`state = S_IO_WRITE_1;`
121			`printf("line: %s", line);`
122			`return true;`
123			`}`
124
125			`uint32 irq_val = 0;`
126			`count = sscanf(line, "raise_irq %d", &irq_val);`
127			`if(count == 1 && irq_val == 0) {`
128			`irq = 1;`
129
130			`printf("line: %s", line);`
131			`delay = 5;`
132			`state = S_DELAY;`
133			`return true;`
134			`}`
135
136			`count = sscanf(line, "lower_irq %d", &irq_val);`
137			`if(count == 1 && irq_val == 0) {`
138			`irq = 0;`
139
140			`printf("line: %s", line);`
141			`delay = 5;`
142			`state = S_DELAY;`
143			`return true;`
144
145			`}`
146
147
148			`} while(true);`
149
150			`return false;`
151			`}`
152
153			`//------------------------------------------------------------------------------`
154
155			`int main(int argc, char **argv) {`
156			`Verilated::commandArgs(argc, argv);`
157
158			`Verilated::traceEverOn(true);`
159			`VerilatedVcdC* tracer = new VerilatedVcdC;`
160
161			`Vpit *top = new Vpit();`
162			`top->trace (tracer, 99);`
163			`//tracer->rolloverMB(1000000);`
164			`tracer->open("pit.vcd");`
165
166			`bool dump = true;`
167
168			`//reset`
169			`top->clk = 0; top->rst_n = 1; top->eval();`
170			`top->clk = 1; top->rst_n = 1; top->eval();`
171			`top->clk = 1; top->rst_n = 0; top->eval();`
172			`top->clk = 0; top->rst_n = 0; top->eval();`
173			`top->clk = 0; top->rst_n = 1; top->eval();`
174
175			`uint32 cycle = 0;`
176			`while(!Verilated::gotFinish()) {`
177
178			`//----------------------------------------------------------------------`
179
180			`if(state == S_IDLE) {`
181			`bool res = next_record();`
182			`if(res == false) {`
183			`printf("End of file.\n");`
184			`break;`
185			`}`
186
187
188			`}`
189
190			`//----------------------------------------------------------------------`
191
192			`if(state == S_DELAY) {`
193			`delay--;`
194
195			`if(delay == 0) {`
196			`state = S_IDLE;`
197			`}`
198			`}`
199			`else if(state == S_IO_READ_1) {`
200			`if(address >= 0x0040 && address <= 0x0043) {`
201			`top->io_address = address & 0x3;`
202			`top->io_read = 1;`
203			`}`
204			`else {`
205			`printf("ERROR: invalid io rd address: %08x\n", address);`
206			`exit(-1);`
207			`}`
208			`state = S_IO_READ_2;`
209			`}`
210			`else if(state == S_IO_READ_2) {`
211			`length--;`
212			`shifted_read++;`
213
214			`uint32 top_readdata = 0;`
215
216			`if(address >= 0x0040 && address <= 0x0043) top_readdata = top->io_readdata & 0xFF;`
217
218			`if(length > 0) {`
219			`address++;`
220
221			`if(address >= 0x0040 && address <= 0x0043) top->io_address = address & 0x3;`
222			`else {`
223			`printf("ERROR: invalid io rd address: %08x\n", address);`
224			`exit(-1);`
225			`}`
226
227			`value_read \|= (top_readdata & 0xFF) << 24;`
228			`value_read >>= 8;`
229
230			`top->io_read = 0;`
231			`state = S_IO_READ_3;`
232			`}`
233			`else {`
234			`top->io_read = 0;`
235
236			`value_read \|= (top_readdata & 0xFF) << 24;`
237			`value_read >>= 8*(4 - shifted_read - shifted);`
238
239			`if(value_read != value_base) {`
240			`printf("mismatch io rd %08x %x %08x != %08x\n", address_base, byteena, value_base, value_read);`
241
242			`if(! ((address_base == 0x0040 && byteena == 1)))`
243			`exit(0);`
244			`}`
245
246			`delay = 5;`
247			`state = S_DELAY;`
248			`}`
249			`}`
250			`else if(state == S_IO_READ_3) {`
251			`if(address >= 0x0040 && address <= 0x0043) top->io_read = 1;`
252
253			`state = S_IO_READ_2;`
254			`}`
255			`else if(state == S_IO_WRITE_1) {`
256			`if(address >= 0x0040 && address <= 0x0043) {`
257			`top->io_address = address & 0x3;`
258			`top->io_write = 1;`
259			`top->io_writedata = value & 0xFF;`
260			`}`
261			`else {`
262			`printf("ERROR: invalid io wr address: %08x\n", address);`
263			`exit(-1);`
264			`}`
265			`state = S_IO_WRITE_2;`
266			`}`
267			`else if(state == S_IO_WRITE_2) {`
268			`length--;`
269
270			`if(length > 0) {`
271			`address++;`
272			`value >>= 8;`
273
274			`if(address >= 0x0040 && address <= 0x0043) {`
275			`top->io_address = address & 0x3;`
276			`top->io_writedata = value & 0xFF;`
277			`}`
278			`else {`
279			`printf("ERROR: invalid io wr address: %08x\n", address);`
280			`exit(-1);`
281			`}`
282
283			`top->io_write = 0;`
284			`state = S_IO_WRITE_3;`
285			`}`
286			`else {`
287			`top->io_write = 0;`
288
289			`delay = 5;`
290			`state = S_DELAY;`
291			`}`
292			`}`
293			`else if(state == S_IO_WRITE_3) {`
294			`if(address >= 0x0040 && address <= 0x0043) top->io_write = 1;`
295
296			`state = S_IO_WRITE_2;`
297			`}`
298
299			`//----------------------------------------------------------------------`
300
301			`top->clk = 0;`
302			`top->eval();`
303			`if(dump) tracer->dump(cycle++);`
304
305			`top->clk = 1;`
306			`top->eval();`
307			`if(dump) tracer->dump(cycle++);`
308
309			`tracer->flush();`
310			`}`
311			`tracer->close();`
312			`delete tracer;`
313			`delete top;`
314
315			`return 0;`
316			`}`
317
318			`//------------------------------------------------------------------------------`
319
320			`/*`
321			`input clk,`
322			`input rst_n,`
323
324			`output irq,`
325
326			`//io slave 040h-043h`
327			`input [1:0] io_address,`
328			`input io_read,`
329			`output reg [7:0] io_readdata,`
330			`input io_write,`
331			`input [7:0] io_writedata,`
332
333			`//speaker port 61h`
334			`input speaker_61h_read,`
335			`output [7:0] speaker_61h_readdata,`
336			`input speaker_61h_write,`
337			`input [7:0] speaker_61h_writedata,`
338
339			`//speaker output`
340			`output reg speaker_enable,`
341			`output speaker_out,`
342
343			`//mgmt slave`
344			`//0.[7:0]: cycles in sysclock 1193181 Hz`
345
346			`input mgmt_address,`
347			`input mgmt_write,`
348			`input [31:0] mgmt_writedata`
349			`*/`