OpenCores
URL https://opencores.org/ocsvn/ao486/ao486/trunk

Subversion Repositories ao486

[/] [ao486/] [trunk/] [sim/] [verilator/] [soc/] [sound/] [main.cpp] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 alfik
#include <cstdio>
2
#include <cstdlib>
3
#include <unistd.h>
4
 
5
#include "Vsound.h"
6
#include "verilated.h"
7
#include "verilated_vcd_c.h"
8
 
9
//------------------------------------------------------------------------------
10
 
11
typedef unsigned char  uint8;
12
typedef unsigned short uint16;
13
typedef unsigned int   uint32;
14
typedef unsigned long  uint64;
15
 
16
//------------------------------------------------------------------------------
17
 
18
FILE *fp = NULL;
19
int counter_to_end = 0;
20
 
21
void next_write(uint32 &address, uint32 &value, uint32 &wait) {
22
    if(fp == NULL) {
23
        fp = fopen("input.txt", "rb");
24
        if(fp == NULL) {
25
            fprintf(stderr, "can not open file\n");
26
            exit(-1);
27
        }
28
    }
29
    char line[256];
30
 
31
    wait = 0;
32
    while(true) {
33
    char *result = fgets(line, sizeof(line), fp);
34
        if(result == NULL) {
35
            fprintf(stderr, "EOF\n");
36
            wait = 1;
37
            counter_to_end = 100000;
38
            return;
39
        }
40
 
41
        uint32 byteena, val;
42
        int ret = sscanf(line, "io wr 0228 %d %x", &byteena, &val);
43
 
44
        if(ret == 2) {
45
            if(byteena == 1) {
46
                address = 0;
47
                value   = val & 0xFF;
48
                return;
49
            }
50
            else if(byteena == 2) {
51
                address = 1;
52
                value = (val >> 8) & 0xFF;
53
                return;
54
            }
55
            else {
56
                fprintf(stderr, "unknown byteena: %d, val: %08x\n", byteena, val);
57
            }
58
        }
59
        else if(strstr(line, "IAC") != NULL) {
60
            wait = 1;
61
            return;
62
        }
63
        else {
64
            fprintf(stderr, "skipping line: %s\n", line);
65
        }
66
    }
67
}
68
//------------------------------------------------------------------------------
69
 
70
int main(int argc, char **argv) {
71
 
72
    Verilated::commandArgs(argc, argv);
73
 
74
    Verilated::traceEverOn(true);
75
    VerilatedVcdC* tracer = new VerilatedVcdC;
76
 
77
    Vsound *top = new Vsound();
78
    top->trace (tracer, 99);
79
    //tracer->rolloverMB(1000000);
80
    tracer->open("sound.vcd");
81
 
82
    //reset
83
    top->clk = 0; top->rst_n = 1; top->eval();
84
    top->clk = 1; top->rst_n = 1; top->eval();
85
    top->clk = 1; top->rst_n = 0; top->eval();
86
    top->clk = 0; top->rst_n = 0; top->eval();
87
    top->clk = 0; top->rst_n = 1; top->eval();
88
 
89
    bool dump = true;
90
    uint64 cycle = 0;
91
 
92
    int CYCLES_IN_80_US = 2400;
93
    int CYCLES_IN_SAMPLE = 347;
94
 
95
    //256.[12:0]:  cycles in 80us
96
    //257.[9:0]:   cycles in 1 sample: 96000 Hz
97
 
98
    for(uint32 i=256; i<258; i++) {
99
        top->mgmt_write = 1;
100
        top->mgmt_address = i;
101
        top->mgmt_writedata = (i==256)? CYCLES_IN_80_US : CYCLES_IN_SAMPLE;
102
 
103
        top->clk = 0;
104
        top->eval();
105
        if(dump) tracer->dump(cycle++);
106
 
107
        top->clk = 1;
108
        top->eval();
109
        if(dump) tracer->dump(cycle++);
110
 
111
        tracer->flush();
112
    }
113
    top->mgmt_write = 0;
114
 
115
    printf("sound main.cpp\n");
116
 
117
    uint32 DELAY = 200;
118
    uint32 delay = DELAY;
119
    while(!Verilated::gotFinish()) {
120
 
121
        top->fm_write = 0;
122
        if(counter_to_end == 1) break;
123
        if(counter_to_end > 1) counter_to_end--;
124
 
125
        //----------------------------------------------------------------------
126
 
127
        if(delay == 0 && counter_to_end == 0) {
128
            uint32 address, value, wait;
129
 
130
            next_write(address, value, wait);
131
 
132
            if(wait == 0) {
133
                top->fm_address   = address;
134
                top->fm_write     = 1;
135
                top->fm_writedata = value;
136
 
137
                delay = DELAY;
138
            }
139
            else {
140
                delay = 10*DELAY;
141
            }
142
        }
143
        else {
144
            delay--;
145
        }
146
        //----------------------------------------------------------------------
147
 
148
        top->clk = 0;
149
        top->eval();
150
        if(dump) tracer->dump(cycle++);
151
 
152
        top->clk = 1;
153
        top->eval();
154
        if(dump) tracer->dump(cycle++);
155
 
156
        tracer->flush();
157
    }
158
    tracer->close();
159
    delete tracer;
160
    delete top;
161
 
162
    return 0;
163
}
164
 
165
//------------------------------------------------------------------------------
166
 
167
/*
168
module sound(
169
    input               clk,
170
    input               rst_n,
171
 
172
    output              irq,
173
 
174
    //speaker input
175
    input               speaker_enable,
176
    input               speaker_out,
177
 
178
    //io slave 220h-22Fh
179
    input       [3:0]   io_address,
180
    input               io_read,
181
    output reg  [7:0]   io_readdata,
182
    input               io_write,
183
    input       [7:0]   io_writedata,
184
 
185
    //fm music io slave 388h-389h
186
    input               fm_address,
187
    input               fm_read,
188
    output      [7:0]   fm_readdata,
189
    input               fm_write,
190
    input       [7:0]   fm_writedata,
191
 
192
    //dma
193
    output              dma_soundblaster_req,
194
    input               dma_soundblaster_ack,
195
    input               dma_soundblaster_terminal,
196
    input       [7:0]   dma_soundblaster_readdata,
197
    output      [7:0]   dma_soundblaster_writedata,
198
 
199
    //sound interface master
200
    output      [2:0]   avm_address,
201
    input               avm_waitrequest,
202
    output              avm_write,
203
    output      [31:0]  avm_writedata,
204
 
205
    //mgmt slave
206
 
207
    //0-255.[15:0]: cycles in period
208
    //256.[12:0]:  cycles in 80us
209
    //257.[9:0]:   cycles in 1 sample: 96000 Hz
210
 
211
    input       [8:0]   mgmt_address,
212
    input               mgmt_write,
213
    input       [31:0]  mgmt_writedata
214
);
215
*/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.