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[/] [ao486/] [trunk/] [sim/] [verilator/] [soc/] [vga/] [main.cpp] - Blame information for rev 2

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#include <cstdio>
#include <cstring>
#include <cstdlib>
 
#include "Vvga.h"
#include "verilated.h"
#include "verilated_vcd_c.h"
 
//------------------------------------------------------------------------------
 
typedef unsigned int uint32;
typedef unsigned char uint8;
 
//------------------------------------------------------------------------------
 
enum state_t {
    S_IDLE,
 
    S_MEM_READ_1,
    S_MEM_READ_2,
    S_MEM_READ_3,
 
    S_MEM_WRITE_1,
    S_MEM_WRITE_2,
    S_MEM_WRITE_3,
 
    S_IO_READ_1,
    S_IO_READ_2,
    S_IO_READ_3,
 
    S_IO_WRITE_1,
    S_IO_WRITE_2,
    S_IO_WRITE_3,
 
    S_DELAY
};
 
uint32  address_base;
uint32  address;
uint32  byteena;
uint32  value_base;
uint32  value;
state_t state = S_IDLE;
uint32  shifted;
uint32  shifted_read;
uint32  length;
uint32  value_read;
 
uint32  delay;
 
void check_byteena(uint32 byteena) {
    if(byteena == 0 || byteena == 5 || byteena == 9 || byteena == 10 || byteena == 11 || byteena == 13) {
        printf("ERROR: invalid byteena: %x\n", byteena);
        exit(-1);
    }
 
    value_read = 0;
    address_base = address;
    value_base = value;
    shifted_read = 0;
 
    shifted = 0;
    for(uint32 i=0; i<4; i++) {
        if(byteena & 1) break;
 
        shifted++;
        address++;
        byteena >>= 1;
        value >>= 8;
    }
 
    length = 0;
    for(uint32 i=0; i<4; i++) {
        if(byteena & 1) length++;
 
        byteena >>= 1;
    }
}
 
bool next_record() {
    static FILE *fp = NULL;
 
    if(fp == NULL) {
        fp = fopen("./../../../../backup/run-3/track.txt", "rb");
        if(fp == NULL) {
            printf("ERROR: can not open file.\n");
            exit(-1);
        }
    }
 
    do {
        char line[256];
        memset(line, 0, sizeof(line));
 
        char *res = fgets(line, sizeof(line), fp);
        if(res == NULL) {
            fclose(fp);
            fp = NULL;
            return false;
        }
 
//printf("line: %s\n", line);
 
        int count;
 
        count = sscanf(line, "io rd %x %x %x", &address, &byteena, &value);
        if(count == 3 && address >= 0x03B0 && address <= 0x03DF) {
            check_byteena(byteena);
            state = S_IO_READ_1;
            return true;
        }
        count = sscanf(line, "io wr %x %x %x", &address, &byteena, &value);
        if(count == 3 && address >= 0x03B0 && address <= 0x03DF) {
            check_byteena(byteena);
            state = S_IO_WRITE_1;
            return true;
        }
        count = sscanf(line, "vga rd %x %x %x", &address, &byteena, &value);
        if(count == 3 && address >= 0x000A0000 && address <= 0x000BFFFF) {
            check_byteena(byteena);
            state = S_MEM_READ_1;
            return true;
        }
        count = sscanf(line, "vga wr %x %x %x", &address, &byteena, &value);
        if(count == 3 && address >= 0x000A0000 && address <= 0x000BFFFF) {
            check_byteena(byteena);
            state = S_MEM_WRITE_1;
            return true;
        }
    } while(true);
 
    return false;
}
 
 
//------------------------------------------------------------------------------
 
int main(int argc, char **argv) {
    Verilated::commandArgs(argc, argv);
 
    Verilated::traceEverOn(true);
    VerilatedVcdC* tracer = new VerilatedVcdC;
 
    Vvga *top = new Vvga();
    top->trace (tracer, 99);
    //tracer->rolloverMB(1000000);
    tracer->open("vga.vcd");
 
    bool dump = true;
 
    //reset
    top->clk_26 = 0; top->rst_n = 1; top->eval();
    top->clk_26 = 1; top->rst_n = 1; top->eval();
    top->clk_26 = 1; top->rst_n = 0; top->eval();
    top->clk_26 = 0; top->rst_n = 0; top->eval();
    top->clk_26 = 0; top->rst_n = 1; top->eval();
 
    uint32 cycle = 0;
    while(!Verilated::gotFinish()) {
 
        //----------------------------------------------------------------------
 
        if(state == S_IDLE) {
            bool res = next_record();
            if(res == false) {
                printf("End of file.\n");
                break;
            }
        }
 
        //----------------------------------------------------------------------
 
        if(state == S_DELAY) {
            delay--;
 
            if(delay == 0) {
                state = S_IDLE;
            }
        }
        else if(state == S_MEM_READ_1) {
            top->mem_address = address & 0x1FFFF;
            top->mem_read = 1;
 
            state = S_MEM_READ_2;
        }
        else if(state == S_MEM_READ_2) {
            length--;
            shifted_read++;
 
            if(length > 0) {
                address++;
 
                top->mem_address = address & 0x1FFFF;
 
                value_read |= (top->mem_readdata & 0xFF) << 24;
                value_read >>= 8;
 
                top->mem_read = 0;
                state = S_MEM_READ_3;
            }
            else {
                top->mem_read = 0;
 
                value_read |= (top->mem_readdata & 0xFF) << 24;
                value_read >>= 8*(4 - shifted_read - shifted);
 
                if(value_read != value_base) {
                    printf("mismatch mem rd %08x %x %08x != %08x\n", address_base, byteena, value_base, value_read);
exit(0);
                }
 
                delay = 5;
                state = S_DELAY;
            }
        }
        else if(state == S_MEM_READ_3) {
            top->mem_read = 1;
            state = S_MEM_READ_2;
        }
        else if(state == S_MEM_WRITE_1) {
            top->mem_address = address & 0x1FFFF;
            top->mem_write = 1;
            top->mem_writedata = value & 0xFF;
 
            state = S_MEM_WRITE_2;
        }
        else if(state == S_MEM_WRITE_2) {
            length--;
 
            if(length > 0) {
                address++;
 
                top->mem_address = address & 0x1FFFF;
 
                value >>= 8;
                top->mem_writedata = value & 0xFF;
 
                top->mem_write = 0;
                state = S_MEM_WRITE_3;
            }
            else {
                top->mem_write = 0;
 
                delay = 5;
                state = S_DELAY;
            }
        }
        else if(state == S_MEM_WRITE_3) {
            top->mem_write = 1;
            state = S_MEM_WRITE_2;
        }
        else if(state == S_IO_READ_1) {
            if(address >= 0x03B0 && address <= 0x03BF) {
                top->io_b_address = address & 0xF;
                top->io_b_read = 1;
            }
            else if(address >= 0x03C0 && address <= 0x03CF) {
                top->io_c_address = address & 0xF;
                top->io_c_read = 1;
            }
            else if(address >= 0x03D0 && address <= 0x03DF) {
                top->io_d_address = address & 0xF;
                top->io_d_read = 1;
            }
            else {
                printf("ERROR: invalid io rd address: %08x\n", address);
                exit(-1);
            }
            state = S_IO_READ_2;
        }
        else if(state == S_IO_READ_2) {
            length--;
            shifted_read++;
 
            uint32 top_readdata = 0;
 
            if(address >= 0x03B0 && address <= 0x03BF)      top_readdata = top->io_b_readdata & 0xFF;
            else if(address >= 0x03C0 && address <= 0x03CF) top_readdata = top->io_c_readdata & 0xFF;
            else if(address >= 0x03D0 && address <= 0x03DF) top_readdata = top->io_d_readdata & 0xFF;
 
            if(length > 0) {
                address++;
 
                if(address >= 0x03B0 && address <= 0x03BF)      top->io_b_address = address & 0xF;
                else if(address >= 0x03C0 && address <= 0x03CF) top->io_c_address = address & 0xF;
                else if(address >= 0x03D0 && address <= 0x03DF) top->io_d_address = address & 0xF;
                else {
                    printf("ERROR: invalid io rd address: %08x\n", address);
                    exit(-1);
                }
 
                value_read |= (top_readdata & 0xFF) << 24;
                value_read >>= 8;
 
                top->io_b_read = 0;
                top->io_c_read = 0;
                top->io_d_read = 0;
                state = S_IO_READ_3;
            }
            else {
                top->io_b_read = 0;
                top->io_c_read = 0;
                top->io_d_read = 0;
 
                value_read |= (top_readdata & 0xFF) << 24;
                value_read >>= 8*(4 - shifted_read - shifted);
 
                if(value_read != value_base) {
                    printf("mismatch io rd %08x %x %08x != %08x\n", address_base, byteena, value_base, value_read);
 
if(! ((address_base == 0x03D8 && byteena == 4) || (address_base == 0x03C8 && byteena == 4)))
exit(0);
                }
 
                delay = 5;
                state = S_DELAY;
            }
        }
        else if(state == S_IO_READ_3) {
            if(address >= 0x03B0 && address <= 0x03BF)      top->io_b_read = 1;
            else if(address >= 0x03C0 && address <= 0x03CF) top->io_c_read = 1;
            else if(address >= 0x03D0 && address <= 0x03DF) top->io_d_read = 1;
 
            state = S_IO_READ_2;
        }
        else if(state == S_IO_WRITE_1) {
            if(address >= 0x03B0 && address <= 0x03BF) {
                top->io_b_address = address & 0xF;
                top->io_b_write = 1;
                top->io_b_writedata = value & 0xFF;
            }
            else if(address >= 0x03C0 && address <= 0x03CF) {
                top->io_c_address = address & 0xF;
                top->io_c_write = 1;
                top->io_c_writedata = value & 0xFF;
            }
            else if(address >= 0x03D0 && address <= 0x03DF) {
                top->io_d_address = address & 0xF;
                top->io_d_write = 1;
                top->io_d_writedata = value & 0xFF;
            }
            else {
                printf("ERROR: invalid io wr address: %08x\n", address);
                exit(-1);
            }
            state = S_IO_WRITE_2;
        }
        else if(state == S_IO_WRITE_2) {
            length--;
 
            if(length > 0) {
                address++;
                value >>= 8;
 
                if(address >= 0x03B0 && address <= 0x03BF) {
                    top->io_b_address = address & 0xF;
                    top->io_b_writedata = value & 0xFF;
                }
                else if(address >= 0x03C0 && address <= 0x03CF) {
                    top->io_c_address = address & 0xF;
                    top->io_c_writedata = value & 0xFF;
                }
                else if(address >= 0x03D0 && address <= 0x03DF) {
                    top->io_d_address = address & 0xF;
                    top->io_d_writedata = value & 0xFF;
                }
                else {
                    printf("ERROR: invalid io wr address: %08x\n", address);
                    exit(-1);
                }
 
                top->io_b_write = 0;
                top->io_c_write = 0;
                top->io_d_write = 0;
                state = S_IO_WRITE_3;
            }
            else {
                top->io_b_write = 0;
                top->io_c_write = 0;
                top->io_d_write = 0;
 
                delay = 5;
                state = S_DELAY;
            }
        }
        else if(state == S_IO_WRITE_3) {
            if(address >= 0x03B0 && address <= 0x03BF)      top->io_b_write = 1;
            else if(address >= 0x03C0 && address <= 0x03CF) top->io_c_write = 1;
            else if(address >= 0x03D0 && address <= 0x03DF) top->io_d_write = 1;
 
            state = S_IO_WRITE_2;
        }
 
        //----------------------------------------------------------------------
 
        top->clk_26 = 0;
        top->eval();
        if(dump) tracer->dump(cycle++);
 
        top->clk_26 = 1;
        top->eval();
        if(dump) tracer->dump(cycle++);
 
        //if((cycle % 1000) == 0) printf("half-cycle: %d\n", cycle);
 
        tracer->flush();
    }
    tracer->close();
    delete tracer;
    delete top;
 
    return 0;
}
 
//------------------------------------------------------------------------------
 
/*
    input               clk_26,
    input               rst_n,
 
    //avalon slave for system overlay
    input       [7:0]   sys_address,
    input               sys_read,
    output      [31:0]  sys_readdata,
    input               sys_write,
    input       [31:0]  sys_writedata,
 
    //avalon slave vga io 0x3B0 - 0x3BF
    input       [3:0]   io_b_address,
    input               io_b_read,
    output      [7:0]   io_b_readdata,
    input               io_b_write,
    input       [7:0]   io_b_writedata,
 
    //avalon slave vga io 0x3C0 - 0xCF
    input       [3:0]   io_c_address,
    input               io_c_read,
    output      [7:0]   io_c_readdata,
    input               io_c_write,
    input       [7:0]   io_c_writedata,
 
    //avalon slave vga io 0x3D0 - 0x3DF
    input       [3:0]   io_d_address,
    input               io_d_read,
    output      [7:0]   io_d_readdata,
    input               io_d_write,
    input       [7:0]   io_d_writedata,
 
    //avalon slave vga memory 0xA0000 - 0xBFFFF
    input       [16:0]  mem_address,
    input               mem_read,
    output      [7:0]   mem_readdata,
    input               mem_write,
    input       [7:0]   mem_writedata,
*/

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[/] [ao486/] [trunk/] [sim/] [verilator/] [soc/] [vga/] [main.cpp] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	alfik	`#include <cstdio>`
2			`#include <cstring>`
3			`#include <cstdlib>`
4
5			`#include "Vvga.h"`
6			`#include "verilated.h"`
7			`#include "verilated_vcd_c.h"`
8
9			`//------------------------------------------------------------------------------`
10
11			`typedef unsigned int uint32;`
12			`typedef unsigned char uint8;`
13
14			`//------------------------------------------------------------------------------`
15
16			`enum state_t {`
17			`S_IDLE,`
18
19			`S_MEM_READ_1,`
20			`S_MEM_READ_2,`
21			`S_MEM_READ_3,`
22
23			`S_MEM_WRITE_1,`
24			`S_MEM_WRITE_2,`
25			`S_MEM_WRITE_3,`
26
27			`S_IO_READ_1,`
28			`S_IO_READ_2,`
29			`S_IO_READ_3,`
30
31			`S_IO_WRITE_1,`
32			`S_IO_WRITE_2,`
33			`S_IO_WRITE_3,`
34
35			`S_DELAY`
36			`};`
37
38			`uint32 address_base;`
39			`uint32 address;`
40			`uint32 byteena;`
41			`uint32 value_base;`
42			`uint32 value;`
43			`state_t state = S_IDLE;`
44			`uint32 shifted;`
45			`uint32 shifted_read;`
46			`uint32 length;`
47			`uint32 value_read;`
48
49			`uint32 delay;`
50
51			`void check_byteena(uint32 byteena) {`
52			`if(byteena == 0 \|\| byteena == 5 \|\| byteena == 9 \|\| byteena == 10 \|\| byteena == 11 \|\| byteena == 13) {`
53			`printf("ERROR: invalid byteena: %x\n", byteena);`
54			`exit(-1);`
55			`}`
56
57			`value_read = 0;`
58			`address_base = address;`
59			`value_base = value;`
60			`shifted_read = 0;`
61
62			`shifted = 0;`
63			`for(uint32 i=0; i<4; i++) {`
64			`if(byteena & 1) break;`
65
66			`shifted++;`
67			`address++;`
68			`byteena >>= 1;`
69			`value >>= 8;`
70			`}`
71
72			`length = 0;`
73			`for(uint32 i=0; i<4; i++) {`
74			`if(byteena & 1) length++;`
75
76			`byteena >>= 1;`
77			`}`
78			`}`
79
80			`bool next_record() {`
81			`static FILE *fp = NULL;`
82
83			`if(fp == NULL) {`
84			`fp = fopen("./../../../../backup/run-3/track.txt", "rb");`
85			`if(fp == NULL) {`
86			`printf("ERROR: can not open file.\n");`
87			`exit(-1);`
88			`}`
89			`}`
90
91			`do {`
92			`char line[256];`
93			`memset(line, 0, sizeof(line));`
94
95			`char *res = fgets(line, sizeof(line), fp);`
96			`if(res == NULL) {`
97			`fclose(fp);`
98			`fp = NULL;`
99			`return false;`
100			`}`
101
102			`//printf("line: %s\n", line);`
103
104			`int count;`
105
106			`count = sscanf(line, "io rd %x %x %x", &address, &byteena, &value);`
107			`if(count == 3 && address >= 0x03B0 && address <= 0x03DF) {`
108			`check_byteena(byteena);`
109			`state = S_IO_READ_1;`
110			`return true;`
111			`}`
112			`count = sscanf(line, "io wr %x %x %x", &address, &byteena, &value);`
113			`if(count == 3 && address >= 0x03B0 && address <= 0x03DF) {`
114			`check_byteena(byteena);`
115			`state = S_IO_WRITE_1;`
116			`return true;`
117			`}`
118			`count = sscanf(line, "vga rd %x %x %x", &address, &byteena, &value);`
119			`if(count == 3 && address >= 0x000A0000 && address <= 0x000BFFFF) {`
120			`check_byteena(byteena);`
121			`state = S_MEM_READ_1;`
122			`return true;`
123			`}`
124			`count = sscanf(line, "vga wr %x %x %x", &address, &byteena, &value);`
125			`if(count == 3 && address >= 0x000A0000 && address <= 0x000BFFFF) {`
126			`check_byteena(byteena);`
127			`state = S_MEM_WRITE_1;`
128			`return true;`
129			`}`
130			`} while(true);`
131
132			`return false;`
133			`}`
134
135
136			`//------------------------------------------------------------------------------`
137
138			`int main(int argc, char **argv) {`
139			`Verilated::commandArgs(argc, argv);`
140
141			`Verilated::traceEverOn(true);`
142			`VerilatedVcdC* tracer = new VerilatedVcdC;`
143
144			`Vvga *top = new Vvga();`
145			`top->trace (tracer, 99);`
146			`//tracer->rolloverMB(1000000);`
147			`tracer->open("vga.vcd");`
148
149			`bool dump = true;`
150
151			`//reset`
152			`top->clk_26 = 0; top->rst_n = 1; top->eval();`
153			`top->clk_26 = 1; top->rst_n = 1; top->eval();`
154			`top->clk_26 = 1; top->rst_n = 0; top->eval();`
155			`top->clk_26 = 0; top->rst_n = 0; top->eval();`
156			`top->clk_26 = 0; top->rst_n = 1; top->eval();`
157
158			`uint32 cycle = 0;`
159			`while(!Verilated::gotFinish()) {`
160
161			`//----------------------------------------------------------------------`
162
163			`if(state == S_IDLE) {`
164			`bool res = next_record();`
165			`if(res == false) {`
166			`printf("End of file.\n");`
167			`break;`
168			`}`
169			`}`
170
171			`//----------------------------------------------------------------------`
172
173			`if(state == S_DELAY) {`
174			`delay--;`
175
176			`if(delay == 0) {`
177			`state = S_IDLE;`
178			`}`
179			`}`
180			`else if(state == S_MEM_READ_1) {`
181			`top->mem_address = address & 0x1FFFF;`
182			`top->mem_read = 1;`
183
184			`state = S_MEM_READ_2;`
185			`}`
186			`else if(state == S_MEM_READ_2) {`
187			`length--;`
188			`shifted_read++;`
189
190			`if(length > 0) {`
191			`address++;`
192
193			`top->mem_address = address & 0x1FFFF;`
194
195			`value_read \|= (top->mem_readdata & 0xFF) << 24;`
196			`value_read >>= 8;`
197
198			`top->mem_read = 0;`
199			`state = S_MEM_READ_3;`
200			`}`
201			`else {`
202			`top->mem_read = 0;`
203
204			`value_read \|= (top->mem_readdata & 0xFF) << 24;`
205			`value_read >>= 8*(4 - shifted_read - shifted);`
206
207			`if(value_read != value_base) {`
208			`printf("mismatch mem rd %08x %x %08x != %08x\n", address_base, byteena, value_base, value_read);`
209			`exit(0);`
210			`}`
211
212			`delay = 5;`
213			`state = S_DELAY;`
214			`}`
215			`}`
216			`else if(state == S_MEM_READ_3) {`
217			`top->mem_read = 1;`
218			`state = S_MEM_READ_2;`
219			`}`
220			`else if(state == S_MEM_WRITE_1) {`
221			`top->mem_address = address & 0x1FFFF;`
222			`top->mem_write = 1;`
223			`top->mem_writedata = value & 0xFF;`
224
225			`state = S_MEM_WRITE_2;`
226			`}`
227			`else if(state == S_MEM_WRITE_2) {`
228			`length--;`
229
230			`if(length > 0) {`
231			`address++;`
232
233			`top->mem_address = address & 0x1FFFF;`
234
235			`value >>= 8;`
236			`top->mem_writedata = value & 0xFF;`
237
238			`top->mem_write = 0;`
239			`state = S_MEM_WRITE_3;`
240			`}`
241			`else {`
242			`top->mem_write = 0;`
243
244			`delay = 5;`
245			`state = S_DELAY;`
246			`}`
247			`}`
248			`else if(state == S_MEM_WRITE_3) {`
249			`top->mem_write = 1;`
250			`state = S_MEM_WRITE_2;`
251			`}`
252			`else if(state == S_IO_READ_1) {`
253			`if(address >= 0x03B0 && address <= 0x03BF) {`
254			`top->io_b_address = address & 0xF;`
255			`top->io_b_read = 1;`
256			`}`
257			`else if(address >= 0x03C0 && address <= 0x03CF) {`
258			`top->io_c_address = address & 0xF;`
259			`top->io_c_read = 1;`
260			`}`
261			`else if(address >= 0x03D0 && address <= 0x03DF) {`
262			`top->io_d_address = address & 0xF;`
263			`top->io_d_read = 1;`
264			`}`
265			`else {`
266			`printf("ERROR: invalid io rd address: %08x\n", address);`
267			`exit(-1);`
268			`}`
269			`state = S_IO_READ_2;`
270			`}`
271			`else if(state == S_IO_READ_2) {`
272			`length--;`
273			`shifted_read++;`
274
275			`uint32 top_readdata = 0;`
276
277			`if(address >= 0x03B0 && address <= 0x03BF) top_readdata = top->io_b_readdata & 0xFF;`
278			`else if(address >= 0x03C0 && address <= 0x03CF) top_readdata = top->io_c_readdata & 0xFF;`
279			`else if(address >= 0x03D0 && address <= 0x03DF) top_readdata = top->io_d_readdata & 0xFF;`
280
281			`if(length > 0) {`
282			`address++;`
283
284			`if(address >= 0x03B0 && address <= 0x03BF) top->io_b_address = address & 0xF;`
285			`else if(address >= 0x03C0 && address <= 0x03CF) top->io_c_address = address & 0xF;`
286			`else if(address >= 0x03D0 && address <= 0x03DF) top->io_d_address = address & 0xF;`
287			`else {`
288			`printf("ERROR: invalid io rd address: %08x\n", address);`
289			`exit(-1);`
290			`}`
291
292			`value_read \|= (top_readdata & 0xFF) << 24;`
293			`value_read >>= 8;`
294
295			`top->io_b_read = 0;`
296			`top->io_c_read = 0;`
297			`top->io_d_read = 0;`
298			`state = S_IO_READ_3;`
299			`}`
300			`else {`
301			`top->io_b_read = 0;`
302			`top->io_c_read = 0;`
303			`top->io_d_read = 0;`
304
305			`value_read \|= (top_readdata & 0xFF) << 24;`
306			`value_read >>= 8*(4 - shifted_read - shifted);`
307
308			`if(value_read != value_base) {`
309			`printf("mismatch io rd %08x %x %08x != %08x\n", address_base, byteena, value_base, value_read);`
310
311			`if(! ((address_base == 0x03D8 && byteena == 4) \|\| (address_base == 0x03C8 && byteena == 4)))`
312			`exit(0);`
313			`}`
314
315			`delay = 5;`
316			`state = S_DELAY;`
317			`}`
318			`}`
319			`else if(state == S_IO_READ_3) {`
320			`if(address >= 0x03B0 && address <= 0x03BF) top->io_b_read = 1;`
321			`else if(address >= 0x03C0 && address <= 0x03CF) top->io_c_read = 1;`
322			`else if(address >= 0x03D0 && address <= 0x03DF) top->io_d_read = 1;`
323
324			`state = S_IO_READ_2;`
325			`}`
326			`else if(state == S_IO_WRITE_1) {`
327			`if(address >= 0x03B0 && address <= 0x03BF) {`
328			`top->io_b_address = address & 0xF;`
329			`top->io_b_write = 1;`
330			`top->io_b_writedata = value & 0xFF;`
331			`}`
332			`else if(address >= 0x03C0 && address <= 0x03CF) {`
333			`top->io_c_address = address & 0xF;`
334			`top->io_c_write = 1;`
335			`top->io_c_writedata = value & 0xFF;`
336			`}`
337			`else if(address >= 0x03D0 && address <= 0x03DF) {`
338			`top->io_d_address = address & 0xF;`
339			`top->io_d_write = 1;`
340			`top->io_d_writedata = value & 0xFF;`
341			`}`
342			`else {`
343			`printf("ERROR: invalid io wr address: %08x\n", address);`
344			`exit(-1);`
345			`}`
346			`state = S_IO_WRITE_2;`
347			`}`
348			`else if(state == S_IO_WRITE_2) {`
349			`length--;`
350
351			`if(length > 0) {`
352			`address++;`
353			`value >>= 8;`
354
355			`if(address >= 0x03B0 && address <= 0x03BF) {`
356			`top->io_b_address = address & 0xF;`
357			`top->io_b_writedata = value & 0xFF;`
358			`}`
359			`else if(address >= 0x03C0 && address <= 0x03CF) {`
360			`top->io_c_address = address & 0xF;`
361			`top->io_c_writedata = value & 0xFF;`
362			`}`
363			`else if(address >= 0x03D0 && address <= 0x03DF) {`
364			`top->io_d_address = address & 0xF;`
365			`top->io_d_writedata = value & 0xFF;`
366			`}`
367			`else {`
368			`printf("ERROR: invalid io wr address: %08x\n", address);`
369			`exit(-1);`
370			`}`
371
372			`top->io_b_write = 0;`
373			`top->io_c_write = 0;`
374			`top->io_d_write = 0;`
375			`state = S_IO_WRITE_3;`
376			`}`
377			`else {`
378			`top->io_b_write = 0;`
379			`top->io_c_write = 0;`
380			`top->io_d_write = 0;`
381
382			`delay = 5;`
383			`state = S_DELAY;`
384			`}`
385			`}`
386			`else if(state == S_IO_WRITE_3) {`
387			`if(address >= 0x03B0 && address <= 0x03BF) top->io_b_write = 1;`
388			`else if(address >= 0x03C0 && address <= 0x03CF) top->io_c_write = 1;`
389			`else if(address >= 0x03D0 && address <= 0x03DF) top->io_d_write = 1;`
390
391			`state = S_IO_WRITE_2;`
392			`}`
393
394			`//----------------------------------------------------------------------`
395
396			`top->clk_26 = 0;`
397			`top->eval();`
398			`if(dump) tracer->dump(cycle++);`
399
400			`top->clk_26 = 1;`
401			`top->eval();`
402			`if(dump) tracer->dump(cycle++);`
403
404			`//if((cycle % 1000) == 0) printf("half-cycle: %d\n", cycle);`
405
406			`tracer->flush();`
407			`}`
408			`tracer->close();`
409			`delete tracer;`
410			`delete top;`
411
412			`return 0;`
413			`}`
414
415			`//------------------------------------------------------------------------------`
416
417			`/*`
418			`input clk_26,`
419			`input rst_n,`
420
421			`//avalon slave for system overlay`
422			`input [7:0] sys_address,`
423			`input sys_read,`
424			`output [31:0] sys_readdata,`
425			`input sys_write,`
426			`input [31:0] sys_writedata,`
427
428			`//avalon slave vga io 0x3B0 - 0x3BF`
429			`input [3:0] io_b_address,`
430			`input io_b_read,`
431			`output [7:0] io_b_readdata,`
432			`input io_b_write,`
433			`input [7:0] io_b_writedata,`
434
435			`//avalon slave vga io 0x3C0 - 0xCF`
436			`input [3:0] io_c_address,`
437			`input io_c_read,`
438			`output [7:0] io_c_readdata,`
439			`input io_c_write,`
440			`input [7:0] io_c_writedata,`
441
442			`//avalon slave vga io 0x3D0 - 0x3DF`
443			`input [3:0] io_d_address,`
444			`input io_d_read,`
445			`output [7:0] io_d_readdata,`
446			`input io_d_write,`
447			`input [7:0] io_d_writedata,`
448
449			`//avalon slave vga memory 0xA0000 - 0xBFFFF`
450			`input [16:0] mem_address,`
451			`input mem_read,`
452			`output [7:0] mem_readdata,`
453			`input mem_write,`
454			`input [7:0] mem_writedata,`
455			`*/`