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alfik |
#include <cstdio>
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#include <cstdlib>
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#include <dlfcn.h>
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#include <sys/mman.h>
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#include <sys/types.h>
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#include <sys/stat.h>
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#include <fcntl.h>
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#include <unistd.h>
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#include "Vvga.h"
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#include "verilated.h"
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#include "verilated_vcd_c.h"
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#include "shared_mem.h"
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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volatile shared_mem_t *shared_ptr = NULL;
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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int main(int argc, char **argv) {
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//map shared memory
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int fd = open("./../../../sim_pc/shared_mem.dat", O_RDWR, S_IRUSR | S_IWUSR);
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if(fd == -1) {
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perror("open() failed for shared_mem.dat");
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return -1;
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}
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shared_ptr = (shared_mem_t *)mmap(NULL, sizeof(shared_mem_t), PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
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if(shared_ptr == MAP_FAILED) {
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perror("mmap() failed");
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close(fd);
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return -2;
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}
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Verilated::commandArgs(argc, argv);
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Verilated::traceEverOn(true);
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VerilatedVcdC* tracer = new VerilatedVcdC;
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Vvga *top = new Vvga();
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top->trace (tracer, 99);
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//tracer->rolloverMB(1000000);
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tracer->open("vga.vcd");
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bool dump = false;
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//reset
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top->clk_26 = 0; top->rst_n = 1; top->eval();
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top->clk_26 = 1; top->rst_n = 1; top->eval();
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top->clk_26 = 1; top->rst_n = 0; top->eval();
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top->clk_26 = 0; top->rst_n = 0; top->eval();
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top->clk_26 = 0; top->rst_n = 1; top->eval();
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uint64 cycle = 0;
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bool read_cycle = false;
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bool read_mem_cycle = false;
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uint32 curr_io_byteenable = 0;
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uint32 curr_io_byteena_modif = 0;
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step_t curr_io_step = STEP_IDLE;
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uint32 curr_mem_byteenable = 0;
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uint32 curr_mem_byteena_modif = 0;
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step_t curr_mem_step = STEP_IDLE;
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uint32 curr_mrd_byteenable = 0;
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uint32 curr_mrd_byteena_modif = 0;
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step_t curr_mrd_step = STEP_IDLE;
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printf("vga main_plugin.cpp\n");
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while(!Verilated::gotFinish()) {
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//----------------------------------------------------------------------
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/*
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uint32 combined.io_address;
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uint32 combined.io_data;
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uint32 combined.io_byteenable;
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uint32 combined.io_is_write;
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step_t combined.io_step;
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//avalon slave vga io 0x3B0 - 0x3BF
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input [3:0] io_b_address,
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input io_b_read,
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output [7:0] io_b_readdata,
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input io_b_write,
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input [7:0] io_b_writedata,
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//avalon slave vga io 0x3C0 - 0xCF
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input [3:0] io_c_address,
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input io_c_read,
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output [7:0] io_c_readdata,
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input io_c_write,
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input [7:0] io_c_writedata,
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//avalon slave vga io 0x3D0 - 0x3DF
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input [3:0] io_d_address,
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input io_d_read,
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output [7:0] io_d_readdata,
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input io_d_write,
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input [7:0] io_d_writedata,
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*/
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if(shared_ptr->combined.io_step == STEP_REQ && shared_ptr->combined.io_is_write &&
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(shared_ptr->combined.io_address == 0x03B0 || shared_ptr->combined.io_address == 0x03B4 || shared_ptr->combined.io_address == 0x03B8 || shared_ptr->combined.io_address == 0x03BC ||
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shared_ptr->combined.io_address == 0x03C0 || shared_ptr->combined.io_address == 0x03C4 || shared_ptr->combined.io_address == 0x03C8 || shared_ptr->combined.io_address == 0x03CC ||
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shared_ptr->combined.io_address == 0x03D0 || shared_ptr->combined.io_address == 0x03D4 || shared_ptr->combined.io_address == 0x03D8 || shared_ptr->combined.io_address == 0x03DC))
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{
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if(curr_io_step == STEP_IDLE) {
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curr_io_byteena_modif = shared_ptr->combined.io_byteenable;
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curr_io_step = STEP_REQ;
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}
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if(curr_io_step == STEP_REQ) {
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if((curr_io_byteena_modif >> 0) & 1) {
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curr_io_byteenable = 1;
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curr_io_byteena_modif &= 0xE;
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}
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else if((curr_io_byteena_modif >> 1) & 1) {
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curr_io_byteenable = 2;
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curr_io_byteena_modif &= 0xC;
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}
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else if((curr_io_byteena_modif >> 2) & 1) {
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curr_io_byteenable = 4;
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curr_io_byteena_modif &= 0x8;
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}
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else if((curr_io_byteena_modif >> 3) & 1) {
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curr_io_byteenable = 8;
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curr_io_byteena_modif &= 0x0;
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}
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else {
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shared_ptr->combined.io_step = STEP_ACK;
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curr_io_step = STEP_IDLE;
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}
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}
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}
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top->io_b_read = 0;
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top->io_b_write = 0;
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top->io_c_read = 0;
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top->io_c_write = 0;
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top->io_d_read = 0;
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top->io_d_write = 0;
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if(shared_ptr->combined.io_step == STEP_REQ && shared_ptr->combined.io_is_write && curr_io_step == STEP_REQ &&
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(shared_ptr->combined.io_address == 0x03B0 || shared_ptr->combined.io_address == 0x03B4 || shared_ptr->combined.io_address == 0x03B8 || shared_ptr->combined.io_address == 0x03BC ||
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shared_ptr->combined.io_address == 0x03C0 || shared_ptr->combined.io_address == 0x03C4 || shared_ptr->combined.io_address == 0x03C8 || shared_ptr->combined.io_address == 0x03CC ||
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shared_ptr->combined.io_address == 0x03D0 || shared_ptr->combined.io_address == 0x03D4 || shared_ptr->combined.io_address == 0x03D8 || shared_ptr->combined.io_address == 0x03DC))
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{
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if(curr_io_byteenable != 1 && curr_io_byteenable != 2 && curr_io_byteenable != 4 && curr_io_byteenable != 8) {
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printf("Vvga: curr_io_byteenable invalid: %04x %x\n", shared_ptr->combined.io_address, curr_io_byteenable);
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exit(-1);
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}
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top->io_b_address = (shared_ptr->combined.io_address == 0x03B0 && curr_io_byteenable == 1)? 0 :
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(shared_ptr->combined.io_address == 0x03B0 && curr_io_byteenable == 2)? 1 :
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(shared_ptr->combined.io_address == 0x03B0 && curr_io_byteenable == 4)? 2 :
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(shared_ptr->combined.io_address == 0x03B0 && curr_io_byteenable == 8)? 3 :
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(shared_ptr->combined.io_address == 0x03B4 && curr_io_byteenable == 1)? 4 :
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(shared_ptr->combined.io_address == 0x03B4 && curr_io_byteenable == 2)? 5 :
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(shared_ptr->combined.io_address == 0x03B4 && curr_io_byteenable == 4)? 6 :
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(shared_ptr->combined.io_address == 0x03B4 && curr_io_byteenable == 8)? 7 :
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(shared_ptr->combined.io_address == 0x03B8 && curr_io_byteenable == 1)? 8 :
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(shared_ptr->combined.io_address == 0x03B8 && curr_io_byteenable == 2)? 9 :
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(shared_ptr->combined.io_address == 0x03B8 && curr_io_byteenable == 4)? 10 :
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(shared_ptr->combined.io_address == 0x03B8 && curr_io_byteenable == 8)? 11 :
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(shared_ptr->combined.io_address == 0x03BC && curr_io_byteenable == 1)? 12 :
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(shared_ptr->combined.io_address == 0x03BC && curr_io_byteenable == 2)? 13 :
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(shared_ptr->combined.io_address == 0x03BC && curr_io_byteenable == 4)? 14 :
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15;
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top->io_c_address = (shared_ptr->combined.io_address == 0x03C0 && curr_io_byteenable == 1)? 0 :
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(shared_ptr->combined.io_address == 0x03C0 && curr_io_byteenable == 2)? 1 :
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(shared_ptr->combined.io_address == 0x03C0 && curr_io_byteenable == 4)? 2 :
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(shared_ptr->combined.io_address == 0x03C0 && curr_io_byteenable == 8)? 3 :
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(shared_ptr->combined.io_address == 0x03C4 && curr_io_byteenable == 1)? 4 :
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(shared_ptr->combined.io_address == 0x03C4 && curr_io_byteenable == 2)? 5 :
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(shared_ptr->combined.io_address == 0x03C4 && curr_io_byteenable == 4)? 6 :
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(shared_ptr->combined.io_address == 0x03C4 && curr_io_byteenable == 8)? 7 :
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(shared_ptr->combined.io_address == 0x03C8 && curr_io_byteenable == 1)? 8 :
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(shared_ptr->combined.io_address == 0x03C8 && curr_io_byteenable == 2)? 9 :
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(shared_ptr->combined.io_address == 0x03C8 && curr_io_byteenable == 4)? 10 :
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| 197 |
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(shared_ptr->combined.io_address == 0x03C8 && curr_io_byteenable == 8)? 11 :
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| 198 |
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(shared_ptr->combined.io_address == 0x03CC && curr_io_byteenable == 1)? 12 :
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(shared_ptr->combined.io_address == 0x03CC && curr_io_byteenable == 2)? 13 :
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| 200 |
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(shared_ptr->combined.io_address == 0x03CC && curr_io_byteenable == 4)? 14 :
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15;
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| 203 |
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top->io_d_address = (shared_ptr->combined.io_address == 0x03D0 && curr_io_byteenable == 1)? 0 :
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| 204 |
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(shared_ptr->combined.io_address == 0x03D0 && curr_io_byteenable == 2)? 1 :
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| 205 |
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(shared_ptr->combined.io_address == 0x03D0 && curr_io_byteenable == 4)? 2 :
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| 206 |
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(shared_ptr->combined.io_address == 0x03D0 && curr_io_byteenable == 8)? 3 :
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| 207 |
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(shared_ptr->combined.io_address == 0x03D4 && curr_io_byteenable == 1)? 4 :
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| 208 |
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(shared_ptr->combined.io_address == 0x03D4 && curr_io_byteenable == 2)? 5 :
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| 209 |
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(shared_ptr->combined.io_address == 0x03D4 && curr_io_byteenable == 4)? 6 :
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| 210 |
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(shared_ptr->combined.io_address == 0x03D4 && curr_io_byteenable == 8)? 7 :
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| 211 |
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(shared_ptr->combined.io_address == 0x03D8 && curr_io_byteenable == 1)? 8 :
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| 212 |
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(shared_ptr->combined.io_address == 0x03D8 && curr_io_byteenable == 2)? 9 :
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| 213 |
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(shared_ptr->combined.io_address == 0x03D8 && curr_io_byteenable == 4)? 10 :
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| 214 |
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(shared_ptr->combined.io_address == 0x03D8 && curr_io_byteenable == 8)? 11 :
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| 215 |
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(shared_ptr->combined.io_address == 0x03DC && curr_io_byteenable == 1)? 12 :
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| 216 |
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(shared_ptr->combined.io_address == 0x03DC && curr_io_byteenable == 2)? 13 :
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| 217 |
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(shared_ptr->combined.io_address == 0x03DC && curr_io_byteenable == 4)? 14 :
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| 218 |
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15;
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| 219 |
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| 220 |
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| 221 |
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top->io_b_writedata = (curr_io_byteenable == 1)? shared_ptr->combined.io_data & 0xFF :
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| 222 |
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(curr_io_byteenable == 2)? (shared_ptr->combined.io_data >> 8) & 0xFF :
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| 223 |
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(curr_io_byteenable == 4)? (shared_ptr->combined.io_data >> 16) & 0xFF :
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| 224 |
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(shared_ptr->combined.io_data >> 24) & 0xFF;
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| 225 |
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| 226 |
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top->io_c_writedata = (curr_io_byteenable == 1)? shared_ptr->combined.io_data & 0xFF :
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| 227 |
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(curr_io_byteenable == 2)? (shared_ptr->combined.io_data >> 8) & 0xFF :
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| 228 |
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(curr_io_byteenable == 4)? (shared_ptr->combined.io_data >> 16) & 0xFF :
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| 229 |
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(shared_ptr->combined.io_data >> 24) & 0xFF;
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| 230 |
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| 231 |
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top->io_d_writedata = (curr_io_byteenable == 1)? shared_ptr->combined.io_data & 0xFF :
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| 232 |
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(curr_io_byteenable == 2)? (shared_ptr->combined.io_data >> 8) & 0xFF :
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| 233 |
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(curr_io_byteenable == 4)? (shared_ptr->combined.io_data >> 16) & 0xFF :
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| 234 |
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(shared_ptr->combined.io_data >> 24) & 0xFF;
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| 235 |
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| 236 |
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if(shared_ptr->combined.io_address == 0x03B0 || shared_ptr->combined.io_address == 0x03B4 || shared_ptr->combined.io_address == 0x03B8 || shared_ptr->combined.io_address == 0x03BC) {
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| 237 |
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top->io_b_read = 0;
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| 238 |
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top->io_b_write = 1;
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| 239 |
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}
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| 240 |
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if(shared_ptr->combined.io_address == 0x03C0 || shared_ptr->combined.io_address == 0x03C4 || shared_ptr->combined.io_address == 0x03C8 || shared_ptr->combined.io_address == 0x03CC) {
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| 241 |
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top->io_c_read = 0;
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| 242 |
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top->io_c_write = 1;
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| 243 |
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}
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| 244 |
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if(shared_ptr->combined.io_address == 0x03D0 || shared_ptr->combined.io_address == 0x03D4 || shared_ptr->combined.io_address == 0x03D8 || shared_ptr->combined.io_address == 0x03DC) {
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| 245 |
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top->io_d_read = 0;
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| 246 |
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top->io_d_write = 1;
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| 247 |
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}
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| 248 |
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}
|
| 249 |
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| 250 |
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if(read_cycle == false) {
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| 251 |
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if(shared_ptr->combined.io_step == STEP_REQ && shared_ptr->combined.io_is_write == 0 &&
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| 252 |
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(shared_ptr->combined.io_address == 0x03B0 || shared_ptr->combined.io_address == 0x03B4 || shared_ptr->combined.io_address == 0x03B8 || shared_ptr->combined.io_address == 0x03BC ||
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| 253 |
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shared_ptr->combined.io_address == 0x03C0 || shared_ptr->combined.io_address == 0x03C4 || shared_ptr->combined.io_address == 0x03C8 || shared_ptr->combined.io_address == 0x03CC ||
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| 254 |
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shared_ptr->combined.io_address == 0x03D0 || shared_ptr->combined.io_address == 0x03D4 || shared_ptr->combined.io_address == 0x03D8 || shared_ptr->combined.io_address == 0x03DC))
|
| 255 |
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{
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| 256 |
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if(shared_ptr->combined.io_byteenable != 1 && shared_ptr->combined.io_byteenable != 2 && shared_ptr->combined.io_byteenable != 4 && shared_ptr->combined.io_byteenable != 8) {
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| 257 |
|
|
printf("Vvga: combined.io_byteenable invalid: %x\n", shared_ptr->combined.io_byteenable);
|
| 258 |
|
|
exit(-1);
|
| 259 |
|
|
}
|
| 260 |
|
|
|
| 261 |
|
|
top->io_b_address = (shared_ptr->combined.io_address == 0x03B0 && shared_ptr->combined.io_byteenable == 1)? 0 :
|
| 262 |
|
|
(shared_ptr->combined.io_address == 0x03B0 && shared_ptr->combined.io_byteenable == 2)? 1 :
|
| 263 |
|
|
(shared_ptr->combined.io_address == 0x03B0 && shared_ptr->combined.io_byteenable == 4)? 2 :
|
| 264 |
|
|
(shared_ptr->combined.io_address == 0x03B0 && shared_ptr->combined.io_byteenable == 8)? 3 :
|
| 265 |
|
|
(shared_ptr->combined.io_address == 0x03B4 && shared_ptr->combined.io_byteenable == 1)? 4 :
|
| 266 |
|
|
(shared_ptr->combined.io_address == 0x03B4 && shared_ptr->combined.io_byteenable == 2)? 5 :
|
| 267 |
|
|
(shared_ptr->combined.io_address == 0x03B4 && shared_ptr->combined.io_byteenable == 4)? 6 :
|
| 268 |
|
|
(shared_ptr->combined.io_address == 0x03B4 && shared_ptr->combined.io_byteenable == 8)? 7 :
|
| 269 |
|
|
(shared_ptr->combined.io_address == 0x03B8 && shared_ptr->combined.io_byteenable == 1)? 8 :
|
| 270 |
|
|
(shared_ptr->combined.io_address == 0x03B8 && shared_ptr->combined.io_byteenable == 2)? 9 :
|
| 271 |
|
|
(shared_ptr->combined.io_address == 0x03B8 && shared_ptr->combined.io_byteenable == 4)? 10 :
|
| 272 |
|
|
(shared_ptr->combined.io_address == 0x03B8 && shared_ptr->combined.io_byteenable == 8)? 11 :
|
| 273 |
|
|
(shared_ptr->combined.io_address == 0x03BC && shared_ptr->combined.io_byteenable == 1)? 12 :
|
| 274 |
|
|
(shared_ptr->combined.io_address == 0x03BC && shared_ptr->combined.io_byteenable == 2)? 13 :
|
| 275 |
|
|
(shared_ptr->combined.io_address == 0x03BC && shared_ptr->combined.io_byteenable == 4)? 14 :
|
| 276 |
|
|
15;
|
| 277 |
|
|
|
| 278 |
|
|
top->io_c_address = (shared_ptr->combined.io_address == 0x03C0 && shared_ptr->combined.io_byteenable == 1)? 0 :
|
| 279 |
|
|
(shared_ptr->combined.io_address == 0x03C0 && shared_ptr->combined.io_byteenable == 2)? 1 :
|
| 280 |
|
|
(shared_ptr->combined.io_address == 0x03C0 && shared_ptr->combined.io_byteenable == 4)? 2 :
|
| 281 |
|
|
(shared_ptr->combined.io_address == 0x03C0 && shared_ptr->combined.io_byteenable == 8)? 3 :
|
| 282 |
|
|
(shared_ptr->combined.io_address == 0x03C4 && shared_ptr->combined.io_byteenable == 1)? 4 :
|
| 283 |
|
|
(shared_ptr->combined.io_address == 0x03C4 && shared_ptr->combined.io_byteenable == 2)? 5 :
|
| 284 |
|
|
(shared_ptr->combined.io_address == 0x03C4 && shared_ptr->combined.io_byteenable == 4)? 6 :
|
| 285 |
|
|
(shared_ptr->combined.io_address == 0x03C4 && shared_ptr->combined.io_byteenable == 8)? 7 :
|
| 286 |
|
|
(shared_ptr->combined.io_address == 0x03C8 && shared_ptr->combined.io_byteenable == 1)? 8 :
|
| 287 |
|
|
(shared_ptr->combined.io_address == 0x03C8 && shared_ptr->combined.io_byteenable == 2)? 9 :
|
| 288 |
|
|
(shared_ptr->combined.io_address == 0x03C8 && shared_ptr->combined.io_byteenable == 4)? 10 :
|
| 289 |
|
|
(shared_ptr->combined.io_address == 0x03C8 && shared_ptr->combined.io_byteenable == 8)? 11 :
|
| 290 |
|
|
(shared_ptr->combined.io_address == 0x03CC && shared_ptr->combined.io_byteenable == 1)? 12 :
|
| 291 |
|
|
(shared_ptr->combined.io_address == 0x03CC && shared_ptr->combined.io_byteenable == 2)? 13 :
|
| 292 |
|
|
(shared_ptr->combined.io_address == 0x03CC && shared_ptr->combined.io_byteenable == 4)? 14 :
|
| 293 |
|
|
15;
|
| 294 |
|
|
|
| 295 |
|
|
top->io_d_address = (shared_ptr->combined.io_address == 0x03D0 && shared_ptr->combined.io_byteenable == 1)? 0 :
|
| 296 |
|
|
(shared_ptr->combined.io_address == 0x03D0 && shared_ptr->combined.io_byteenable == 2)? 1 :
|
| 297 |
|
|
(shared_ptr->combined.io_address == 0x03D0 && shared_ptr->combined.io_byteenable == 4)? 2 :
|
| 298 |
|
|
(shared_ptr->combined.io_address == 0x03D0 && shared_ptr->combined.io_byteenable == 8)? 3 :
|
| 299 |
|
|
(shared_ptr->combined.io_address == 0x03D4 && shared_ptr->combined.io_byteenable == 1)? 4 :
|
| 300 |
|
|
(shared_ptr->combined.io_address == 0x03D4 && shared_ptr->combined.io_byteenable == 2)? 5 :
|
| 301 |
|
|
(shared_ptr->combined.io_address == 0x03D4 && shared_ptr->combined.io_byteenable == 4)? 6 :
|
| 302 |
|
|
(shared_ptr->combined.io_address == 0x03D4 && shared_ptr->combined.io_byteenable == 8)? 7 :
|
| 303 |
|
|
(shared_ptr->combined.io_address == 0x03D8 && shared_ptr->combined.io_byteenable == 1)? 8 :
|
| 304 |
|
|
(shared_ptr->combined.io_address == 0x03D8 && shared_ptr->combined.io_byteenable == 2)? 9 :
|
| 305 |
|
|
(shared_ptr->combined.io_address == 0x03D8 && shared_ptr->combined.io_byteenable == 4)? 10 :
|
| 306 |
|
|
(shared_ptr->combined.io_address == 0x03D8 && shared_ptr->combined.io_byteenable == 8)? 11 :
|
| 307 |
|
|
(shared_ptr->combined.io_address == 0x03DC && shared_ptr->combined.io_byteenable == 1)? 12 :
|
| 308 |
|
|
(shared_ptr->combined.io_address == 0x03DC && shared_ptr->combined.io_byteenable == 2)? 13 :
|
| 309 |
|
|
(shared_ptr->combined.io_address == 0x03DC && shared_ptr->combined.io_byteenable == 4)? 14 :
|
| 310 |
|
|
15;
|
| 311 |
|
|
|
| 312 |
|
|
|
| 313 |
|
|
top->io_b_writedata = 0;
|
| 314 |
|
|
top->io_c_writedata = 0;
|
| 315 |
|
|
top->io_d_writedata = 0;
|
| 316 |
|
|
|
| 317 |
|
|
if(shared_ptr->combined.io_address == 0x03B0 || shared_ptr->combined.io_address == 0x03B4 || shared_ptr->combined.io_address == 0x03B8 || shared_ptr->combined.io_address == 0x03BC) {
|
| 318 |
|
|
top->io_b_read = 1;
|
| 319 |
|
|
top->io_b_write = 0;
|
| 320 |
|
|
}
|
| 321 |
|
|
if(shared_ptr->combined.io_address == 0x03C0 || shared_ptr->combined.io_address == 0x03C4 || shared_ptr->combined.io_address == 0x03C8 || shared_ptr->combined.io_address == 0x03CC) {
|
| 322 |
|
|
top->io_c_read = 1;
|
| 323 |
|
|
top->io_c_write = 0;
|
| 324 |
|
|
}
|
| 325 |
|
|
if(shared_ptr->combined.io_address == 0x03D0 || shared_ptr->combined.io_address == 0x03D4 || shared_ptr->combined.io_address == 0x03D8 || shared_ptr->combined.io_address == 0x03DC) {
|
| 326 |
|
|
top->io_d_read = 1;
|
| 327 |
|
|
top->io_d_write = 0;
|
| 328 |
|
|
}
|
| 329 |
|
|
|
| 330 |
|
|
read_cycle = true;
|
| 331 |
|
|
}
|
| 332 |
|
|
}
|
| 333 |
|
|
else {
|
| 334 |
|
|
if(shared_ptr->combined.io_step == STEP_REQ && shared_ptr->combined.io_is_write == 0 &&
|
| 335 |
|
|
(shared_ptr->combined.io_address == 0x03B0 || shared_ptr->combined.io_address == 0x03B4 || shared_ptr->combined.io_address == 0x03B8 || shared_ptr->combined.io_address == 0x03BC ||
|
| 336 |
|
|
shared_ptr->combined.io_address == 0x03C0 || shared_ptr->combined.io_address == 0x03C4 || shared_ptr->combined.io_address == 0x03C8 || shared_ptr->combined.io_address == 0x03CC ||
|
| 337 |
|
|
shared_ptr->combined.io_address == 0x03D0 || shared_ptr->combined.io_address == 0x03D4 || shared_ptr->combined.io_address == 0x03D8 || shared_ptr->combined.io_address == 0x03DC))
|
| 338 |
|
|
{
|
| 339 |
|
|
uint32 val = 0;
|
| 340 |
|
|
|
| 341 |
|
|
if(shared_ptr->combined.io_address == 0x03B0 || shared_ptr->combined.io_address == 0x03B4 || shared_ptr->combined.io_address == 0x03B8 || shared_ptr->combined.io_address == 0x03BC) {
|
| 342 |
|
|
val = top->io_b_readdata;
|
| 343 |
|
|
}
|
| 344 |
|
|
if(shared_ptr->combined.io_address == 0x03C0 || shared_ptr->combined.io_address == 0x03C4 || shared_ptr->combined.io_address == 0x03C8 || shared_ptr->combined.io_address == 0x03CC) {
|
| 345 |
|
|
val = top->io_c_readdata;
|
| 346 |
|
|
}
|
| 347 |
|
|
if(shared_ptr->combined.io_address == 0x03D0 || shared_ptr->combined.io_address == 0x03D4 || shared_ptr->combined.io_address == 0x03D8 || shared_ptr->combined.io_address == 0x03DC) {
|
| 348 |
|
|
val = top->io_d_readdata;
|
| 349 |
|
|
}
|
| 350 |
|
|
|
| 351 |
|
|
if(shared_ptr->combined.io_byteenable & 1) val <<= 0;
|
| 352 |
|
|
if(shared_ptr->combined.io_byteenable & 2) val <<= 8;
|
| 353 |
|
|
if(shared_ptr->combined.io_byteenable & 4) val <<= 16;
|
| 354 |
|
|
if(shared_ptr->combined.io_byteenable & 8) val <<= 24;
|
| 355 |
|
|
|
| 356 |
|
|
shared_ptr->combined.io_data = val;
|
| 357 |
|
|
|
| 358 |
|
|
read_cycle = false;
|
| 359 |
|
|
shared_ptr->combined.io_step = STEP_ACK;
|
| 360 |
|
|
}
|
| 361 |
|
|
}
|
| 362 |
|
|
|
| 363 |
|
|
//----------------------------------------------------------------------
|
| 364 |
|
|
/*
|
| 365 |
|
|
uint32 combined.mem_address;
|
| 366 |
|
|
uint32 combined.mem_data;
|
| 367 |
|
|
uint32 combined.mem_byteenable;
|
| 368 |
|
|
uint32 combined.mem_is_write;
|
| 369 |
|
|
step_t combined.mem_step;
|
| 370 |
|
|
|
| 371 |
|
|
//avalon slave vga memory 0xA0000 - 0xBFFFF
|
| 372 |
|
|
input [16:0] mem_address,
|
| 373 |
|
|
input mem_read,
|
| 374 |
|
|
output [7:0] mem_readdata,
|
| 375 |
|
|
input mem_write,
|
| 376 |
|
|
input [7:0] mem_writedata,
|
| 377 |
|
|
*/
|
| 378 |
|
|
|
| 379 |
|
|
if(shared_ptr->combined.mem_step == STEP_REQ && shared_ptr->combined.mem_is_write && shared_ptr->combined.mem_address >= 0x000A0000 && shared_ptr->combined.mem_address < 0x000C0000)
|
| 380 |
|
|
{
|
| 381 |
|
|
if(curr_mem_step == STEP_IDLE) {
|
| 382 |
|
|
curr_mem_byteena_modif = shared_ptr->combined.mem_byteenable;
|
| 383 |
|
|
curr_mem_step = STEP_REQ;
|
| 384 |
|
|
}
|
| 385 |
|
|
|
| 386 |
|
|
if(curr_mem_step == STEP_REQ) {
|
| 387 |
|
|
if((curr_mem_byteena_modif >> 0) & 1) {
|
| 388 |
|
|
curr_mem_byteenable = 1;
|
| 389 |
|
|
curr_mem_byteena_modif &= 0xE;
|
| 390 |
|
|
}
|
| 391 |
|
|
else if((curr_mem_byteena_modif >> 1) & 1) {
|
| 392 |
|
|
curr_mem_byteenable = 2;
|
| 393 |
|
|
curr_mem_byteena_modif &= 0xC;
|
| 394 |
|
|
}
|
| 395 |
|
|
else if((curr_mem_byteena_modif >> 2) & 1) {
|
| 396 |
|
|
curr_mem_byteenable = 4;
|
| 397 |
|
|
curr_mem_byteena_modif &= 0x8;
|
| 398 |
|
|
}
|
| 399 |
|
|
else if((curr_mem_byteena_modif >> 3) & 1) {
|
| 400 |
|
|
curr_mem_byteenable = 8;
|
| 401 |
|
|
curr_mem_byteena_modif &= 0x0;
|
| 402 |
|
|
}
|
| 403 |
|
|
else {
|
| 404 |
|
|
shared_ptr->combined.mem_step = STEP_ACK;
|
| 405 |
|
|
curr_mem_step = STEP_IDLE;
|
| 406 |
|
|
}
|
| 407 |
|
|
}
|
| 408 |
|
|
}
|
| 409 |
|
|
|
| 410 |
|
|
top->mem_read = 0;
|
| 411 |
|
|
top->mem_write = 0;
|
| 412 |
|
|
|
| 413 |
|
|
if(shared_ptr->combined.mem_step == STEP_REQ && shared_ptr->combined.mem_is_write && shared_ptr->combined.mem_address >= 0x000A0000 && shared_ptr->combined.mem_address < 0x000C0000 &&
|
| 414 |
|
|
curr_mem_step == STEP_REQ)
|
| 415 |
|
|
{
|
| 416 |
|
|
if(curr_mem_byteenable != 1 && curr_mem_byteenable != 2 && curr_mem_byteenable != 4 && curr_mem_byteenable != 8) {
|
| 417 |
|
|
printf("Vvga: combined.curr_mem_byteenable invalid wr: %x\n", curr_mem_byteenable);
|
| 418 |
|
|
exit(-1);
|
| 419 |
|
|
}
|
| 420 |
|
|
|
| 421 |
|
|
top->mem_address = (shared_ptr->combined.mem_address >> 2) & 0x1FFFF;
|
| 422 |
|
|
|
| 423 |
|
|
top->mem_writedata = (curr_mem_byteenable == 1)? shared_ptr->combined.mem_data & 0xFF :
|
| 424 |
|
|
(curr_mem_byteenable == 2)? (shared_ptr->combined.mem_data >> 8) & 0xFF :
|
| 425 |
|
|
(curr_mem_byteenable == 4)? (shared_ptr->combined.mem_data >> 16) & 0xFF :
|
| 426 |
|
|
(shared_ptr->combined.mem_data >> 24) & 0xFF;
|
| 427 |
|
|
top->mem_read = 0;
|
| 428 |
|
|
top->mem_write = 1;
|
| 429 |
|
|
}
|
| 430 |
|
|
|
| 431 |
|
|
if(read_mem_cycle == false) {
|
| 432 |
|
|
|
| 433 |
|
|
if(shared_ptr->combined.mem_step == STEP_REQ && shared_ptr->combined.mem_is_write == 0 && shared_ptr->combined.mem_address >= 0x000A0000 && shared_ptr->combined.mem_address < 0x000C0000)
|
| 434 |
|
|
{
|
| 435 |
|
|
if(curr_mrd_step == STEP_IDLE) {
|
| 436 |
|
|
curr_mrd_byteena_modif = shared_ptr->combined.mem_byteenable;
|
| 437 |
|
|
curr_mrd_step = STEP_REQ;
|
| 438 |
|
|
|
| 439 |
|
|
shared_ptr->combined.mem_data = 0;
|
| 440 |
|
|
}
|
| 441 |
|
|
|
| 442 |
|
|
if(curr_mrd_step == STEP_REQ) {
|
| 443 |
|
|
if((curr_mrd_byteena_modif >> 0) & 1) {
|
| 444 |
|
|
curr_mrd_byteenable = 1;
|
| 445 |
|
|
curr_mrd_byteena_modif &= 0xE;
|
| 446 |
|
|
}
|
| 447 |
|
|
else if((curr_mrd_byteena_modif >> 1) & 1) {
|
| 448 |
|
|
curr_mrd_byteenable = 2;
|
| 449 |
|
|
curr_mrd_byteena_modif &= 0xC;
|
| 450 |
|
|
}
|
| 451 |
|
|
else if((curr_mrd_byteena_modif >> 2) & 1) {
|
| 452 |
|
|
curr_mrd_byteenable = 4;
|
| 453 |
|
|
curr_mrd_byteena_modif &= 0x8;
|
| 454 |
|
|
}
|
| 455 |
|
|
else if((curr_mrd_byteena_modif >> 3) & 1) {
|
| 456 |
|
|
curr_mrd_byteenable = 8;
|
| 457 |
|
|
curr_mrd_byteena_modif &= 0x0;
|
| 458 |
|
|
}
|
| 459 |
|
|
else {
|
| 460 |
|
|
shared_ptr->combined.mem_step = STEP_ACK;
|
| 461 |
|
|
curr_mrd_step = STEP_IDLE;
|
| 462 |
|
|
}
|
| 463 |
|
|
}
|
| 464 |
|
|
}
|
| 465 |
|
|
|
| 466 |
|
|
if(shared_ptr->combined.mem_step == STEP_REQ && shared_ptr->combined.mem_is_write == 0 && shared_ptr->combined.mem_address >= 0x000A0000 && shared_ptr->combined.mem_address < 0x000C0000 &&
|
| 467 |
|
|
curr_mrd_step == STEP_REQ)
|
| 468 |
|
|
{
|
| 469 |
|
|
if(curr_mrd_byteenable != 1 && curr_mrd_byteenable != 2 && curr_mrd_byteenable != 4 && curr_mrd_byteenable != 8) {
|
| 470 |
|
|
printf("Vvga: curr_mrd_byteenable invalid rd: %x\n", curr_mrd_byteenable);
|
| 471 |
|
|
exit(-1);
|
| 472 |
|
|
}
|
| 473 |
|
|
|
| 474 |
|
|
top->mem_address = (shared_ptr->combined.mem_address >> 2) & 0x1FFFF;
|
| 475 |
|
|
|
| 476 |
|
|
top->mem_writedata = 0;
|
| 477 |
|
|
|
| 478 |
|
|
top->mem_read = 1;
|
| 479 |
|
|
top->mem_write= 0;
|
| 480 |
|
|
|
| 481 |
|
|
read_mem_cycle = true;
|
| 482 |
|
|
}
|
| 483 |
|
|
}
|
| 484 |
|
|
else {
|
| 485 |
|
|
if(shared_ptr->combined.mem_step == STEP_REQ && shared_ptr->combined.mem_is_write == 0 && shared_ptr->combined.mem_address >= 0x000A0000 && shared_ptr->combined.mem_address < 0x000C0000 &&
|
| 486 |
|
|
curr_mrd_step == STEP_REQ)
|
| 487 |
|
|
{
|
| 488 |
|
|
uint32 val = top->mem_readdata;
|
| 489 |
|
|
|
| 490 |
|
|
if(curr_mrd_byteenable & 1) val <<= 0;
|
| 491 |
|
|
if(curr_mrd_byteenable & 2) val <<= 8;
|
| 492 |
|
|
if(curr_mrd_byteenable & 4) val <<= 16;
|
| 493 |
|
|
if(curr_mrd_byteenable & 8) val <<= 24;
|
| 494 |
|
|
|
| 495 |
|
|
shared_ptr->combined.mem_data |= val;
|
| 496 |
|
|
|
| 497 |
|
|
read_mem_cycle = false;
|
| 498 |
|
|
}
|
| 499 |
|
|
}
|
| 500 |
|
|
|
| 501 |
|
|
//----------------------------------------------------------------------
|
| 502 |
|
|
|
| 503 |
|
|
//----------------------------------------------------------------------
|
| 504 |
|
|
|
| 505 |
|
|
top->clk_26 = 0;
|
| 506 |
|
|
top->eval();
|
| 507 |
|
|
if(dump) tracer->dump(cycle++);
|
| 508 |
|
|
|
| 509 |
|
|
top->clk_26 = 1;
|
| 510 |
|
|
top->eval();
|
| 511 |
|
|
if(dump) tracer->dump(cycle++);
|
| 512 |
|
|
|
| 513 |
|
|
tracer->flush();
|
| 514 |
|
|
|
| 515 |
|
|
usleep(1);
|
| 516 |
|
|
}
|
| 517 |
|
|
tracer->close();
|
| 518 |
|
|
delete tracer;
|
| 519 |
|
|
delete top;
|
| 520 |
|
|
|
| 521 |
|
|
return 0;
|
| 522 |
|
|
}
|
| 523 |
|
|
|
| 524 |
|
|
//------------------------------------------------------------------------------
|
| 525 |
|
|
|
| 526 |
|
|
/*
|
| 527 |
|
|
input clk_26,
|
| 528 |
|
|
input rst_n,
|
| 529 |
|
|
|
| 530 |
|
|
//avalon slave for system overlay
|
| 531 |
|
|
input [7:0] sys_address,
|
| 532 |
|
|
input sys_read,
|
| 533 |
|
|
output [31:0] sys_readdata,
|
| 534 |
|
|
input sys_write,
|
| 535 |
|
|
input [31:0] sys_writedata,
|
| 536 |
|
|
|
| 537 |
|
|
//avalon slave vga io 0x3B0 - 0x3BF
|
| 538 |
|
|
input [3:0] io_b_address,
|
| 539 |
|
|
input io_b_read,
|
| 540 |
|
|
output [7:0] io_b_readdata,
|
| 541 |
|
|
input io_b_write,
|
| 542 |
|
|
input [7:0] io_b_writedata,
|
| 543 |
|
|
|
| 544 |
|
|
//avalon slave vga io 0x3C0 - 0xCF
|
| 545 |
|
|
input [3:0] io_c_address,
|
| 546 |
|
|
input io_c_read,
|
| 547 |
|
|
output [7:0] io_c_readdata,
|
| 548 |
|
|
input io_c_write,
|
| 549 |
|
|
input [7:0] io_c_writedata,
|
| 550 |
|
|
|
| 551 |
|
|
//avalon slave vga io 0x3D0 - 0x3DF
|
| 552 |
|
|
input [3:0] io_d_address,
|
| 553 |
|
|
input io_d_read,
|
| 554 |
|
|
output [7:0] io_d_readdata,
|
| 555 |
|
|
input io_d_write,
|
| 556 |
|
|
input [7:0] io_d_writedata,
|
| 557 |
|
|
|
| 558 |
|
|
//avalon slave vga memory 0xA0000 - 0xBFFFF
|
| 559 |
|
|
input [16:0] mem_address,
|
| 560 |
|
|
input mem_read,
|
| 561 |
|
|
output [7:0] mem_readdata,
|
| 562 |
|
|
input mem_write,
|
| 563 |
|
|
input [7:0] mem_writedata,
|
| 564 |
|
|
*/
|
