Subversion Repositories ao486

# -------------------------------------------------------------------------- #

#

# Copyright (C) 1991-2013 Altera Corporation

# Your use of Altera Corporation's design tools, logic functions

# and other software and tools, and its AMPP partner logic

# functions, and any output files from any of the foregoing

# (including device programming or simulation files), and any

# associated documentation or information are expressly subject

# to the terms and conditions of the Altera Program License

# Subscription Agreement, Altera MegaCore Function License

# Agreement, or other applicable license agreement, including,

# without limitation, that your use is for the sole purpose of

# programming logic devices manufactured by Altera and sold by

# Altera or its authorized distributors.  Please refer to the

# applicable agreement for further details.

#

# -------------------------------------------------------------------------- #

#

# Quartus II 64-Bit

# Version 13.0.0 Build 156 04/24/2013 SJ Web Edition

# Date created = 20:56:54  May 11, 2013

#

# -------------------------------------------------------------------------- #

#

# Notes:

#

# 1) The default values for assignments are stored in the file:

#               memory_assignment_defaults.qdf

#    If this file doesn't exist, see file:

#               assignment_defaults.qdf

#

# 2) Altera recommends that you do not modify this file. This

#    file is updated automatically by the Quartus II software

#    and any changes you make may be lost or overwritten.

#

# -------------------------------------------------------------------------- #

set_global_assignment -name FAMILY "Cyclone IV E"

set_global_assignment -name DEVICE EP4CE115F29C7

set_global_assignment -name TOP_LEVEL_ENTITY memory

set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.0

set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:56:54  MAY 11, 2013"

set_global_assignment -name LAST_QUARTUS_VERSION 13.0

set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files

set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0

set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1

set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V

set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top

set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

set_global_assignment -name SEARCH_PATH /home/alek/aktualne/ao486/rtl

set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"

set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"

set_global_assignment -name VERILOG_FILE ../../rtl/altera/altera_prefetch_fifo.v

set_global_assignment -name VERILOG_FILE ../../rtl/altera/altera_icache_control_ram.v

set_global_assignment -name VERILOG_FILE ../../rtl/altera/altera_dcache_to_icache_fifo.v

set_global_assignment -name VERILOG_FILE ../../rtl/altera/altera_dcache_control_ram.v

set_global_assignment -name VERILOG_FILE ../../rtl/altera/altera_cache_data_ram.v

set_global_assignment -name VERILOG_FILE ../../rtl/memory/tlb_regs.v

set_global_assignment -name VERILOG_FILE ../../rtl/memory/tlb_memtype.v

set_global_assignment -name VERILOG_FILE ../../rtl/memory/tlb.v

set_global_assignment -name VERILOG_FILE ../../rtl/memory/prefetch_fifo.v

set_global_assignment -name VERILOG_FILE ../../rtl/memory/prefetch_control.v

set_global_assignment -name VERILOG_FILE ../../rtl/memory/prefetch.v

set_global_assignment -name VERILOG_FILE ../../rtl/memory/memory_write.v

set_global_assignment -name VERILOG_FILE ../../rtl/memory/memory_read.v

set_global_assignment -name VERILOG_FILE ../../rtl/memory/memory.v

set_global_assignment -name VERILOG_FILE ../../rtl/memory/link_writeline.v

set_global_assignment -name VERILOG_FILE ../../rtl/memory/link_writeburst.v

set_global_assignment -name VERILOG_FILE ../../rtl/memory/link_readline.v

set_global_assignment -name VERILOG_FILE ../../rtl/memory/link_readcode.v

set_global_assignment -name VERILOG_FILE ../../rtl/memory/link_readburst.v

set_global_assignment -name VERILOG_FILE ../../rtl/memory/link_dcachewrite.v

set_global_assignment -name VERILOG_FILE ../../rtl/memory/link_dcacheread.v

set_global_assignment -name VERILOG_FILE ../../rtl/memory/icache_read.v

set_global_assignment -name VERILOG_FILE ../../rtl/memory/icache_matched.v

set_global_assignment -name VERILOG_FILE ../../rtl/memory/icache_control_ram.v

set_global_assignment -name VERILOG_FILE ../../rtl/memory/icache.v

set_global_assignment -name VERILOG_FILE ../../rtl/memory/dcache_write.v

set_global_assignment -name VERILOG_FILE ../../rtl/memory/dcache_to_icache_fifo.v

set_global_assignment -name VERILOG_FILE ../../rtl/memory/dcache_read.v

set_global_assignment -name VERILOG_FILE ../../rtl/memory/dcache_matched.v

set_global_assignment -name VERILOG_FILE ../../rtl/memory/dcache_control_ram.v

set_global_assignment -name VERILOG_FILE ../../rtl/memory/dcache.v

set_global_assignment -name VERILOG_FILE ../../rtl/memory/cache_data_ram.v

set_global_assignment -name VERILOG_FILE ../../rtl/memory/avalon_mem.v

set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top