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# -------------------------------------------------------------------------- #

#

# Copyright (C) 1991-2013 Altera Corporation

# Your use of Altera Corporation's design tools, logic functions

# and other software and tools, and its AMPP partner logic

# functions, and any output files from any of the foregoing

# (including device programming or simulation files), and any

# associated documentation or information are expressly subject

# to the terms and conditions of the Altera Program License

# Subscription Agreement, Altera MegaCore Function License

# Agreement, or other applicable license agreement, including,

# without limitation, that your use is for the sole purpose of

# programming logic devices manufactured by Altera and sold by

# Altera or its authorized distributors.  Please refer to the

# applicable agreement for further details.

#

# -------------------------------------------------------------------------- #

#

# Quartus II 64-Bit

# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition

# Date created = 10:40:12  October 29, 2013

#

# -------------------------------------------------------------------------- #

#

# Notes:

#

# 1) The default values for assignments are stored in the file:

#               sound_soc_assignment_defaults.qdf

#    If this file doesn't exist, see file:

#               assignment_defaults.qdf

#

# 2) Altera recommends that you do not modify this file. This

#    file is updated automatically by the Quartus II software

#    and any changes you make may be lost or overwritten.

#

# -------------------------------------------------------------------------- #

set_global_assignment -name FAMILY "Cyclone IV E"

set_global_assignment -name DEVICE EP4CE115F29C7

set_global_assignment -name TOP_LEVEL_ENTITY sound_soc

set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"

set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:40:12  OCTOBER 29, 2013"

set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"

set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files

set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0

set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1

set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V

set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50

set_location_assignment PIN_Y2 -to CLOCK_50

set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCLRCK

set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCDAT

set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACLRCK

set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACDAT

set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_XCK

set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_BCLK

set_location_assignment PIN_D1 -to AUD_DACDAT

set_location_assignment PIN_E3 -to AUD_DACLRCK

set_location_assignment PIN_D2 -to AUD_ADCDAT

set_location_assignment PIN_C2 -to AUD_ADCLRCK

set_location_assignment PIN_E1 -to AUD_XCK

set_location_assignment PIN_F2 -to AUD_BCLK

set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK

set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT

set_location_assignment PIN_B7 -to I2C_SCLK

set_location_assignment PIN_A8 -to I2C_SDAT

set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top

set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

set_global_assignment -name QIP_FILE soc/synthesis/soc.qip

set_global_assignment -name VERILOG_FILE ../altera_waveform_rom.v

set_global_assignment -name VERILOG_FILE ../altera_sample_fifo.v

set_global_assignment -name VERILOG_FILE ../altera_period_ram.v

set_global_assignment -name VERILOG_FILE ../altera_operator_mult.v

set_global_assignment -name VERILOG_FILE ../altera_attack_rom.v

set_global_assignment -name VERILOG_FILE ../sound_opl2.v

set_global_assignment -name VERILOG_FILE ../sound_dsp.v

set_global_assignment -name VERILOG_FILE ../sound.v

set_global_assignment -name VERILOG_FILE pll.v

set_global_assignment -name VERILOG_FILE sound_soc.v

set_global_assignment -name SDC_FILE sound_soc.sdc

set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top