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//////////////////////////////////////////////////////////////////
////
////
////    TOP I2C BLOCK to I2C Core
////
////
////
//// This file is part of the APB to I2C project
////
//// http://www.opencores.org/cores/apbi2c/
////
////
////
//// Description
////
//// Implementation of APB IP core according to
////
//// apbi2c_spec IP core specification document.
////
////
////
//// To Do: Things are right here but always all block can suffer changes
////
////
////
////
////
//// Author(s): - Felipe Fernandes Da Costa, fefe2560@gmail.com
////              Ronal Dario Celaya ,rcelaya.dario@gmail.com
////
///////////////////////////////////////////////////////////////// 
////
////
//// Copyright (C) 2009 Authors and OPENCORES.ORG
////
////
////
//// This source file may be used and distributed without
////
//// restriction provided that this copyright statement is not
////
//// removed from the file and that any derivative work contains
//// the original copyright notice and the associated disclaimer.
////
////
//// This source file is free software; you can redistribute it
////
//// and/or modify it under the terms of the GNU Lesser General
////
//// Public License as published by the Free Software Foundation;
//// either version 2.1 of the License, or (at your option) any
////
//// later version.
////
////
////
//// This source is distributed in the hope that it will be
////
//// useful, but WITHOUT ANY WARRANTY; without even the implied
////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
////
//// PURPOSE. See the GNU Lesser General Public License for more
//// details.
////
////
////
//// You should have received a copy of the GNU Lesser General
////
//// Public License along with this source; if not, download it
////
//// from http://www.opencores.org/lgpl.shtml
////
////
///////////////////////////////////////////////////////////////////
 
 
`timescale 1ns/1ps //timescale 
 
module module_i2c#(
                        //THIS IS USED ONLY LIKE PARAMETER TO BEM CONFIGURABLE
                        parameter integer DWIDTH = 32,
                        parameter integer AWIDTH = 14
                )
                (
                //I2C INTERFACE WITH ANOTHER BLOCKS
                 input PCLK,
                 input PRESETn,
 
                //INTERFACE WITH FIFO TRANSMISSION
                 input fifo_tx_f_full,
                 input fifo_tx_f_empty,
                 input [DWIDTH-1:0] fifo_tx_data_out,
 
                //INTERFACE WITH FIFO RECEIVER
                 input fifo_rx_f_full,
                 input fifo_rx_f_empty,
                 output reg fifo_rx_wr_en,
                 output reg [DWIDTH-1:0] fifo_rx_data_in,
 
                //INTERFACE WITH REGISTER CONFIGURATION
                 input [AWIDTH-1:0] DATA_CONFIG_REG,
                 input [AWIDTH-1:0] TIMEOUT_TX,
 
                //INTERFACE TO APB AND READ FOR FIFO   
                 output reg fifo_tx_rd_en,
                 output   TX_EMPTY,
                 output   RX_EMPTY,
                 output ERROR,
                 output ENABLE_SDA,
                 output ENABLE_SCL,
 
                //I2C BI DIRETIONAL PORTS
                inout SDA,
                inout SCL
 
 
                 );
 
//THIS IS USED TO GENERATE INTERRUPTIONS
assign TX_EMPTY = (fifo_tx_f_empty == 1'b1)? 1'b1:1'b0;
assign RX_EMPTY = (fifo_rx_f_empty == 1'b1)? 1'b1:1'b0;
 
        //THIS COUNT IS USED TO CONTROL DATA ACCROSS FSM        
        reg [1:0] count_tx;
        reg [1:0] count_rx;
        //CONTROL CLOCK AND COUNTER
        reg [11:0] count_send_data;
        reg [11:0] count_receive_data;
        reg [11:0] count_timeout;
        reg BR_CLK_O;
        reg SDA_OUT;
 
        reg BR_CLK_O_RX;
        reg SDA_OUT_RX;
 
        //RESPONSE USED TO HOLD SIGNAL TO ACK OR NACK
        reg RESPONSE;
 
//    PARAMETERS USED TO STATE MACHINE
 
localparam [5:0] IDLE = 6'd0, //IDLE
 
           START = 6'd1,//START BIT
 
             CONTROLIN_1 = 6'd2, //START BYTE
             CONTROLIN_2 = 6'd3,
             CONTROLIN_3 = 6'd4,
             CONTROLIN_4 = 6'd5,
             CONTROLIN_5 = 6'd6,
             CONTROLIN_6 = 6'd7,
             CONTROLIN_7 = 6'd8,
             CONTROLIN_8 = 6'd9, //END FIRST BYTE
 
             RESPONSE_CIN =6'd10, //RESPONSE
 
             ADDRESS_1 = 6'd11,//START BYTE
             ADDRESS_2 = 6'd12,
             ADDRESS_3 = 6'd13,
             ADDRESS_4 = 6'd14,
             ADDRESS_5 = 6'd15,
             ADDRESS_6 = 6'd16,
             ADDRESS_7 = 6'd17,
             ADDRESS_8 = 6'd18,//END FIRST BYTE
 
             RESPONSE_ADDRESS =6'd19, //RESPONSE
 
             DATA0_1 = 6'd20,//START BYTE
             DATA0_2 = 6'd21,
             DATA0_3 = 6'd22,
             DATA0_4 = 6'd23,
             DATA0_5 = 6'd24,
             DATA0_6 = 6'd25,
             DATA0_7 = 6'd26,
             DATA0_8 = 6'd27,//END FIRST BYTE
 
             RESPONSE_DATA0_1 = 6'd28,  //RESPONSE
 
             DATA1_1 = 6'd29,//START BYTE
             DATA1_2 = 6'd30,
             DATA1_3 = 6'd31,
             DATA1_4 = 6'd32,
             DATA1_5 = 6'd33,
             DATA1_6 = 6'd34,
             DATA1_7 = 6'd35,
             DATA1_8 = 6'd36,//END FIRST BYTE
 
             RESPONSE_DATA1_1 = 6'd37,//RESPONSE
 
             DELAY_BYTES = 6'd38,//USED ONLY IN ACK TO DELAY BETWEEN
             NACK = 6'd39,//USED ONLY IN ACK TO DELAY BETWEEN BYTES
             STOP = 6'd40;//USED TO SEND STOP BIT
 
        //STATE CONTROL 
        reg [5:0] state_tx;
        reg [5:0] next_state_tx;
 
//ASSIGN REGISTERS TO BIDIRETIONAL PORTS
assign SDA =(DATA_CONFIG_REG[0] == 1'b1 & DATA_CONFIG_REG[1] == 1'b0 & state_tx != RESPONSE_CIN & state_tx != RESPONSE_ADDRESS & state_tx != RESPONSE_DATA0_1 & state_tx != RESPONSE_DATA1_1)?SDA_OUT:SDA_OUT_RX;
 
 
assign SCL = (DATA_CONFIG_REG[0] == 1'b1 & DATA_CONFIG_REG[1] == 1'b0)?BR_CLK_O:BR_CLK_O_RX;
 
//STANDARD ERROR
assign ERROR = (DATA_CONFIG_REG[0] == 1'b1 & DATA_CONFIG_REG[1] == 1'b1)?1'b1:1'b0;
 
 
//COMBINATIONAL BLOCK TO   
always@(*)
begin
 
        //THE FUN START HERE :-)
        //COMBINATIONAL UPDATE STATE BE CAREFUL WITH WHAT YOU MAKE HERE
        next_state_tx=state_tx;
 
        case(state_tx)//state_   IS MORE SECURE CHANGE ONLY IF YOU KNOW WHAT ARE YOU DOING 
        IDLE:
        begin
                //OBEYING SPEC
                if(DATA_CONFIG_REG[0] == 1'b0 && (fifo_tx_f_full == 1'b1 || fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b0)
                begin
                        next_state_tx   = IDLE;
                end
                else if(DATA_CONFIG_REG[0] == 1'b1 && (fifo_tx_f_full == 1'b1 || fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b1)
                begin
                        next_state_tx   = IDLE;
                end
                else if(DATA_CONFIG_REG[0] == 1'b1 && ((fifo_tx_f_full == 1'b0 && fifo_tx_f_empty == 1'b0) || fifo_tx_f_full == 1'b1) && DATA_CONFIG_REG[1] == 1'b0 && count_timeout < TIMEOUT_TX)
                begin
                        next_state_tx   = START;
                end
 
 
        end
        START://THIS IS USED TOO ALL STATE MACHINES THE COUNTER_SEND_DATA
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx   = START;
                end
                else
                begin
                        next_state_tx   = CONTROLIN_1;
                end
 
        end
        CONTROLIN_1:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx  = CONTROLIN_1;
                end
                else
                begin
                        next_state_tx  =  CONTROLIN_2;
                end
 
        end
        CONTROLIN_2:
        begin
 
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx   = CONTROLIN_2;
                end
                else
                begin
                        next_state_tx   = CONTROLIN_3;
                end
 
        end
        CONTROLIN_3:
        begin
 
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx  =  CONTROLIN_3;
                end
                else
                begin
                        next_state_tx   = CONTROLIN_4;
                end
        end
        CONTROLIN_4:
        begin
 
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx   = CONTROLIN_4;
                end
                else
                begin
                        next_state_tx   = CONTROLIN_5;
                end
        end
        CONTROLIN_5:
        begin
 
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx = CONTROLIN_5;
                end
                else
                begin
                        next_state_tx = CONTROLIN_6;
                end
        end
        CONTROLIN_6:
        begin
 
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx = CONTROLIN_6;
                end
                else
                begin
                        next_state_tx = CONTROLIN_7;
                end
        end
        CONTROLIN_7:
        begin
 
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx = CONTROLIN_7;
                end
                else
                begin
                        next_state_tx = CONTROLIN_8;
                end
        end
        CONTROLIN_8:
        begin
 
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx  = CONTROLIN_8;
                end
                else
                begin
                        next_state_tx  = RESPONSE_CIN;
                end
        end
        RESPONSE_CIN:
        begin
 
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx = RESPONSE_CIN;
                end
                else if(RESPONSE == 1'b0)//ACK
                begin
                        next_state_tx = DELAY_BYTES;
                end
                else if(RESPONSE == 1'b1)//NACK
                begin
                        next_state_tx = NACK;
                end
 
        end
 
        //NOW SENDING ADDRESS
        ADDRESS_1:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx  = ADDRESS_1;
                end
                else
                begin
                        next_state_tx  =  ADDRESS_2;
                end
        end
        ADDRESS_2:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx = ADDRESS_2;
                end
                else
                begin
                        next_state_tx = ADDRESS_3;
                end
        end
        ADDRESS_3:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx = ADDRESS_3;
                end
                else
                begin
                        next_state_tx = ADDRESS_4;
                end
        end
        ADDRESS_4:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx = ADDRESS_4;
                end
                else
                begin
                        next_state_tx = ADDRESS_5;
                end
        end
        ADDRESS_5:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx = ADDRESS_5;
                end
                else
                begin
                        next_state_tx = ADDRESS_6;
                end
        end
        ADDRESS_6:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx = ADDRESS_6;
                end
                else
                begin
                        next_state_tx = ADDRESS_7;
                end
        end
        ADDRESS_7:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx = ADDRESS_7;
                end
                else
                begin
                        next_state_tx = ADDRESS_8;
                end
        end
        ADDRESS_8:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx = ADDRESS_8;
                end
                else
                begin
                        next_state_tx = RESPONSE_ADDRESS;
                end
        end
        RESPONSE_ADDRESS:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx = RESPONSE_ADDRESS;
                end
                else if(RESPONSE == 1'b0)//ACK
                begin
                        next_state_tx = DELAY_BYTES;
                end
                else if(RESPONSE == 1'b1)//NACK --> RESTART CONDITION AND BACK TO START BYTE AGAIN
                begin
                        next_state_tx = NACK;
                end
        end
 
        //data in
        DATA0_1:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx = DATA0_1;
                end
                else
                begin
                        next_state_tx = DATA0_2;
                end
        end
        DATA0_2:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx = DATA0_2;
                end
                else
                begin
                        next_state_tx = DATA0_3;
                end
        end
        DATA0_3:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx = DATA0_3;
                end
                else
                begin
                        next_state_tx = DATA0_4;
                end
        end
        DATA0_4:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx = DATA0_4;
                end
                else
                begin
                        next_state_tx = DATA0_5;
                end
        end
        DATA0_5:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx = DATA0_5;
                end
                else
                begin
                        next_state_tx   = DATA0_6;
                end
        end
        DATA0_6:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx  = DATA0_6;
                end
                else
                begin
                        next_state_tx  = DATA0_7;
                end
        end
        DATA0_7:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx  = DATA0_7;
                end
                else
                begin
                        next_state_tx  = DATA0_8;
                end
        end
        DATA0_8:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx  = DATA0_8;
                end
                else
                begin
                        next_state_tx  =  RESPONSE_DATA0_1;
                end
        end
        RESPONSE_DATA0_1:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx  =  RESPONSE_DATA0_1;
                end
                else if(RESPONSE == 1'b0)//ACK
                begin
                        next_state_tx  =   DELAY_BYTES;
                end
                else if(RESPONSE == 1'b1)//NACK
                begin
                        next_state_tx  =   NACK;
                end
        end
 
        //second byte
        DATA1_1:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx  = DATA1_1;
                end
                else
                begin
                        next_state_tx  = DATA1_2;
                end
        end
        DATA1_2:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx = DATA1_2;
                end
                else
                begin
                        next_state_tx = DATA1_3;
                end
        end
        DATA1_3:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx  = DATA1_3;
                end
                else
                begin
                        next_state_tx  =  DATA1_4;
                end
        end
        DATA1_4:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx  = DATA1_4;
                end
                else
                begin
                        next_state_tx  = DATA1_5;
                end
        end
        DATA1_5:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx = DATA1_5;
                end
                else
                begin
                        next_state_tx = DATA1_6;
                end
        end
        DATA1_6:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx  =  DATA1_6;
                end
                else
                begin
                        next_state_tx  =  DATA1_7;
                end
        end
        DATA1_7:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx =  DATA1_7;
                end
                else
                begin
                        next_state_tx =  DATA1_8;
                end
        end
        DATA1_8:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx = DATA1_8;
                end
                else
                begin
                        next_state_tx = RESPONSE_DATA1_1;
                end
        end
        RESPONSE_DATA1_1:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx   =  RESPONSE_DATA1_1;
                end
                else if(RESPONSE == 1'b0)//ACK
                begin
                        next_state_tx   =  DELAY_BYTES;
                end
                else if(RESPONSE == 1'b1)//NACK
                begin
                        next_state_tx   =  NACK;
                end
        end
        DELAY_BYTES://THIS FORM WORKS 
        begin
 
 
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx =  DELAY_BYTES;
                end
                else
                begin
 
                        if(count_tx == 2'd0)
                        begin
                                next_state_tx = ADDRESS_1;
                        end
                        else if(count_tx   == 2'd1)
                        begin
                                next_state_tx = DATA0_1;
                        end
                        else if(count_tx   == 2'd2)
                        begin
                                next_state_tx = DATA1_1;
                        end
                        else if(count_tx   == 2'd3)
                        begin
                                next_state_tx = STOP;
                        end
 
                end
 
        end
        NACK://NOT TESTED YET !!!!
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2]*2'd2)
                begin
                        next_state_tx  = NACK;
                end
                else
                begin
                        if(count_tx == 2'd0)
                        begin
                                next_state_tx = CONTROLIN_1;
                        end
                        else if(count_tx == 2'd1)
                        begin
                                next_state_tx = ADDRESS_1;
                        end
                        else if(count_tx  == 2'd2)
                        begin
                                next_state_tx   = DATA0_1;
                        end
                        else if(count_tx == 2'd3)
                        begin
                                next_state_tx = DATA1_1;
                        end
                end
        end
        STOP://THIS WORK
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx = STOP;
                end
                else
                begin
                        next_state_tx = IDLE;
                end
        end
        default:
        begin
                next_state_tx =  IDLE;
        end
        endcase
 
 
end
 
 
 
//SEQUENTIAL   
always@(posedge PCLK)
begin
 
        //RESET SYNC
        if(!PRESETn)
        begin
                //SIGNALS MUST BE RESETED
                count_send_data <= 12'd0;
                state_tx   <= IDLE;
                SDA_OUT<= 1'b1;
                fifo_tx_rd_en <= 1'b0;
                count_tx   <= 2'd0;
                BR_CLK_O <= 1'b1;
                RESPONSE<= 1'b0;
        end
        else
        begin
 
                // SEQUENTIAL FUN START
                state_tx  <= next_state_tx;
 
                case(state_tx)
                IDLE:
                begin
 
                        fifo_tx_rd_en <= 1'b0;
 
 
                        if(DATA_CONFIG_REG[0] == 1'b0 && (fifo_tx_f_full == 1'b1 ||fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b0)
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<= 1'b1;
                                BR_CLK_O <= 1'b1;
                        end
                        else if(DATA_CONFIG_REG[0] == 1'b1 && ((fifo_tx_f_empty == 1'b0 && fifo_tx_f_full == 1'b0 )|| fifo_tx_f_full == 1'b1 ) && DATA_CONFIG_REG[1] == 1'b0)
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=1'b0;
                        end
                        else if(DATA_CONFIG_REG[0] == 1'b1 && (fifo_tx_f_full == 1'b1 ||fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b1)
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<= 1'b1;
                                BR_CLK_O <= 1'b1;
                        end
 
                end
                START:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                BR_CLK_O <= 1'b0;
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                        end
 
                        if(count_send_data == DATA_CONFIG_REG[13:2]- 12'd1)
                        begin
                                SDA_OUT<=fifo_tx_data_out[0:0];
                                count_tx   <= 2'd0;
                        end
 
                end
                CONTROLIN_1:
                begin
 
 
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
 
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[0:0];
 
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[1:1];
                        end
 
 
                end
 
                CONTROLIN_2:
                begin
 
 
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[1:1];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[2:2];
                        end
 
                end
 
                CONTROLIN_3:
                begin
 
 
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[2:2];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[3:3];
                        end
 
 
 
                end
                CONTROLIN_4:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[3:3];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[4:4];
                        end
 
                end
 
                CONTROLIN_5:
                begin
 
 
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[4:4];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[5:5];
                        end
 
                end
                CONTROLIN_6:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[5:5];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[6:6];
                        end
 
 
                end
 
                CONTROLIN_7:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[6:6];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[7:7];
                        end
 
 
                end
                CONTROLIN_8:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[7:7];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<= 1'b0;
                        end
 
 
                end
                RESPONSE_CIN:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
 
                                //LETS TRY USE THIS BUT I DONT THINK IF WORKS  
                                RESPONSE<= SDA;
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                        end
 
 
                end
                ADDRESS_1:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[8:8];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[9:9];
                        end
 
                end
                ADDRESS_2:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[9:9];
 
                                if(count_receive_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[10:10];
                        end
 
                end
                ADDRESS_3:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[10:10];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[11:11];
                        end
 
                end
                ADDRESS_4:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[11:11];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[12:12];
                        end
                end
                ADDRESS_5:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[12:12];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[13:13];
                        end
 
 
                end
                ADDRESS_6:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[13:13];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[14:14];
                        end
 
                end
                ADDRESS_7:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[14:14];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[15:15];
                        end
 
 
                end
                ADDRESS_8:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[15:15];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=1'b0;
                        end
 
                end
                RESPONSE_ADDRESS:
                begin
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
 
                                //LETS TRY USE THIS BUT I DONT THINK IF WORKS  
                                RESPONSE<= SDA;
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                        end
 
                end
                DATA0_1:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[16:16];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[17:17];
                        end
 
 
                end
                DATA0_2:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[17:17];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[18:18];
                        end
 
 
                end
                DATA0_3:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[18:18];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[19:19];
                        end
 
                end
                DATA0_4:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[19:19];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[20:20];
                        end
 
                end
                DATA0_5:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[20:20];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[21:21];
                        end
 
                end
                DATA0_6:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[21:21];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[22:22];
                        end
 
                end
                DATA0_7:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[22:22];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[23:23];
                        end
 
                end
                DATA0_8:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[23:23];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
 
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=1'b0;
                        end
 
                end
                RESPONSE_DATA0_1:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
 
                                //LETS TRY USE THIS BUT I DONT THINK IF WORKS  
                                RESPONSE<= SDA;
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                        end
 
                end
                DATA1_1:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[24:24];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[25:25];
 
                        end
 
 
                end
                DATA1_2:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[25:25];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[26:26];
                        end
 
                end
                DATA1_3:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[26:26];
 
                                if(count_receive_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
 
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[27:27];
                        end
 
                end
                DATA1_4:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[27:27];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
 
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[28:28];
                        end
 
                end
                DATA1_5:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[28:28];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
 
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[29:29];
                        end
 
                end
                DATA1_6:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[29:29];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
 
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[30:30];
                        end
 
                end
                DATA1_7:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[30:30];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
 
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[31:31];
                        end
 
 
                end
                DATA1_8:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[31:31];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
 
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=1'b0;
                        end
 
                end
                RESPONSE_DATA1_1:
                begin
                        //fifo_  _rd_en <= 1'b1;
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
 
                                //LETS TRY USE THIS BUT I DONT THINK IF WORKS  
                                RESPONSE<= SDA;
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                fifo_tx_rd_en <= 1'b1;
                        end
 
                end
                DELAY_BYTES:
                begin
 
                        fifo_tx_rd_en <= 1'b0;
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
 
                                count_send_data <= count_send_data + 12'd1;
                                BR_CLK_O <= 1'b0;
                                SDA_OUT<=1'b0;
                        end
                        else
                        begin
 
 
                                if(count_tx == 2'd0)
                                begin
                                        count_tx <= count_tx + 2'd1;
                                        SDA_OUT<=fifo_tx_data_out[8:8];
                                end
                                else if(count_tx   == 2'd1)
                                begin
                                        count_tx <= count_tx + 2'd1;
                                        SDA_OUT<=fifo_tx_data_out[16:16];
                                end
                                else if(count_tx == 2'd2)
                                begin
                                        count_tx <= count_tx + 2'd1;
                                        SDA_OUT<=fifo_tx_data_out[24:24];
                                end
                                else if(count_tx == 2'd3)
                                begin
                                        count_tx <= 2'd0;
                                end
 
                                count_send_data <= 12'd0;
 
                        end
 
                end
                //THIS BLOCK MUST BE CHECKED WITH CARE
                NACK:// MORE A RESTART 
                begin
                        fifo_tx_rd_en <= 1'b0;
 
                        if(count_send_data < DATA_CONFIG_REG[13:2]*2'd2)
                        begin
                                count_send_data <= count_send_data + 12'd1;
 
                                if(count_receive_data < DATA_CONFIG_REG[13:2]/12'd2)
                                begin
                                        SDA_OUT<=1'b0;
                                end
                                else if(count_send_data > DATA_CONFIG_REG[13:2]/12'd2-12'd1 && count_send_data < DATA_CONFIG_REG[13:2])
                                begin
                                        SDA_OUT<=1'b1;
                                end
                                else if(count_send_data  == DATA_CONFIG_REG[13:2]*2'd2)
                                begin
                                        SDA_OUT<=1'b0;
                                end
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd2)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else if(count_send_data > DATA_CONFIG_REG[13:2]/12'd2-12'd1 && count_send_data < DATA_CONFIG_REG[13:2])
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data < DATA_CONFIG_REG[13:2]*2'd2)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
 
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
 
                                if(count_tx == 2'd0)
                                begin
                                        count_tx <= 2'd0;
                                        SDA_OUT<=fifo_tx_data_out[0:0];
                                end
                                else if(count_tx == 2'd1)
                                begin
                                        count_tx <= 2'd1;
                                        SDA_OUT<=fifo_tx_data_out[8:8];
                                end
                                else if(count_tx == 2'd2)
                                begin
                                        count_tx <= 2'd2;
                                        SDA_OUT<=fifo_tx_data_out[16:16];
                                end
                                else if(count_tx == 2'd3)
                                begin
                                        count_tx <= 2'd3;
                                        SDA_OUT<=fifo_tx_data_out[24:24];
                                end
 
 
                        end
                end
                STOP:
                begin
 
                        BR_CLK_O <= 1'b1;
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd2-12'd2)
                                begin
                                        SDA_OUT<=1'b0;
                                end
                                else if(count_send_data > DATA_CONFIG_REG[13:2]/12'd2-12'd1 && count_send_data < DATA_CONFIG_REG[13:2])
                                begin
                                        SDA_OUT<=1'b1;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                        end
                end
                default:
                begin
                        fifo_tx_rd_en <= 1'b0;
                        count_send_data <= 12'd4095;
                end
                endcase
 
        end
 
 
end
 
 
        //STATE CONTROL 
        reg [5:0] state_rx;
        reg [5:0] next_state_rx;
 
assign ENABLE_SDA = (state_rx ==  RESPONSE_CIN||
                     state_rx ==  RESPONSE_ADDRESS||
                     state_rx == RESPONSE_DATA0_1||
                     state_rx == RESPONSE_DATA1_1)?1'b1:
                    (state_tx ==  RESPONSE_CIN||
                     state_tx ==  RESPONSE_ADDRESS||
                     state_tx == RESPONSE_DATA0_1||
                     state_tx == RESPONSE_DATA1_1)?1'b0:1'b1;
 
 
assign ENABLE_SCL = (state_rx ==  RESPONSE_CIN||
                     state_rx ==  RESPONSE_ADDRESS||
                     state_rx == RESPONSE_DATA0_1||
                     state_rx == RESPONSE_DATA1_1)?1'b1:
                    (state_tx ==  RESPONSE_CIN||
                     state_tx ==  RESPONSE_ADDRESS||
                     state_tx == RESPONSE_DATA0_1||
                     state_tx == RESPONSE_DATA1_1)?1'b1:1'b0;
 
 
//COMBINATIONAL BLOCK TO RX
always@(*)
begin
 
        //THE FUN START HERE :-)
        //COMBINATIONAL UPDATE STATE BE CAREFUL WITH WHAT YOU MAKE HERE
        next_state_rx = state_rx;
 
        case(state_rx)//state_rx IS MORE SECURE CHANGE ONLY IF YOU KNOW WHAT ARE YOU DOING 
        IDLE:
        begin
                //OBEYING SPEC
                if(DATA_CONFIG_REG[0] == 1'b0 && DATA_CONFIG_REG[1] == 1'b0)
                begin
                        next_state_rx =   IDLE;
                end
                else if(DATA_CONFIG_REG[0] == 1'b1 && DATA_CONFIG_REG[1] == 1'b1)
                begin
                        next_state_rx =   IDLE;
                end
                else if(DATA_CONFIG_REG[0] == 1'b0 && DATA_CONFIG_REG[1] == 1'b1 && SDA_OUT_RX == 1'b0 && BR_CLK_O_RX == 1'b0)
                begin
                        next_state_rx =   START;
                end
 
 
        end
        START://THIS IS USED TOO ALL STATE MACHINES THE COUNTER_SEND_DATA
        begin
 
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   START;
                end
                else if(fifo_rx_data_in[0] == 1'b0 && fifo_rx_data_in[1] == 1'b0)
                begin
                        next_state_rx =   CONTROLIN_1;
                end
                else
                begin
                        next_state_rx =   IDLE;
                end
 
        end
          CONTROLIN_1:
        begin
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   CONTROLIN_1;
                end
                else
                begin
                        next_state_rx =   CONTROLIN_2;
                end
 
        end
          CONTROLIN_2:
        begin
 
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   CONTROLIN_2;
                end
                else
                begin
                        next_state_rx =   CONTROLIN_3;
                end
 
        end
          CONTROLIN_3:
        begin
 
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   CONTROLIN_3;
                end
                else
                begin
                        next_state_rx =   CONTROLIN_4;
                end
        end
          CONTROLIN_4:
        begin
 
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   CONTROLIN_4;
                end
                else
                begin
                        next_state_rx =   CONTROLIN_5;
                end
        end
          CONTROLIN_5:
        begin
 
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   CONTROLIN_5;
                end
                else
                begin
                        next_state_rx =   CONTROLIN_6;
                end
        end
          CONTROLIN_6:
        begin
 
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   CONTROLIN_6;
                end
                else
                begin
                        next_state_rx =   CONTROLIN_7;
                end
        end
          CONTROLIN_7:
        begin
 
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   CONTROLIN_7;
                end
                else
                begin
                        next_state_rx =   CONTROLIN_8;
                end
        end
          CONTROLIN_8:
        begin
 
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   CONTROLIN_8;
                end
                else
                begin
                        next_state_rx =   RESPONSE_CIN;
                end
        end
        RESPONSE_CIN:
        begin
 
                if(count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   RESPONSE_CIN;
                end
                else if(RESPONSE == 1'b0)//ACK
                begin
                        next_state_rx  =   DELAY_BYTES;
                end
                else if(RESPONSE == 1'b1)//NACK
                begin
                        next_state_rx  =   NACK;
                end
 
        end
        //NOW SENDING ADDRESS
        ADDRESS_1:
        begin
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   ADDRESS_1;
                end
                else
                begin
                        next_state_rx =   ADDRESS_2;
                end
        end
        ADDRESS_2:
        begin
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   ADDRESS_2;
                end
                else
                begin
                        next_state_rx =   ADDRESS_3;
                end
        end
        ADDRESS_3:
        begin
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   ADDRESS_3;
                end
                else
                begin
                        next_state_rx =   ADDRESS_4;
                end
        end
        ADDRESS_4:
        begin
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   ADDRESS_4;
                end
                else
                begin
                        next_state_rx =   ADDRESS_5;
                end
        end
        ADDRESS_5:
        begin
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   ADDRESS_5;
                end
                else
                begin
                        next_state_rx =   ADDRESS_6;
                end
        end
        ADDRESS_6:
        begin
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   ADDRESS_6;
                end
                else
                begin
                        next_state_rx =   ADDRESS_7;
                end
        end
        ADDRESS_7:
        begin
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   ADDRESS_7;
                end
                else
                begin
                        next_state_rx =   ADDRESS_8;
                end
        end
        ADDRESS_8:
        begin
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   ADDRESS_8;
                end
                else
                begin
                        next_state_rx =   RESPONSE_ADDRESS;
                end
        end
        RESPONSE_ADDRESS:
        begin
                if(count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   RESPONSE_ADDRESS;
                end
                else if(RESPONSE == 1'b0)//ACK
                begin
                        next_state_rx  =   DELAY_BYTES;
                end
                else if(RESPONSE == 1'b1)//NACK
                begin
                        next_state_rx  =   NACK;
                end
        end
        //data in
        DATA0_1:
        begin
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   DATA0_1;
                end
                else
                begin
                        next_state_rx =   DATA0_2;
                end
        end
          DATA0_2:
        begin
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   DATA0_2;
                end
                else
                begin
                        next_state_rx =   DATA0_3;
                end
        end
          DATA0_3:
        begin
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   DATA0_3;
                end
                else
                begin
                        next_state_rx =   DATA0_4;
                end
        end
          DATA0_4:
        begin
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   DATA0_4;
                end
                else
                begin
                        next_state_rx =   DATA0_5;
                end
        end
          DATA0_5:
        begin
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   DATA0_5;
                end
                else
                begin
                        next_state_rx =   DATA0_6;
                end
        end
          DATA0_6:
        begin
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   DATA0_6;
                end
                else
                begin
                        next_state_rx =   DATA0_7;
                end
        end
          DATA0_7:
        begin
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   DATA0_7;
                end
                else
                begin
                        next_state_rx =   DATA0_8;
                end
        end
          DATA0_8:
        begin
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   DATA0_8;
                end
                else
                begin
                        next_state_rx =   RESPONSE_DATA0_1;
                end
        end
        RESPONSE_DATA0_1:
        begin
 
                if(count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   RESPONSE_DATA0_1;
                end
                else if(RESPONSE == 1'b0)//ACK
                begin
                        next_state_rx  =   DELAY_BYTES;
                end
                else if(RESPONSE == 1'b1)//NACK
                begin
                        next_state_rx  =   NACK;
                end
        end
        //second byte
        DATA1_1:
        begin
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   DATA1_1;
                end
                else
                begin
                        next_state_rx =   DATA1_2;
                end
        end
        DATA1_2:
        begin
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   DATA1_2;
                end
                else
                begin
                        next_state_rx =   DATA1_3;
                end
        end
        DATA1_3:
        begin
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   DATA1_3;
                end
                else
                begin
                        next_state_rx =   DATA1_4;
                end
        end
          DATA1_4:
        begin
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   DATA1_4;
                end
                else
                begin
                        next_state_rx =   DATA1_5;
                end
        end
          DATA1_5:
        begin
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   DATA1_5;
                end
                else
                begin
                        next_state_rx =   DATA1_6;
                end
        end
          DATA1_6:
        begin
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   DATA1_6;
                end
                else
                begin
                        next_state_rx =   DATA1_7;
                end
        end
          DATA1_7:
        begin
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   DATA1_7;
                end
                else
                begin
                        next_state_rx =   DATA1_8;
                end
        end
          DATA1_8:
        begin
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   DATA1_8;
                end
                else
                begin
                        next_state_rx =   RESPONSE_DATA1_1;
                end
        end
        RESPONSE_DATA1_1:
        begin
                if(count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   RESPONSE_DATA0_1;
                end
                else if(RESPONSE == 1'b0)//ACK
                begin
                        next_state_rx  =   DELAY_BYTES;
                end
                else if(RESPONSE == 1'b1)//NACK
                begin
                        next_state_rx  =   NACK;
                end
 
        end
        DELAY_BYTES://THIS FORM WORKS 
        begin
 
 
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   DELAY_BYTES;
                end
                else
                begin
 
                        if(count_rx == 2'd0)
                        begin
                                next_state_rx =   ADDRESS_1;
                        end
                        else if(count_rx == 2'd1)
                        begin
                                next_state_rx =   DATA0_1;
                        end
                        else if(count_rx == 2'd2)
                        begin
                                next_state_rx =   DATA1_1;
                        end
                        else if(count_rx == 2'd3)
                        begin
                                next_state_rx =   STOP;
                        end
 
                end
 
        end
          STOP://THIS WORK
        begin
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_rx =   STOP;
                end
                else
                begin
                        next_state_rx =   IDLE;
                end
        end
        default:
        begin
                        next_state_rx =   IDLE;
        end
        endcase
 
 
end
 
 
 
//SEQUENTIAL   
always@(posedge PCLK)
begin
 
        //RESET SYNC
        if(!PRESETn)
        begin
                //SIGNALS MUST BE RESETED
                  count_receive_data <= 12'd0;
                state_rx <=   IDLE;
                SDA_OUT_RX<= 1'b0;
                fifo_rx_wr_en <= 1'b0;
                count_rx <= 2'd0;
                BR_CLK_O_RX <= 1'b0;
        end
        else
        begin
 
                // SEQUENTIAL FUN START
                state_rx <= next_state_rx;
 
                case(state_rx)
                  IDLE:
                begin
 
 
 
                        if(((fifo_rx_f_full == 1'b0 && fifo_rx_f_empty == 1'b0) || (fifo_rx_f_full == 1'b0 && fifo_rx_f_empty == 1'b1)) && DATA_CONFIG_REG[1] == 1'b1)
                        begin
 
                                  SDA_OUT_RX<= SDA;
                                  BR_CLK_O_RX<=SCL;
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  SDA_OUT_RX<= SDA_OUT_RX;
                                  BR_CLK_O_RX<=BR_CLK_O_RX;
                                  count_receive_data <=   count_receive_data;
                        end
 
                end
                  START:
                begin
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
 
                        if(  count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                        begin
                                fifo_rx_data_in[0]<= SDA;
                                fifo_rx_data_in[1]<= SCL;
                        end
 
                end
                  CONTROLIN_1:
                begin
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
 
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                        begin
                                fifo_rx_data_in[0]<= SDA;
                        end
 
                end
                  CONTROLIN_2:
                begin
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
 
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                        begin
                                fifo_rx_data_in[1]<= SDA;
                        end
 
                end
                  CONTROLIN_3:
                begin
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
 
 
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                        begin
                                fifo_rx_data_in[2]<= SDA;
                        end
 
 
                end
                  CONTROLIN_4:
                begin
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
 
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                        begin
                                fifo_rx_data_in[3]<= SDA;
                        end
 
                end
                  CONTROLIN_5:
                begin
 
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
 
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                        begin
                                        fifo_rx_data_in[4]<= SDA;
                        end
 
 
                end
                  CONTROLIN_6:
                begin
                                if(  count_receive_data < DATA_CONFIG_REG[13:2])
                                begin
                                          count_receive_data <=   count_receive_data + 12'd1;
                                end
                                else
                                begin
                                          count_receive_data <= 12'd0;
                                end
 
                                if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        fifo_rx_data_in[5]<= SDA;
                                end
                end
 
                  CONTROLIN_7:
                begin
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
 
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                        begin
                                fifo_rx_data_in[6]<= SDA;
                        end
                end
                  CONTROLIN_8:
                begin
 
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
 
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                        begin
                                fifo_rx_data_in[7]<= SDA;
                        end
 
 
 
                end
                  RESPONSE_CIN:
                begin
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
 
                end
                  ADDRESS_1:
                begin
 
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
 
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                        begin
                                fifo_rx_data_in[8]<= SDA;
                        end
 
 
                end
                  ADDRESS_2:
                begin
 
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
 
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                        begin
                                fifo_rx_data_in[9]<= SDA;
                        end
 
 
                end
                  ADDRESS_3:
                begin
 
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
 
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                        begin
                                fifo_rx_data_in[10]<= SDA;
                        end
 
 
 
                end
                  ADDRESS_4:
                begin
 
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
 
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                        begin
                                fifo_rx_data_in[11]<= SDA;
                        end
 
                end
                  ADDRESS_5:
                begin
 
 
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
 
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                        begin
                                fifo_rx_data_in[12]<= SDA;
                        end
 
 
                end
                  ADDRESS_6:
                begin
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
 
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                        begin
                                fifo_rx_data_in[13]<= SDA;
                        end
 
                end
                  ADDRESS_7:
                begin
 
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
 
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                        begin
                                fifo_rx_data_in[14]<= SDA;
                        end
 
                end
                  ADDRESS_8:
                begin
 
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
 
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                        begin
                                fifo_rx_data_in[15]<= SDA;
                        end
 
 
                end
                  RESPONSE_ADDRESS:
                begin
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
 
 
                end
                  DATA0_1:
                begin
 
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
 
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                        begin
                                fifo_rx_data_in[16]<= SDA;
                        end
 
 
 
                end
                  DATA0_2:
                begin
 
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
 
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                        begin
                                fifo_rx_data_in[17]<= SDA;
                        end
 
 
                end
                  DATA0_3:
                begin
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
 
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                        begin
                                fifo_rx_data_in[18]<= SDA;
                        end
 
                end
                  DATA0_4:
                begin
 
 
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
 
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                        begin
                                fifo_rx_data_in[19]<= SDA;
                        end
 
                end
                  DATA0_5:
                begin
 
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
 
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                        begin
                                fifo_rx_data_in[20]<= SDA;
                        end
 
 
                end
                  DATA0_6:
                begin
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
 
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                        begin
                                fifo_rx_data_in[21]<= SDA;
                        end
 
                end
                  DATA0_7:
                begin
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
 
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                        begin
                                fifo_rx_data_in[22]<= SDA;
                        end
 
                end
                  DATA0_8:
                begin
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
 
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                        begin
                                fifo_rx_data_in[23]<= SDA;
                        end
 
                end
                  RESPONSE_DATA0_1:
                begin
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
 
                end
                  DATA1_1:
                begin
 
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
 
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                        begin
                                fifo_rx_data_in[24]<= SDA;
                        end
 
                end
                  DATA1_2:
                begin
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
 
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                        begin
                                fifo_rx_data_in[25]<= SDA;
                        end
 
 
                end
                  DATA1_3:
                begin
 
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
 
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                        begin
                                fifo_rx_data_in[26]<= SDA;
                        end
 
 
                end
                  DATA1_4:
                begin
 
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
 
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                        begin
                                fifo_rx_data_in[27]<= SDA;
                        end
 
 
                end
                  DATA1_5:
                begin
 
 
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
 
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                        begin
                                fifo_rx_data_in[28]<= SDA;
                        end
 
 
                end
                  DATA1_6:
                begin
 
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
 
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                        begin
                                fifo_rx_data_in[29]<= SDA;
                        end
 
 
 
                end
                  DATA1_7:
                begin
 
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
 
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                        begin
                                fifo_rx_data_in[30]<= SDA;
                        end
 
 
 
                end
                  DATA1_8:
                begin
 
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
 
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                        begin
                                fifo_rx_data_in[31]<= SDA;
                        end
 
                end
                RESPONSE_DATA1_1:
                begin
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
                        //fifo_  _rd_en <= 1'b1;
 
                end
                DELAY_BYTES:
                begin
 
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
 
 
                                if(count_rx == 2'd0)
                                begin
                                        count_rx <= count_rx + 2'd1;
                                        //SDA_OUT<=fifo_tx_data_out[8:8];
                                end
                                else if(count_rx   == 2'd1)
                                begin
                                        count_rx <= count_tx + 2'd1;
                                        //SDA_OUT<=fifo_tx_data_out[16:16];
                                end
                                else if(count_rx == 2'd2)
                                begin
                                        count_rx <= count_rx + 2'd1;
                                        //SDA_OUT<=fifo_tx_data_out[24:24];
                                end
                                else if(count_rx == 2'd3)
                                begin
                                        count_rx <= 2'd0;
                                end
 
                                count_receive_data <= 12'd0;
 
                        end
 
 
                end
                STOP:
                begin
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
                        begin
                                  count_receive_data <=   count_receive_data + 12'd1;
                        end
                        else
                        begin
                                  count_receive_data <= 12'd0;
                        end
                        fifo_rx_wr_en <= 1'b0;
                end
                default:
                begin
                        fifo_rx_wr_en <= 1'b0;
                          count_receive_data <= 12'd4095;
                end
                endcase
 
        end
 
 
end
 
//USED ONLY TO COUNTER TIME
always@(posedge PCLK)
begin
 
        //RESET SYNC
        if(!PRESETn)
        begin
                count_timeout <= 12'd0;
        end
        else
        begin
                if(count_timeout <= TIMEOUT_TX && state_tx == IDLE)
                begin
                        if(SDA == 1'b0 && SCL == 1'b0)
                        count_timeout <= count_timeout + 12'd1;
                end
                else
                begin
                        count_timeout <= 12'd0;
                end
 
        end
 
end
 
 
endmodule
 
Line No.	Rev	Author	Line
1	2	redbear	`//////////////////////////////////////////////////////////////////`
2			`////`
3			`////`
4			`//// TOP I2C BLOCK to I2C Core`
5			`////`
6			`////`
7			`////`
8			`//// This file is part of the APB to I2C project`
9			`////`
10			`//// http://www.opencores.org/cores/apbi2c/`
11			`////`
12			`////`
13			`////`
14			`//// Description`
15			`////`
16			`//// Implementation of APB IP core according to`
17			`////`
18			`//// apbi2c_spec IP core specification document.`
19			`////`
20			`////`
21			`////`
22			`//// To Do: Things are right here but always all block can suffer changes`
23			`////`
24			`////`
25			`////`
26			`////`
27			`////`
28			`//// Author(s): - Felipe Fernandes Da Costa, fefe2560@gmail.com`
29	4	redbear	`//// Ronal Dario Celaya ,rcelaya.dario@gmail.com`
30	2	redbear	`////`
31			`/////////////////////////////////////////////////////////////////`
32			`////`
33			`////`
34			`//// Copyright (C) 2009 Authors and OPENCORES.ORG`
35			`////`
36			`////`
37			`////`
38			`//// This source file may be used and distributed without`
39			`////`
40			`//// restriction provided that this copyright statement is not`
41			`////`
42			`//// removed from the file and that any derivative work contains`
43			`//// the original copyright notice and the associated disclaimer.`
44			`////`
45			`////`
46			`//// This source file is free software; you can redistribute it`
47			`////`
48			`//// and/or modify it under the terms of the GNU Lesser General`
49			`////`
50			`//// Public License as published by the Free Software Foundation;`
51			`//// either version 2.1 of the License, or (at your option) any`
52			`////`
53			`//// later version.`
54			`////`
55			`////`
56			`////`
57			`//// This source is distributed in the hope that it will be`
58			`////`
59			`//// useful, but WITHOUT ANY WARRANTY; without even the implied`
60			`////`
61			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR`
62			`////`
63			`//// PURPOSE. See the GNU Lesser General Public License for more`
64			`//// details.`
65			`////`
66			`////`
67			`////`
68			`//// You should have received a copy of the GNU Lesser General`
69			`////`
70			`//// Public License along with this source; if not, download it`
71			`////`
72			`//// from http://www.opencores.org/lgpl.shtml`
73			`////`
74			`////`
75			`///////////////////////////////////////////////////////////////////`
76
77
78			`timescale 1ns/1ps //timescale
79
80			`module module_i2c#(`
81			`//THIS IS USED ONLY LIKE PARAMETER TO BEM CONFIGURABLE`
82			`parameter integer DWIDTH = 32,`
83			`parameter integer AWIDTH = 14`
84			`)`
85			`(`
86			`//I2C INTERFACE WITH ANOTHER BLOCKS`
87			`input PCLK,`
88			`input PRESETn,`
89
90			`//INTERFACE WITH FIFO TRANSMISSION`
91			`input fifo_tx_f_full,`
92			`input fifo_tx_f_empty,`
93			`input [DWIDTH-1:0] fifo_tx_data_out,`
94
95			`//INTERFACE WITH FIFO RECEIVER`
96			`input fifo_rx_f_full,`
97			`input fifo_rx_f_empty,`
98	6	redbear	`output reg fifo_rx_wr_en,`
99			`output reg [DWIDTH-1:0] fifo_rx_data_in,`
100	2	redbear
101			`//INTERFACE WITH REGISTER CONFIGURATION`
102			`input [AWIDTH-1:0] DATA_CONFIG_REG,`
103	20	redbear	`input [AWIDTH-1:0] TIMEOUT_TX,`
104	2	redbear
105	20	redbear	`//INTERFACE TO APB AND READ FOR FIFO`
106	2	redbear	`output reg fifo_tx_rd_en,`
107	20	redbear	`output TX_EMPTY,`
108			`output RX_EMPTY,`
109	2	redbear	`output ERROR,`
110	20	redbear	`output ENABLE_SDA,`
111			`output ENABLE_SCL,`
112	2	redbear
113			`//I2C BI DIRETIONAL PORTS`
114			`inout SDA,`
115			`inout SCL`
116
117
118			`);`
119
120			`//THIS IS USED TO GENERATE INTERRUPTIONS`
121			`assign TX_EMPTY = (fifo_tx_f_empty == 1'b1)? 1'b1:1'b0;`
122			`assign RX_EMPTY = (fifo_rx_f_empty == 1'b1)? 1'b1:1'b0;`
123
124			`//THIS COUNT IS USED TO CONTROL DATA ACCROSS FSM`
125	6	redbear	`reg [1:0] count_tx;`
126	20	redbear	`reg [1:0] count_rx;`
127	2	redbear	`//CONTROL CLOCK AND COUNTER`
128			`reg [11:0] count_send_data;`
129	20	redbear	`reg [11:0] count_receive_data;`
130			`reg [11:0] count_timeout;`
131	2	redbear	`reg BR_CLK_O;`
132			`reg SDA_OUT;`
133
134	20	redbear	`reg BR_CLK_O_RX;`
135			`reg SDA_OUT_RX;`
136
137	2	redbear	`//RESPONSE USED TO HOLD SIGNAL TO ACK OR NACK`
138			`reg RESPONSE;`
139
140	20	redbear	`// PARAMETERS USED TO STATE MACHINE`
141	2	redbear
142	20	redbear	`localparam [5:0] IDLE = 6'd0, //IDLE`
143	2	redbear
144	20	redbear	`START = 6'd1,//START BIT`
145	2	redbear
146	20	redbear	`CONTROLIN_1 = 6'd2, //START BYTE`
147			`CONTROLIN_2 = 6'd3,`
148			`CONTROLIN_3 = 6'd4,`
149			`CONTROLIN_4 = 6'd5,`
150			`CONTROLIN_5 = 6'd6,`
151			`CONTROLIN_6 = 6'd7,`
152			`CONTROLIN_7 = 6'd8,`
153			`CONTROLIN_8 = 6'd9, //END FIRST BYTE`
154	2	redbear
155	20	redbear	`RESPONSE_CIN =6'd10, //RESPONSE`
156	2	redbear
157	20	redbear	`ADDRESS_1 = 6'd11,//START BYTE`
158			`ADDRESS_2 = 6'd12,`
159			`ADDRESS_3 = 6'd13,`
160			`ADDRESS_4 = 6'd14,`
161			`ADDRESS_5 = 6'd15,`
162			`ADDRESS_6 = 6'd16,`
163			`ADDRESS_7 = 6'd17,`
164			`ADDRESS_8 = 6'd18,//END FIRST BYTE`
165	2	redbear
166	20	redbear	`RESPONSE_ADDRESS =6'd19, //RESPONSE`
167	2	redbear
168	20	redbear	`DATA0_1 = 6'd20,//START BYTE`
169			`DATA0_2 = 6'd21,`
170			`DATA0_3 = 6'd22,`
171			`DATA0_4 = 6'd23,`
172			`DATA0_5 = 6'd24,`
173			`DATA0_6 = 6'd25,`
174			`DATA0_7 = 6'd26,`
175			`DATA0_8 = 6'd27,//END FIRST BYTE`
176	2	redbear
177	20	redbear	`RESPONSE_DATA0_1 = 6'd28, //RESPONSE`
178	2	redbear
179	20	redbear	`DATA1_1 = 6'd29,//START BYTE`
180			`DATA1_2 = 6'd30,`
181			`DATA1_3 = 6'd31,`
182			`DATA1_4 = 6'd32,`
183			`DATA1_5 = 6'd33,`
184			`DATA1_6 = 6'd34,`
185			`DATA1_7 = 6'd35,`
186			`DATA1_8 = 6'd36,//END FIRST BYTE`
187	2	redbear
188	20	redbear	`RESPONSE_DATA1_1 = 6'd37,//RESPONSE`
189	2	redbear
190	20	redbear	`DELAY_BYTES = 6'd38,//USED ONLY IN ACK TO DELAY BETWEEN`
191			`NACK = 6'd39,//USED ONLY IN ACK TO DELAY BETWEEN BYTES`
192			`STOP = 6'd40;//USED TO SEND STOP BIT`
193	2	redbear
194			`//STATE CONTROL`
195	20	redbear	`reg [5:0] state_tx;`
196			`reg [5:0] next_state_tx;`
197	2	redbear
198			`//ASSIGN REGISTERS TO BIDIRETIONAL PORTS`
199	22	redbear	`assign SDA =(DATA_CONFIG_REG[0] == 1'b1 & DATA_CONFIG_REG[1] == 1'b0 & state_tx != RESPONSE_CIN & state_tx != RESPONSE_ADDRESS & state_tx != RESPONSE_DATA0_1 & state_tx != RESPONSE_DATA1_1)?SDA_OUT:SDA_OUT_RX;`
200	2	redbear
201	22	redbear
202			`assign SCL = (DATA_CONFIG_REG[0] == 1'b1 & DATA_CONFIG_REG[1] == 1'b0)?BR_CLK_O:BR_CLK_O_RX;`
203
204	4	redbear	`//STANDARD ERROR`
205			`assign ERROR = (DATA_CONFIG_REG[0] == 1'b1 & DATA_CONFIG_REG[1] == 1'b1)?1'b1:1'b0;`
206	2	redbear
207	20	redbear
208			`//COMBINATIONAL BLOCK TO`
209	2	redbear	`always@(*)`
210			`begin`
211
212			`//THE FUN START HERE :-)`
213			`//COMBINATIONAL UPDATE STATE BE CAREFUL WITH WHAT YOU MAKE HERE`
214	20	redbear	`next_state_tx=state_tx;`
215	2	redbear
216	20	redbear	`case(state_tx)//state_ IS MORE SECURE CHANGE ONLY IF YOU KNOW WHAT ARE YOU DOING`
217			`IDLE:`
218	2	redbear	`begin`
219			`//OBEYING SPEC`
220	18	redbear	`if(DATA_CONFIG_REG[0] == 1'b0 && (fifo_tx_f_full == 1'b1 \|\| fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b0)`
221	2	redbear	`begin`
222	20	redbear	`next_state_tx = IDLE;`
223	2	redbear	`end`
224	18	redbear	`else if(DATA_CONFIG_REG[0] == 1'b1 && (fifo_tx_f_full == 1'b1 \|\| fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b1)`
225	2	redbear	`begin`
226	20	redbear	`next_state_tx = IDLE;`
227	4	redbear	`end`
228	23	redbear	`else if(DATA_CONFIG_REG[0] == 1'b1 && ((fifo_tx_f_full == 1'b0 && fifo_tx_f_empty == 1'b0) \|\| fifo_tx_f_full == 1'b1) && DATA_CONFIG_REG[1] == 1'b0 && count_timeout < TIMEOUT_TX)`
229	4	redbear	`begin`
230	20	redbear	`next_state_tx = START;`
231	2	redbear	`end`
232
233
234			`end`
235	20	redbear	`START://THIS IS USED TOO ALL STATE MACHINES THE COUNTER_SEND_DATA`
236	2	redbear	`begin`
237			`if(count_send_data != DATA_CONFIG_REG[13:2])`
238			`begin`
239	20	redbear	`next_state_tx = START;`
240	2	redbear	`end`
241			`else`
242			`begin`
243	20	redbear	`next_state_tx = CONTROLIN_1;`
244	2	redbear	`end`
245
246			`end`
247	20	redbear	`CONTROLIN_1:`
248	2	redbear	`begin`
249			`if(count_send_data != DATA_CONFIG_REG[13:2])`
250			`begin`
251	20	redbear	`next_state_tx = CONTROLIN_1;`
252	2	redbear	`end`
253			`else`
254			`begin`
255	20	redbear	`next_state_tx = CONTROLIN_2;`
256	2	redbear	`end`
257
258			`end`
259	20	redbear	`CONTROLIN_2:`
260	2	redbear	`begin`
261
262			`if(count_send_data != DATA_CONFIG_REG[13:2])`
263			`begin`
264	20	redbear	`next_state_tx = CONTROLIN_2;`
265	2	redbear	`end`
266			`else`
267			`begin`
268	20	redbear	`next_state_tx = CONTROLIN_3;`
269	2	redbear	`end`
270
271			`end`
272	20	redbear	`CONTROLIN_3:`
273	2	redbear	`begin`
274
275			`if(count_send_data != DATA_CONFIG_REG[13:2])`
276			`begin`
277	20	redbear	`next_state_tx = CONTROLIN_3;`
278	2	redbear	`end`
279			`else`
280			`begin`
281	20	redbear	`next_state_tx = CONTROLIN_4;`
282	2	redbear	`end`
283			`end`
284	20	redbear	`CONTROLIN_4:`
285	2	redbear	`begin`
286
287			`if(count_send_data != DATA_CONFIG_REG[13:2])`
288			`begin`
289	20	redbear	`next_state_tx = CONTROLIN_4;`
290	2	redbear	`end`
291			`else`
292			`begin`
293	20	redbear	`next_state_tx = CONTROLIN_5;`
294	2	redbear	`end`
295			`end`
296	20	redbear	`CONTROLIN_5:`
297	2	redbear	`begin`
298
299			`if(count_send_data != DATA_CONFIG_REG[13:2])`
300			`begin`
301	20	redbear	`next_state_tx = CONTROLIN_5;`
302	2	redbear	`end`
303			`else`
304			`begin`
305	20	redbear	`next_state_tx = CONTROLIN_6;`
306	2	redbear	`end`
307			`end`
308	20	redbear	`CONTROLIN_6:`
309	2	redbear	`begin`
310
311			`if(count_send_data != DATA_CONFIG_REG[13:2])`
312			`begin`
313	20	redbear	`next_state_tx = CONTROLIN_6;`
314	2	redbear	`end`
315			`else`
316			`begin`
317	20	redbear	`next_state_tx = CONTROLIN_7;`
318	2	redbear	`end`
319			`end`
320	20	redbear	`CONTROLIN_7:`
321	2	redbear	`begin`
322
323			`if(count_send_data != DATA_CONFIG_REG[13:2])`
324			`begin`
325	20	redbear	`next_state_tx = CONTROLIN_7;`
326	2	redbear	`end`
327			`else`
328			`begin`
329	20	redbear	`next_state_tx = CONTROLIN_8;`
330	2	redbear	`end`
331			`end`
332	20	redbear	`CONTROLIN_8:`
333	2	redbear	`begin`
334
335			`if(count_send_data != DATA_CONFIG_REG[13:2])`
336			`begin`
337	20	redbear	`next_state_tx = CONTROLIN_8;`
338	2	redbear	`end`
339			`else`
340			`begin`
341	22	redbear	`next_state_tx = RESPONSE_CIN;`
342	2	redbear	`end`
343			`end`
344	20	redbear	`RESPONSE_CIN:`
345	2	redbear	`begin`
346
347			`if(count_send_data != DATA_CONFIG_REG[13:2])`
348			`begin`
349	20	redbear	`next_state_tx = RESPONSE_CIN;`
350	2	redbear	`end`
351			`else if(RESPONSE == 1'b0)//ACK`
352			`begin`
353	20	redbear	`next_state_tx = DELAY_BYTES;`
354	2	redbear	`end`
355			`else if(RESPONSE == 1'b1)//NACK`
356			`begin`
357	20	redbear	`next_state_tx = NACK;`
358	2	redbear	`end`
359
360			`end`
361
362			`//NOW SENDING ADDRESS`
363	20	redbear	`ADDRESS_1:`
364	2	redbear	`begin`
365			`if(count_send_data != DATA_CONFIG_REG[13:2])`
366			`begin`
367	20	redbear	`next_state_tx = ADDRESS_1;`
368	2	redbear	`end`
369			`else`
370			`begin`
371	20	redbear	`next_state_tx = ADDRESS_2;`
372	2	redbear	`end`
373			`end`
374	20	redbear	`ADDRESS_2:`
375	2	redbear	`begin`
376			`if(count_send_data != DATA_CONFIG_REG[13:2])`
377			`begin`
378	20	redbear	`next_state_tx = ADDRESS_2;`
379	2	redbear	`end`
380			`else`
381			`begin`
382	20	redbear	`next_state_tx = ADDRESS_3;`
383	2	redbear	`end`
384			`end`
385	20	redbear	`ADDRESS_3:`
386	2	redbear	`begin`
387			`if(count_send_data != DATA_CONFIG_REG[13:2])`
388			`begin`
389	20	redbear	`next_state_tx = ADDRESS_3;`
390	2	redbear	`end`
391			`else`
392			`begin`
393	20	redbear	`next_state_tx = ADDRESS_4;`
394	2	redbear	`end`
395			`end`
396	20	redbear	`ADDRESS_4:`
397	2	redbear	`begin`
398			`if(count_send_data != DATA_CONFIG_REG[13:2])`
399			`begin`
400	20	redbear	`next_state_tx = ADDRESS_4;`
401	2	redbear	`end`
402			`else`
403			`begin`
404	20	redbear	`next_state_tx = ADDRESS_5;`
405	2	redbear	`end`
406			`end`
407	20	redbear	`ADDRESS_5:`
408	2	redbear	`begin`
409			`if(count_send_data != DATA_CONFIG_REG[13:2])`
410			`begin`
411	20	redbear	`next_state_tx = ADDRESS_5;`
412	2	redbear	`end`
413			`else`
414			`begin`
415	20	redbear	`next_state_tx = ADDRESS_6;`
416	2	redbear	`end`
417			`end`
418	20	redbear	`ADDRESS_6:`
419	2	redbear	`begin`
420			`if(count_send_data != DATA_CONFIG_REG[13:2])`
421			`begin`
422	20	redbear	`next_state_tx = ADDRESS_6;`
423	2	redbear	`end`
424			`else`
425			`begin`
426	20	redbear	`next_state_tx = ADDRESS_7;`
427	2	redbear	`end`
428			`end`
429	20	redbear	`ADDRESS_7:`
430	2	redbear	`begin`
431			`if(count_send_data != DATA_CONFIG_REG[13:2])`
432			`begin`
433	20	redbear	`next_state_tx = ADDRESS_7;`
434	2	redbear	`end`
435			`else`
436			`begin`
437	20	redbear	`next_state_tx = ADDRESS_8;`
438	2	redbear	`end`
439			`end`
440	20	redbear	`ADDRESS_8:`
441	2	redbear	`begin`
442			`if(count_send_data != DATA_CONFIG_REG[13:2])`
443			`begin`
444	20	redbear	`next_state_tx = ADDRESS_8;`
445	2	redbear	`end`
446			`else`
447			`begin`
448	20	redbear	`next_state_tx = RESPONSE_ADDRESS;`
449	2	redbear	`end`
450			`end`
451	20	redbear	`RESPONSE_ADDRESS:`
452	2	redbear	`begin`
453			`if(count_send_data != DATA_CONFIG_REG[13:2])`
454			`begin`
455	20	redbear	`next_state_tx = RESPONSE_ADDRESS;`
456	2	redbear	`end`
457			`else if(RESPONSE == 1'b0)//ACK`
458			`begin`
459	20	redbear	`next_state_tx = DELAY_BYTES;`
460	2	redbear	`end`
461			`else if(RESPONSE == 1'b1)//NACK --> RESTART CONDITION AND BACK TO START BYTE AGAIN`
462			`begin`
463	20	redbear	`next_state_tx = NACK;`
464	2	redbear	`end`
465			`end`
466
467			`//data in`
468	20	redbear	`DATA0_1:`
469	2	redbear	`begin`
470			`if(count_send_data != DATA_CONFIG_REG[13:2])`
471			`begin`
472	20	redbear	`next_state_tx = DATA0_1;`
473	2	redbear	`end`
474			`else`
475			`begin`
476	20	redbear	`next_state_tx = DATA0_2;`
477	2	redbear	`end`
478			`end`
479	20	redbear	`DATA0_2:`
480	2	redbear	`begin`
481			`if(count_send_data != DATA_CONFIG_REG[13:2])`
482			`begin`
483	20	redbear	`next_state_tx = DATA0_2;`
484	2	redbear	`end`
485			`else`
486			`begin`
487	20	redbear	`next_state_tx = DATA0_3;`
488	2	redbear	`end`
489			`end`
490	20	redbear	`DATA0_3:`
491	2	redbear	`begin`
492			`if(count_send_data != DATA_CONFIG_REG[13:2])`
493			`begin`
494	20	redbear	`next_state_tx = DATA0_3;`
495	2	redbear	`end`
496			`else`
497			`begin`
498	20	redbear	`next_state_tx = DATA0_4;`
499	2	redbear	`end`
500			`end`
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