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[/] [artificial_neural_network/] [trunk/] [ANN_kernel/] [RTL_VHDL_files/] [adder_tree.vhd] - Blame information for rev 3

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1 3 ojosynariz
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date:    15:27:42 06/20/2013
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-- Design Name:    Configurable ANN
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-- Module Name:    adder_tree - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description: Recursive adder tree
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use ieee.numeric_std.all;
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entity adder_tree is
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   generic
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   (
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      NumIn   : integer := 9;  -- Number of inputs
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      Nbit    : integer := 12  -- Bit width of the input data
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   );
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   port
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   (
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      -- Input ports
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      reset    : in  std_logic;
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      clk      : in  std_logic;
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      en       : in  std_logic; -- Enable
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      inputs   : in  std_logic_vector((Nbit*NumIn)-1 downto 0); -- Input data
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      -- Output ports
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      en_out   : out std_logic; -- Output enable (output data validation)
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      output   : out std_logic_vector(Nbit-1 downto 0) -- Output of the tree adder
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   );
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end adder_tree;
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architecture Behavioral of adder_tree is
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   constant NumIn2 : integer := NumIn/2; -- Number of imputs of the next adder tree layer
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   signal next_en : std_logic := '0'; -- Next adder tree layer enable
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   signal res : std_logic_vector((Nbit*((NumIn2)+(NumIn mod 2)))-1 downto 0); -- Partial results
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   signal resL_reg : std_logic_vector((Nbit*NumIn2)-1 downto 0);
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   signal resH_reg : std_logic_vector(Nbit-1 downto 0);
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begin
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-- Additions:
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add_proc:
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   process (clk) -- Synchronous to allow pipeline
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   begin
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      if (clk'event and clk = '1') then
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         if (reset = '1') then
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            resL_reg <= (others => '0');
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         else
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            if (en = '1') then
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               -- Addition of inputs (2*i y 2*i+1), resulting in NumIn/2 outputs of this layer of the adder tree:
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               for i in ((NumIn2)-1) downto 0 loop
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                  resL_reg((Nbit*(i+1))-1 downto Nbit*i) <= std_logic_vector( signed(inputs((Nbit*((2*i)+1))-1 downto Nbit*2*i)) + signed(inputs((Nbit*((2*i)+2))-1 downto Nbit*((2*i)+1))) );
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               end loop;
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            end if;
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         end if;
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      end if;
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   end process;
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   res((Nbit*NumIn2)-1 downto 0) <= resL_reg;
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-- Register the uneven input (if needed):
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uneven_register:
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   if (NumIn mod 2 = 1) generate
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      process (clk)
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      begin
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         if (clk'event and clk = '1') then
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            if (reset = '1') then
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               resH_reg <= (others => '0');
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            else
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               if (en = '1') then
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                  resH_reg <= inputs((Nbit*NumIn)-1 downto Nbit*(NumIn-1));
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               end if;
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            end if;
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         end if;
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      end process;
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      res((Nbit*((NumIn2)+1))-1 downto Nbit*(NumIn2)) <= resH_reg;
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   end generate;
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   process (clk)
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   begin
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      if (clk'event and clk = '1') then
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         if reset = '1' then
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            next_en <= '0';
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         else
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            next_en <= en; -- Enable is delayed 1 cycle for the next layer of the adder tree
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         end if;
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      end if;
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   end process;
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recursion:
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   if (NumIn > 2) generate
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      sub_adder_tree: entity work.adder_tree
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         generic map
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         (
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            NumIn => (NumIn2)+(NumIn mod 2),
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            Nbit  => Nbit
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         )
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         port map
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         (
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            clk    => clk,
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            reset  => reset,
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            en     => next_en,
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            inputs => res,
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            en_out => en_out,
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            output => output -- Solution is passed from the sub-adder trees to the top adder tree
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         );
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   end generate;
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trivial_solution:
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   if (NumIn = 2) generate
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      en_out <= next_en;
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      output <= res; -- Assign the final result to the adder tree output
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   end generate;
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end Behavioral;
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