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[/] [artificial_neural_network/] [trunk/] [ANN_kernel/] [RTL_VHDL_files/] [ann.vhd] - Blame information for rev 13

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1 3 ojosynariz
----------------------------------------------------------------------------------
2
-- Company: CEI - UPM
3
-- Engineer: David Aledo
4
--
5
-- Create Date: 01.10.2015 15:15:28
6
-- Design Name: Configurable ANN
7
-- Module Name: ann - config_structural
8
-- Project Name:
9
-- Target Devices:
10
-- Tool Versions:
11
-- Description: generates the structure of an ANN with the given parameters.
12
--
13
-- Dependencies:
14
--
15
-- Revision:
16
-- Revision 0.01 - File Created
17
-- Additional Comments:
18
--
19
----------------------------------------------------------------------------------
20
 
21
 
22
library IEEE;
23
use IEEE.STD_LOGIC_1164.ALL;
24
use IEEE.NUMERIC_STD.ALL;
25
 
26
use work.layers_pkg.all;
27
 
28
entity ann is
29
   generic
30
   (
31 8 jstefanowi
      WBinit  : boolean := false;
32 3 ojosynariz
      Nlayer  : integer := 2;   ---- Number of layers
33
      NbitW   : natural := 16;  ---- Bit width of weights and biases
34
      NumIn   : natural := 64;  ---- Number of inputs to the network
35
      NbitIn  : natural := 8;   ---- Bit width of the inputs
36
      NumN    : int_vector;   ------ Number of neurons in each layer
37
      l_type  : string;   ---------- Layer type of each layer
38
      f_type  : string;   ---------- Activation function type of each layer
39
      LSbit   : int_vector;   ------ LSB of the output of each layer
40
      NbitO   : int_vector;   ------ Bit width of the outputs of each layer
41
      NbitOut : natural := 8   ----- Bit width of the network output
42
   );
43
 
44
   port
45
   (
46
      -- Input ports
47
      reset   : in  std_logic;
48
      clk     : in  std_logic;
49
      run_in  : in  std_logic; -- Start and input data validation
50
      m_en    : in  std_logic; -- Weight and bias memory enable (external interface)
51
      m_we    : in  std_logic_vector(((NbitW+7)/8)-1 downto 0); -- Weight and bias memory write enable (external interface)
52
      inputs  : in  std_logic_vector(NbitIn-1 downto 0); -- Input data
53
      wdata   : in  std_logic_vector(NbitW-1 downto 0);  -- Weight and bias memory write data
54 6 ojosynariz
      addr    : in  std_logic_vector((calculate_addr_l(NumIn, NumN, Nlayer)+log2(Nlayer))-1 downto 0); -- Weight and bias memory address
55 3 ojosynariz
 
56
      -- Output ports
57
      run_out : out std_logic; -- Output data validation
58
      rdata   : out std_logic_vector(NbitW-1 downto 0);  -- Weight and bias memory read data
59
      outputs : out std_logic_vector(NbitOut-1 downto 0) -- Output data
60
   );
61
end ann;
62
 
63
architecture config_structural of ann is
64
 
65
   -- Arrays of configuration constants, generated from string generics:
66
   constant ltype_v : ltype_vector(Nlayer-1 downto 0) := assign_ltype(l_type,Nlayer);
67
   constant ftype_v : ftype_vector(Nlayer-1 downto 0) := assign_ftype(f_type,Nlayer);
68
   constant lra_l  : int_vector(Nlayer-1 downto 0) := assign_addrl(NumIn,NumN,Nlayer); -- Layer RAM address length of each layer
69
   constant NumIn_v : int_vector(Nlayer-1 downto 0) := NumN(Nlayer-2 downto 0) & NumIn;
70
   constant wra_l   : int_vector(Nlayer-1 downto 0) := log2(NumIn_v, Nlayer); -- Weight RAM address length of each layer
71
   constant bra_l   : int_vector(Nlayer-1 downto 0) := log2(NumN, Nlayer); -- Bias ram address length of each layer
72
 
73
   -- Internal signals:
74
   signal lm_en  : std_logic_vector(Nlayer-1 downto 0); -- Weight and bias memory enable of each layer
75
   type lrd_type is array (Nlayer-1 downto 0) of std_logic_vector(NbitW-1 downto 0);
76
   signal lrdata : lrd_type; -- Weight and bias memory read data of each layer
77
 
78
   type lodata_t is array (Nlayer-1 downto 0) of std_logic_vector(calculate_max_mul(NbitO,NumN)-1 downto 0); -- Parallel or serial data
79
   type ladata_t is array (Nlayer-1 downto 0) of std_logic_vector(calculate_max(NbitO)-1 downto 0); -- Always serial data
80
   signal runO : std_logic_vector(Nlayer-1 downto 0); -- Output data validation of each layer (before activation function)
81
   signal runI : std_logic_vector(Nlayer-1 downto 0); -- Input data validation of each layer
82
   signal runA : std_logic_vector(Nlayer-1 downto 0); -- Auxiliar serial data validation of each layer
83
   signal lodata : lodata_t; -- Output data of each layer (before activation function)
84
   signal lidata : lodata_t; -- Input data of each layer
85
   signal ladata : ladata_t; -- Auxiliar serial data of each layer
86
 
87
begin
88
 
89
-- Weight and bias memory layer selection (combinational mux):
90
   process (addr(addr'length-1 downto addr'length-log2(Nlayer)), m_en, lrdata)
91
   begin
92
      for i in 0 to Nlayer-1 loop
93
         if to_integer(unsigned(addr(addr'length-1 downto addr'length-log2(Nlayer)))) = i then
94
            lm_en(i) <= m_en;
95
            rdata <= lrdata(i);
96
         else
97
            lm_en(i) <= '0';
98
         end if;
99
      end loop;
100
      -- Note: Attention with addresses greater than Nlayer when it is not a power of two
101
   end process;
102
 
103
-- ATTENTION: without the following if generate, the first layer must have serial input ('S')
104
parallelize_inputs:
105
if ltype_v(0)(1) = 'P' generate
106
   -- TODO: instantiate shift register with parallel output.
107
   -- synthesis translate_off
108
   assert ltype_v(0)(1) /= 'P'
109
      report "Current version does not accept parallel inputs."
110
      severity failure;
111
   -- synthesis translate_on
112
   -- TODO: delete above lines when instantiate shift register with parallel output.
113
end generate;
114
 
115
first_layer_SP:
116
if ltype_v(0) = "SP" generate
117
 
118
first_layerSP_top_inst: entity work.layerSP_top
119
   generic map
120
   (
121 8 jstefanowi
      WBinit  => WBinit ,
122
      LNum    => 0 ,
123 3 ojosynariz
      NumN    => NumN(0),   -- Number of neurons in the first layer
124
      NumIn   => NumIn,   ---- Number of inputs of the first layer
125
      NbitIn  => NbitIn,   --- Bit width of the input data
126
      NbitW   => NbitW,   ---- Bit width of weights and biases
127
      NbitOut => NbitO(0),  -- Bit width of the first layer output
128
      lra_l   => lra_l(0),  -- Layer RAM address length of the first layer
129
      wra_l   => wra_l(0),  -- Weight RAM address length of the first layer
130
      bra_l   => bra_l(0),  -- Bias RAM address length of the first layer
131
      LSbit   => LSbit(0)   -- Less significant bit of the first layer outputs
132
   )
133
   port map
134
   (
135
      -- Input ports
136
      reset   => reset,
137
      clk     => clk,
138
      run_in  => run_in,   --- Input data validation of the first layer
139
      m_en    => lm_en(0),  -- Weight and bias memory enable of the first layer
140
      b_sel   => addr((addr'length-log2(Nlayer))-1), -- Bias select. Selects between layer or bias memories
141
      m_we    => m_we,   ----- Weight and bias memory write enable
142
      inputs  => inputs,   --- Inputs of the first layer (serial data)
143
      wdata   => wdata,   ---- Weight and bias memory write data
144
      addr    => addr(lra_l(0)-1 downto 0), -- Weight and bias memory address of the first layer
145
 
146
      -- Output ports
147
      run_out => runO(0),   -- Output data validation of the first layer
148
      rdata   => lrdata(0), -- Weight and bias memory read data of the first layer
149
      outputs => lodata(0)((NumN(0)*NbitO(0))-1 downto 0) -- Outputs of the first layer (parallel data)
150
   );
151
end generate;
152
 
153
 
154
layers_insts:
155
for i in 1 to Nlayer-1 generate
156
 
157
   -- If the previous layer (i-1) has parallel outputs and actual layer (i) has serial inputs, a serializer
158
   -- is inserted before the activation function (i-1). So, parallel activations functions are avoided.
159
serializer:
160
   if (ltype_v(i-1)(2) = 'P') and (ltype_v(i)(1) = 'S') generate
161
 
162
      -- Instantiate shift-register with parallel load:
163
shiftreg_parallel_load: entity work.shiftreg_pl
164
      generic map
165
      (
166
         Nreg => NumN(i-1),   --- Number of registers in the shift-register corresponds with the number of neurons in the previous layer (i-1)
167
         Nbit => NbitO(i-1)   --- Bit width of the registers corresponds with the bit width of the outputs of the previous layer (i-1)
168
      )
169
      port map
170
      (
171
         reset   => reset,
172
         clk     => clk,
173
         run_in  => runO(i-1), -- Input data validation of the shift-register comes from the output data validation of the previous layer (i-1)
174
         inputs  => lodata(i-1)((NumN(i-1)*NbitO(i-1))-1 downto 0), -- Parallel input data to the shift-register come from the previous layer (i-1)
175
         run_out => runA(i-1), -- Output data validation goes to the activation function of the previous layer (i-1)
176
         outputs => ladata(i-1)(NbitO(i-1)-1 downto 0) -- Output serial data go to the activation function of the previous layer (i-1)
177
      );
178
 
179
      -- Instantiate single activation function of the previous layer (i-1):
180
activation_function_inst: entity work.activation_function
181
      generic map
182
      (
183
         f_type => ftype_v(i-1), -- Activation function type of the previous layer (i-1)
184 8 jstefanowi
         Nbit   => NbitO(i-1),   -- Bit width of the outputs of the previous layer (i-1)
185 13 ojosynariz
         lsbit  => LSbit(i-1)    -- least significant bit of activation function
186 3 ojosynariz
      )
187
      port map
188
      (
189
         reset   => reset,
190
         clk     => clk,
191
         run_in  => runA(i-1),   -- Input data validation comes from the shift-register
192
         inputs  => ladata(i-1)(NbitO(i-1)-1 downto 0), -- Serial input data come from the shift-register
193
         run_out => runI(i-1),   -- Output data validation goes to the input data validation of this layer
194
         outputs => lidata(i-1)(NbitO(i-1)-1 downto 0) -- Serial output data go to the inputs of this layer
195
      );
196
 
197
   end generate; -- serializer
198
 
199
   -- If the previous layer (i-1) has serial outputs and actual layer (i) has serial inputs,
200
   -- a single activation function is instantiated:
201
single_activation_function:
202
   if (ltype_v(i-1)(2) = 'S') and (ltype_v(i)(1) = 'S') generate
203
 
204
      -- Instantiate single activation function of the previous layer (i-1):
205
activation_function_inst: entity work.activation_function
206
      generic map
207
      (
208
         f_type => ftype_v(i-1), -- Activation function type of the previous layer (i-1)
209 8 jstefanowi
         Nbit   => NbitO(i-1),   -- Bit width of the outputs of the previous layer (i-1)
210
         lsbit  => LSbit(i-1)    -- least significant bit of activation function
211 3 ojosynariz
      )
212
      port map
213
      (
214
         reset   => reset,
215
         clk     => clk,
216
         run_in  => runO(i-1),   -- Input data validation comes from the previous layer (i-1)
217
         inputs  => lodata(i-1)(NbitO(i-1)-1 downto 0), -- Serial input data come from the previous layer (i-1)
218
         run_out => runI(i-1),   -- Output data validation goes to the input data validation of this layer
219
         outputs => lidata(i-1)(NbitO(i-1)-1 downto 0) -- Serial output data go to the inputs of this layer
220
      );
221
 
222
   end generate; -- single_activation_function
223
 
224
   -- If the previous layer (i-1) has parallel outputs and actual layer (i) has parallel inputs,
225
   -- multiple parallel activation functions are instantiated:
226
multiple_activation_functions:
227
   if (ltype_v(i-1)(2) = 'P') and (ltype_v(i)(1) = 'P') generate
228
 
229
      -- First of the parallel activation functions. This is the one which generates the output data validation
230
act_function_inst_0: entity work.activation_function
231
      generic map
232
      (
233
         f_type => ftype_v(i-1), -- Activation function type of the previous layer (i-1)
234 8 jstefanowi
         Nbit   => NbitO(i-1),   -- Bit width of the outputs of the previous layer (i-1)
235
         lsbit  => LSbit(i-1)    -- least significant bit of activation function
236 3 ojosynariz
      )
237
      port map
238
      (
239
         reset   => reset,
240
         clk     => clk,
241
         run_in  => runO(i-1),   -- Input data validation comes from the previous layer (i-1)
242
         inputs  => lodata(i-1)(NbitO(i-1)-1 downto 0), -- First of the parallel input data wich comes from the previous layer (i-1)
243
         run_out => runI(i-1),   -- Output data validation goes to the input data validation of this layer
244
         outputs => lidata(i-1)(NbitO(i-1)-1 downto 0)  -- First of the parallel inputs of this layer
245
      );
246
 
247
      -- Rest of the parallel activation functions of the previous layer (i-1)
248
multiple_activation_function_insts:
249
      for j in 1 to NumN(i-1)-1 generate
250
activation_function_inst: entity work.activation_function
251
         generic map
252
         (
253
            f_type => ftype_v(i-1), -- Activation function type of the previous layer (i-1)
254 8 jstefanowi
            Nbit   => NbitO(i-1) ,  -- Bit width of the outputs of the previous layer (i-1)
255
            lsbit  => LSbit(i-1)    -- least significant bit of activation function
256 3 ojosynariz
         )
257
         port map
258
         (
259
            reset   => reset,
260
            clk     => clk,
261
            run_in  => runO(i-1),   -- Input data validation comes from the previous layer (i-1)
262
            inputs  => lodata(i-1)((NbitO(i-1)*(j+1))-1 downto NbitO(i-1)*j), -- Rest of the parallel input data which come from the previous layer (i-1)
263
            run_out => open,   ------- As only one output data validation is needed, the rest ones are left unconnected
264
            outputs => lidata(i-1)((NbitO(i-1)*(j+1))-1 downto NbitO(i-1)*j)  -- Rest of the parallel inputs of this layer
265
         );
266
      end generate;
267
 
268
   end generate; -- multiple_activation_functions
269
 
270
   -- If the previous layer (i-1) has serial outputs and actual layer (i) has parallel inputs, a parallelizer
271
   -- is insested after the activation function (i-1):
272
parallelizer:
273
   if (ltype_v(i-1)(2) = 'S') and (ltype_v(i)(1) = 'P') generate
274
 
275
      -- Instantiate single activation function of the previous layer (i-1):
276
activation_function_inst: entity work.activation_function
277
      generic map
278
      (
279
         f_type => ftype_v(i-1),
280 8 jstefanowi
         Nbit   => NbitO(i-1),
281
         lsbit  => LSbit(i-1)    -- least significant bit of activation function
282 3 ojosynariz
      )
283
      port map
284
      (
285
         reset   => reset,
286
         clk     => clk,
287
         run_in  => runO(i-1),
288
         inputs  => lodata(i-1)(NbitO(i-1)-1 downto 0),
289
         run_out => runA(i-1),
290
         outputs => ladata(i-1)(NbitO(i-1)-1 downto 0)
291
      );
292
 
293
      -- Instantiate shift-register with parallel unload:
294
shiftreg_parallel_unload: entity work.shiftreg_pu
295
      generic map
296
      (
297
         Nreg => NumN(i-1),   --- Number of registers in the shift-register corresponds with the number of neurons in the previous layer (i-1)
298
         Nbit => NbitO(i-1)   --- Bit width of the registers corresponds with the bit width of the outputs of the previous layer (i-1)
299
      )
300
      port map
301
      (
302
         reset   => reset,
303
         clk     => clk,
304
         run_in  => runA(i-1), -- Input data validation comes from the activation function of the previous layer (i-1)
305
         inputs  => ladata(i-1)(NbitO(i-1)-1 downto 0), -- Serial input data
306 13 ojosynariz
         run_out => runI(i-1), -- Output data validation goes to the input data validation of this layer
307
         outputs => lidata(i-1)((NumN(i-1)*NbitO(i-1))-1 downto 0) -- Parallel output data
308 3 ojosynariz
      );
309
 
310
   end generate; -- parallelizer
311
 
312
   -- Instance the layer (i), cases SP, PS or PP:
313
 
314
   -- Serial-input parallel-output layer:
315
SP_case:
316
   if ltype_v(i) = "SP" generate
317
layerSP_top_inst: entity work.layerSP_top
318
      generic map
319
      (
320 8 jstefanowi
         WBinit  => WBinit ,
321
         LNum    => i ,
322 3 ojosynariz
         NumN    => NumN(i),   --- Number of neurons in layer (i)
323
         NumIn   => NumN(i-1),  -- Number of inputs, is the number of neurons in previous layer (i-1)
324
         NbitIn  => NbitO(i-1), -- Bit width of the input data, is the bit width of output data of layer (i-1)
325
         NbitW   => NbitW,   ----- Bit width of weights and biases
326
         NbitOut => NbitO(i),   -- Bit width of layer (i) output
327
         lra_l   => lra_l(i),   -- Layer RAM address length of layer (i)
328
         wra_l   => wra_l(i),   -- Weight RAM address length of layer (i)
329
         bra_l   => bra_l(i),   -- Bias RAM address length of layer (i)
330
         LSbit   => LSbit(i)   --- Less significant bit of layer (i) outputs
331
      )
332
      port map
333
      (
334
         -- Input ports
335
         reset   => reset,
336
         clk     => clk,
337
         run_in  => runI(i-1),  -- Input data validation of this layer
338
         m_en    => lm_en(i),   -- Weight and bias memory enable of this layer
339
         b_sel   => addr((addr'length-log2(Nlayer))-1), -- Bias select. Selects between layer or bias memories
340
         m_we    => m_we,   ------ Weight and bias memory write enable
341
         inputs  => lidata(i-1)(NbitO(i-1)-1 downto 0), -- Inputs of this layer (serial data)
342
         wdata   => wdata,   ----- Weight and bias memory write data
343
         addr    => addr(lra_l(i)-1 downto 0), -- Weight and bias memory address of this layer
344
 
345
         -- Output ports
346
         run_out => runO(i),   -- Output data validation of this layer
347
         rdata   => lrdata(i), -- Weight and bias memory read data of this layer
348
         outputs => lodata(i)((NumN(i)*NbitO(i))-1 downto 0) -- Outputs of this layer (parallel data)
349
      );
350
   end generate;
351
 
352
   -- Parallel-input serial-output layer:
353
PS_case:
354
   if ltype_v(i) = "PS" generate
355
layerPS_top_inst: entity work.layerPS_top
356
      generic map
357 13 ojosynariz
      (
358 8 jstefanowi
         WBinit  => WBinit ,
359
         LNum    => i ,
360 3 ojosynariz
         NumN    => NumN(i),   --- Number of neurons in layer (i)
361
         NumIn   => NumN(i-1),  -- Number of inputs, is the number of neurons in previous layer (i-1)
362
         NbitIn  => NbitO(i-1), -- Bit width of the input data, is the bit width of output data of layer (i-1)
363
         NbitW   => NbitW,   ----- Bit width of weights and biases
364
         NbitOut => NbitO(i),   -- Bit width of layer (i) output
365
         lra_l   => lra_l(i),   -- Layer RAM address length of layer (i)
366
         wra_l   => wra_l(i),   -- Weight RAM address length of layer (i)
367
         bra_l   => bra_l(i),   -- Bias ram address length of layer (i)
368
         LSbit   => LSbit(i)   --- Less significant bit of layer (i) outputs
369
      )
370
      port map
371
      (
372
         -- Input ports
373
         reset   => reset,
374
         clk     => clk,
375
         run_in  => runI(i-1),  -- Input data validation of this layer
376
         m_en    => lm_en(i),   -- Weight and bias memory enable of this layer
377
         b_sel   => addr((addr'length-log2(Nlayer))-1), -- Bias select. Selects between layer or bias memories
378
         m_we    => m_we,   ------ Weight and bias memory write enable
379
         inputs  => lidata(i-1)((NumN(i-1)*NbitO(i-1))-1 downto 0), -- Inputs of this layer (parallel data)
380
         wdata   => wdata,   ----- Weight and bias memory write data
381
         addr    => addr(lra_l(i)-1 downto 0), -- Weight and bias memory address of this layer
382
 
383
         -- Output ports
384
         run_out => runO(i),   -- Output data validation of this layer
385
         rdata   => lrdata(i), -- Weight and bias memory read data of this layer
386
         outputs => lodata(i)(NbitO(i)-1 downto 0) -- Outputs of this layer (serial data)
387
      );
388
   end generate;
389
 
390
   -- Parallel-input parallel-output layer:
391
PP_case:
392
   if ltype_v(i) = "PP" generate
393
      -- TODO: instance a full parallel layer. At current version this layer type has not been developed.
394
      -- synthesis translate_off
395 8 jstefanowi
      --assert l_type(i) /= "PP"
396
      --   report "Current version does not accept parallel-input parallel-output (PP) layer type."
397
      --   severity failure;
398 3 ojosynariz
      -- synthesis translate_on
399
      -- TODO: delete above lines when instantiate the parallel-input parallel-output layer.
400
   end generate;
401
 
402
end generate; -- layers_insts
403
 
404
-- If the last layer (Nlayer-1) has parallel outputs, a serializer is inserted before the activation function:
405
last_serializer:
406
if (ltype_v(Nlayer-1)(2) = 'P') generate
407
 
408
   -- Instantiate shift-register with parallel load:
409
last_shiftreg_parallel_load: entity work.shiftreg_pl
410
   generic map
411
   (
412
      Nreg => NumN(Nlayer-1),   --- Number of registers corresponds with the number of neurons in the last layer (Nlayer-1)
413
      Nbit => NbitO(Nlayer-1)   --- Bit width of the registers corresponds with the bit width of the outputs of the last layer (Nlayer-1)
414
   )
415
   port map
416
   (
417
      reset   => reset,
418
      clk     => clk,
419
      run_in  => runO(Nlayer-1), -- Input data validation comes from the output data validation of the last layer (Nlayer-1)
420
      inputs  => lodata(Nlayer-1)((NumN(Nlayer-1)*NbitO(Nlayer-1))-1 downto 0), -- Parallel input data come from the last layer
421
      run_out => runA(Nlayer-1), -- Output data validation goes to the last activation function (Nlayer-1)
422
      outputs => ladata(Nlayer-1)(NbitO(Nlayer-1)-1 downto 0) -- Serial output data go to the last activation function
423
   );
424
 
425
last_activation_function_inst: entity work.activation_function
426
      generic map
427
      (
428
         f_type => ftype_v(Nlayer-1), -- Activation function type of the last layer (Nlayer-1)
429 8 jstefanowi
         Nbit   => NbitO(Nlayer-1),   --- Bit width of the outputs of the last layer (Nlayer-1)
430
         lsbit  => LSbit(Nlayer-1)    -- least significant bit of activation function
431 3 ojosynariz
      )
432
      port map
433
      (
434
         reset   => reset,
435
         clk     => clk,
436
         run_in  => runA(Nlayer-1),   -- Input data validation comes from the shift-register output validation
437
         inputs  => ladata(Nlayer-1)(NbitO(Nlayer-1)-1 downto 0), -- Serial input data come from the shift-register
438
         run_out => run_out,   --------- Output data validation of the network
439
         outputs => outputs   ---------- Outputs of the network (serial data)
440
      );
441
 
442
end generate; -- last_serializer
443
 
444
-- If the las layer has serial outputs:
445
last_simple_activation_function:
446
if (ltype_v(Nlayer-1)(2) = 'S') generate
447
last_activation_function_inst: entity work.activation_function
448
      generic map
449
      (
450
         f_type => ftype_v(Nlayer-1), -- Activation function type of the last layer (Nlayer-1)
451 8 jstefanowi
         Nbit   => NbitO(Nlayer-1),   -- Bit width of the outputs of the last layer (Nlayer-1)
452
         lsbit  => LSbit(Nlayer-1)    -- least significant bit of activation function
453 3 ojosynariz
      )
454
      port map
455
      (
456
         reset   => reset,
457
         clk     => clk,
458
         run_in  => runO(Nlayer-1),   -- Input data validation comes from the last layer (Nlayer-1) output validation
459
         inputs  => lodata(Nlayer-1)(NbitO(Nlayer-1)-1 downto 0), -- Inputs come from the outputs of the last layer (serial data)
460
         run_out => run_out,   --------- Output data validation of the network
461
         outputs => outputs   ---------- Outputs of the network (serial data)
462
      );
463
end generate;
464
 
465
end config_structural;

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