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[/] [artificial_neural_network/] [trunk/] [ANN_kernel/] [RTL_VHDL_files/] [layerPS.vhd] - Blame information for rev 3

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1 3 ojosynariz
----------------------------------------------------------------------------------
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-- Company: CEI
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-- Engineer: David Aledo
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--
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-- Create Date:    11:24:24 05/28/2013
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-- Design Name:    Configurable ANN
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-- Module Name:    layerPS - arq
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description: basic and parametrizable neuron layer for hardware artificial
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--             neural networks. Paralel input and serial output.
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--             It implemnts one neuron reused to calculate all.
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-- Deprecated XPS library: -- Needed functions have been implemented in layers_pkg
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--library proc_common_v3_00_a;
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--use proc_common_v3_00_a.proc_common_pkg.all;
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use work.layers_pkg.all;
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entity layerPS is
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   generic
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   (
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      NumN    : natural := 64; -- Number of neurons of the layer
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      NumIn   : natural := 8;  -- Number of inputs of each neuron
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      NbitIn  : natural := 12; -- Bit width of the input data
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      NbitW   : natural := 8;  -- Bit width of weights and biases
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      NbitOut : natural := 8;  -- Bit width of the output data
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      LSbit   : natural := 4   -- Less significant bit of the outputs
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   );
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   port
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   (
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      -- Input ports
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      reset    : in  std_logic;
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      clk      : in  std_logic;
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      en       : in  std_logic; -- First step enable
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      en2      : in  std_logic; -- Second stage enable
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      en_r     : in  std_logic; -- Output register enable
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      inputs   : in  std_logic_vector((NbitIn*NumIn)-1 downto 0); -- Input data (parallel)
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      Wyb      : in  std_logic_vector((NbitW*NumIn)-1 downto 0);  -- Weight vectors
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      bias     : in  std_logic_vector(NbitW-1 downto 0);   --------- Bias
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      -- Output ports
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      en_out   : out std_logic; -- Output data validation
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      outputs  : out std_logic_vector(NbitOut-1 downto 0) -- Output data (serial)
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   );
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end layerPS;
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architecture arq of layerPS is
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   constant NbOvrf : natural := log2(NumIn); -- Extra bits avoid overflow in adders
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   constant sat_max : signed(NbitIn+NbitW+NbOvrf downto 0) := (NbitIn+NbitW+NbOvrf downto LSbit+NbitOut-1 => '0') & (LSbit+NbitOut-2 downto 0 => '1'); -- E.g. "0001111"
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   constant sat_min : signed(NbitIn+NbitW+NbOvrf downto 0) := (NbitIn+NbitW+NbOvrf downto LSbit+NbitOut-1 => '1') & (LSbit+NbitOut-2 downto 0 => '0'); -- E.g. "1110000"
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   type v_res is array(NumIn-1 downto 0) of signed((NbitIn+NbitW)-1 downto 0); -- Array type for results from multipliers
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   signal res  : v_res := (others => (others => '0')); -- Results from multipliers
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   signal sum  : std_logic_vector(NbitIn+NbitW+NbOvrf downto 0) := (others => '0');   -- Addition result
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   signal reg  : std_logic_vector(NbitOut-1 downto 0) := (others => '0');    ----------- Output register
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   signal sum_aux : std_logic_vector(((NbitIn+NbitW+NbOvrf+1)*(NumIn+1))-1 downto 0); -- Pipeline registers for adders
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begin
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muls: -- Instances as multipliers as NumIn
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   for i in (NumIn-1) downto 0 generate
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      process (clk) -- Multiplier
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      begin
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         if (clk'event and clk = '1') then
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            if (reset = '1') then
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               res(i) <= (others => '0');
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            else
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               if (en = '1') then
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                  -- Multiplies every input with its weight:
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                  res(i) <= signed(inputs((NbitIn*(i+1))-1 downto NbitIn*i)) * signed(Wyb((NbitW*(i+1))-1 downto NbitW*i));
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               end if;
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            end if;
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         end if;
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      end process;
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   end generate;
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asign_adder_tree_inputs:
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   for i in NumIn-1 downto 0 generate
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      sum_aux(((NbitIn+NbitW+NbOvrf+1)*(i+1))-1 downto (NbitIn+NbitW+NbOvrf+1)*i) <= std_logic_vector(resize(res(i),NbitIn+NbitW+NbOvrf+1));
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   end generate;
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   sum_aux(((NbitIn+NbitW+NbOvrf+1)*(NumIn+1))-1 downto (NbitIn+NbitW+NbOvrf+1)*NumIn) <= std_logic_vector(resize(signed(bias),NbitIn+NbitW+NbOvrf+1)); -- Bias is added placed in the last position
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recursive_adder_tree: entity work.adder_tree
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         generic map
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         (
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            NumIn => NumIn+1, -- +bias
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            Nbit  => NbitIn+NbitW+NbOvrf+1
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         )
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         port map
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         (
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            clk    => clk,
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            reset  => reset,
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            en     => en2,
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            inputs => sum_aux,
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            en_out => en_out,
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            output => sum
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         );
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   process(clk)
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   begin
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      if(rising_edge(clk)) then
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         if(reset = '1') then -- Synchronous reset, active high
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            reg <= (others => '0');
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         else
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            if en_r = '1' then -- Output register enable (clipping)
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               if signed(sum) > sat_max then
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                  -- Saturating result to the maximum value:
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                  reg <= '0' & (NbitOut-2 downto 0 => '1');
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               elsif signed(sum) < sat_min then
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                  -- Saturating result to the minimum value:
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                  reg <= '1' & (NbitOut-2 downto 0 => '0');
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               else
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                  -- Configured window of result bits are assigned to the output:
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                  reg <= sum(LSbit+NbitOut-1 downto LSbit);
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               end if;
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            end if;
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         end if;
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      end if;
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   end process;
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-- Assigns output register to output data port:
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   outputs <= reg;
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end arq;

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