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[/] [artificial_neural_network/] [trunk/] [ANN_kernel/] [RTL_VHDL_files/] [mac.vhd] - Blame information for rev 3

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1 3 ojosynariz
----------------------------------------------------------------------------------
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-- Company: CEI
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-- Engineer: David Aledo
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--
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-- Create Date:
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-- Design Name:    Configurable ANN
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-- Module Name:    mac - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description: Multiplier and accumulator (MAC).
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use ieee.numeric_std.all;
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entity mac is
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   generic
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   (
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      dirload : boolean := FALSE; -- Direct load. Load accumulator with port C value (TRUE) or A*B + C (FALSE)
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      NbOvrf  : natural := 3;   ---- Extra bits in acc to avoid overflow
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      NbitIn  : natural := 16;   --- Bit width of the input data
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      NbitC   : natural := 18   ---- Bit width of weight and bias
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   );
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   port
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   (
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      CLK  : in  std_logic;
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      RST  : in  std_logic;
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      A    : in  STD_LOGIC_VECTOR (NbitIn-1 DOWNTO 0); -- Input data
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      B    : in  STD_LOGIC_VECTOR (NbitC-1 DOWNTO 0);  -- Weights
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      C    : in  std_logic_vector (NbitC-1 downto 0);  -- Bias
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      P    : out std_logic_vector (NbitIn+NbitC+NbOvrf DOWNTO 0); -- Output data
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      CE1  : in  std_logic;  -- Multiplier eneble
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      CE2  : in  std_logic;  -- Accumulator enable
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      LOAD : in  std_logic   -- Load signal. Resets the accumulator with value determined by dirload parameter
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      );
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end mac;
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architecture Behavioral of mac is
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   signal acc  : signed (NbitIn+NbitC+NbOvrf DOWNTO 0) := (others => '0'); -- Accumulator register
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   signal Mreg : signed (NbitIn+NbitC-1 DOWNTO 0) := (others => '0');  -- Multiplier output register
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begin
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   process (CLK)
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   begin
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      if CLK'event and CLK = '1' then
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         if RST = '1' then
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            acc  <= (others => '0');
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            Mreg <= (others => '0');
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         else
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            if CE1 = '1' then
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               Mreg <= signed(A)*signed(B);
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            end if;
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            if CE2 = '1' then
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               if LOAD = '1' then
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                  if dirload then
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                     -- Load acc with port C value (bias):
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                     acc <= resize(signed(C),NbitIn+NbitC+NbOvrf+1); -- Sign extension
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                  else
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                     -- Load acc with A*B + C (bias):
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                     acc <= resize(signed(C),NbitIn+NbitC+NbOvrf+1) + Mreg;
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                  end if;
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               else
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                  acc <= acc + Mreg;
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               end if;
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            end if;
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         end if;
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      end if;
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   end process;
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   P <= std_logic_vector(acc);
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end Behavioral;
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