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[/] [artificial_neural_network/] [trunk/] [ANN_kernel/] [RTL_VHDL_files/] [wb_init.vhd] - Blame information for rev 8

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Line No. Rev Author Line
1 8 jstefanowi
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.support_pkg.all;
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use work.layers_pkg.all;
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package wb_init is
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  type ramd_type is array (3 downto 0) of std_logic_vector(NbitW-1 downto 0);
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  type layer_ram is array (3 downto 0) of ramd_type;
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  type w_ram  is array (integer range <>) of layer_ram;
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  type b_type is array (integer range <>) of ramd_type;
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  constant w_init : w_ram :=
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  (
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        1 => real2stdlv(NbitW,-2.6600),
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        others =>(others => '0')
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      ),
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      others=>(others =>(others => '0'))
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    ),
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    1 => (
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        1 => real2stdlv(NbitW,-1.5274),
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        2 => real2stdlv(NbitW,-8.4909),
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        others =>(others => '0')
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      ),
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      1 => (
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        1 => real2stdlv(NbitW,0.7244),
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        2 => real2stdlv(NbitW,3.8977),
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        others =>(others => '0')
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      ),
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      others=>(others =>(others => '0'))
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    ),
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    2 => (
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        others =>(others => '0')
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      ),
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      1 => (
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        others =>(others => '0')
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      ),
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      2 => (
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        others =>(others => '0')
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      ),
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      others=>(others =>(others => '0'))
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    )
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  );
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  constant b_init : b_type :=
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  (
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      1 => real2stdlv(NbitW,(2.0**LSB_OUT)*(0.7149)),
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      others =>(others => '0')
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    ),
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    1 => (
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      1 => real2stdlv(NbitW,(2.0**LSB_OUT)*(0.3690)),
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      2 => real2stdlv(NbitW,(2.0**LSB_OUT)*(2.4685)),
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      others =>(others => '0')
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    ),
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    2 => (
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      others =>(others => '0')
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    )
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  );
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end wb_init;

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