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[/] [artificial_neural_network/] [trunk/] [test_bench/] [src/] [ann_tb.vhd] - Blame information for rev 8

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1 8 jstefanowi
-------------------------------------------------------------------------------
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-- Title      : Testbench for design "ann". XOR solving neural network.
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-- Project    : 
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-------------------------------------------------------------------------------
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-- File       : ann_tb.vhd
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-- Author     : Jurek Stefanowicz
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-- Company    : 
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-- Created    : 2016-09-30
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-- Last update: 2016-09-30
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-- Platform   : 
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-- Standard   : VHDL'87
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-------------------------------------------------------------------------------
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-- Description: 
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-------------------------------------------------------------------------------
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-- Copyright (c) 2016
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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library std;
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use std.textio.all;
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library work;
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use work.layers_pkg.all;
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use work.support_pkg.all;
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-------------------------------------------------------------------------------
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entity ann_tb is
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end ann_tb;
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-------------------------------------------------------------------------------
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architecture beh1 of ann_tb is
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  -- testbech signals
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  signal end_sim : boolean := false;
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  file data_out        : text open write_mode is "data_out_tb.txt";
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  file data_in         : text open read_mode is "data_in.txt";
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  signal reset   : std_logic := '1';
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  signal clk     : std_logic := '1';
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  -- ann input sigs
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  signal run_in  : std_logic := '0'; -- Start and input data validation
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  signal inputs  : std_logic_vector(Nbit-1 downto 0) := (others => '0'); -- Input data
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  -- weight&bias memory interface (not used)
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  signal wdata   : std_logic_vector(NbitW-1 downto 0) := (others => '0');  -- Weight and bias memory write data
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  signal addr    : std_logic_vector((calculate_addr_l(NumIn, NumN, Nlayer)+log2(Nlayer))-1 downto 0) := (others => '0'); -- Weight and bias memory address
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  signal m_en    : std_logic := '0'; -- Weight and bias memory enable (external interface)
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  signal m_we    : std_logic_vector(((NbitW+7)/8)-1 downto 0) := (others => '0');
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  signal run_out : std_logic; -- Output data validation
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  signal rdata   : std_logic_vector(NbitW-1 downto 0);  -- Weight and bias memory read data
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  signal outputs : std_logic_vector(Nbit-1 downto 0); -- Output data
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begin
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  -- component instantiation
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  ann0 : entity work.ann
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    generic map (
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      WBinit   => true,
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      Nlayer   => Nlayer,
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      NbitW    => NbitW,
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      NumIn    => NumIn,
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      NbitIn   => Nbit,
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      NumN     => NumN,
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      l_type   => l_type,
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      f_type   => f_type,
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      LSbit    => LSbit,
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      NbitO    => NbitO,
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      NbitOut  => NbitOut)
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    port map (
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      -- in
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      reset    => reset,
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      clk      => clk,
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      run_in   => run_in,
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      m_en     => m_en,
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      m_we     => m_we,
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      inputs   => inputs,
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      wdata    => wdata,
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      addr     => addr,
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      -- out
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      run_out  => run_out,
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      rdata    => rdata,
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      outputs  => outputs
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    );
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  -- clock generation
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  Clk <= not Clk after 10 ns when end_sim = false else '0';
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  -- xor wieghts:
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  -- layer0:                          addresses:
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  -- weights:                         layer bias  neuron input     
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  --   neuron 1, input 1 : -3.7596     0     0     0      0  
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  --   neuron 1, input 2 :  3.0396     0     0     0      1   
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  --   neuron 2, input 1 :  2.3740     0     0     1      0    
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  --   neuron 2, input 2 : -2.1895     0     0     1      1    
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  -- bias:                            layer bias    x   neuron       
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  --   neuron 1 : 2.20762               0     1     0      0              
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  --   neuron 2 : 0.96043               0     1     0      1                
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  -- layer1:                                
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  -- weights:                         layer bias  neuron input            
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  --   neuron 1, input 1 :  -2.2381     1     0     0      0                               
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  --   neuron 1, input 2 :  -2.2888     1     0     0      1                                 
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  -- bias:                            layer bias    x   neuron    
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  --   neuron 1: 3.8896                 1     1     0      0              
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  --
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  DataSave : process(Clk)
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    variable my_line : line;  -- type 'line' comes from textio
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  begin
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    if (Clk'event and Clk = '1' ) then
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      if ( run_out = '1') then
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        write(my_line,  to_integer(signed(outputs)));
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        writeline(data_out, my_line);
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      end if;
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    end if;
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  end process;
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  DataLoad : process
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    variable input_line  : line;
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    variable din         : real;
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  begin
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    wait for 20 ns;
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    reset <= '0';
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    wait until clk = '0';
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    wait until clk = '1';
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    wait until clk = '0';
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    wait until clk = '1';
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    l1 : while not end_sim loop
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      if not endfile(data_in) then
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        readline(data_in, input_line);
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        read(input_line, din);
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      else
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        end_sim <= true;
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        exit l1;
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      end if;
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      run_in <= '1';
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      inputs  <= std_logic_vector(to_signed(integer(din*(2.0**LSB_In)),NbitIn));
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      wait until clk = '0';
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      wait until clk = '1';
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      run_in <= '0';
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      -- We wait 4 clock cycles between run_ins because
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      -- the network has a maximum layers size of 3 neurons
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      wait until clk = '0';
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      wait until clk = '1';
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      wait until clk = '0';
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      wait until clk = '1';
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      wait until clk = '0';
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      wait until clk = '1';
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      --wait until clk = '0';
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      --wait until clk = '1';
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    end loop l1;
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    wait ;
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  end process;
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end beh1;
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