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--------------------------------------------------------------------------------
2
--
3
-- Copyright (C) 2014
4
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
5
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
6
--
7
-- This program is free software: you can redistribute it and/or modify
8
-- it under the terms of the GNU General Public License as published by
9
-- the Free Software Foundation, either version 3 of the License, or
10
-- (at your option) any later version.
11
--
12
-- This program is distributed in the hope that it will be useful,
13
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
14
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
-- GNU General Public License for more details.
16
--
17
-- You should have received a copy of the GNU General Public License
18
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
19
--
20
--------------------------------------------------------------------------------
21
 
22
-- Purpose:
23
--   The FIFO starts outputting data when the output is ready and it has been
24
--   filled with more than g_fifo_fill words. Given a fixed frame length, this
25
--   is useful when the in_val is throttled while the out_val should not be
26
--   inactive valid between out_sop to out_eop. This is necessary for frame
27
--   transport over a PHY link without separate data valid signal.
28
-- Description:
29
--   The FIFO is filled sufficiently for each input frame, as defined by the
30
--   sop and then read until the eop.
31
--   The rd_fill_32b control input is used for dynamic control of the fill
32
--   level on the read side of the FIFO. The rd_fill_32b defaults to
33
--   g_fifo_fill, so if rd_fill_32b is not connected then the fill level is
34
--   fixed to g_fifo_fill. A g_fifo_fill disables the fifo fill mechanism.
35
--   The rd_fill_32b signal must be stable in the rd_clk domain.
36
-- Remarks:
37
-- . Reuse from LOFAR rad_frame_scheduler.vhd and rad_frame_scheduler(rtl).vhd
38
-- . For g_fifo_fill=0 this dp_fifo_fill_core defaults to dp_fifo_core.
39
-- . The architecture offers two implementations via g_fifo_rl. Use 0 for show
40
--   ahead FIFO or 1 for normal FIFO. At the output of dp_fifo_fill_core the
41
--   RL=1 independent of g_fifo_rl, the g_fifo_rl only applies to the internal
42
--   FIFO. The show ahead FIFO uses the dp_latency_adapter to get to RL 0
43
--   internally. The normal FIFO is prefered, because it uses less logic. It
44
--   keeps the RL internally also at 1.
45
-- . Note that the structure of p_state is idendical in both architectures
46
--   for both g_fifo_rl=0 or 1. Hence the implementation of g_fifo_rl=1 with
47
--   dp_input_hold is an example of how to use dp_input_hold to get the same
48
--   behaviour as if the input had g_fifo_rl=0 as with the show ahead FIFO.
49
-- . To view the similarity of the p_state process for both g_fifo_rl e.g.
50
--   open the file in two editors or do repeatedly find (F3) on a text
51
--   section like 'WHEN s_fill  =>' that only occurs one in each p_state.
52
-- . The next_src_out = pend_src_out when src_in.ready='1'. However it is more
53
--   clear to only use pend_src_out and explicitely write the condition on
54
--   src_in.ready in the code, because then the structure of p_state is the
55
--   same for both g_fifo_rl=0 or 1. Furthermore using pend_src_out and 
56
--   src_in.ready is often more clear to comprehend then using next_src_out
57
--   directly.
58
 
59
LIBRARY IEEE, common_pkg_lib, dp_pkg_lib, dp_components_lib, technology_lib;
60
USE IEEE.std_logic_1164.ALL;
61
USE IEEE.numeric_std.ALL;
62
USE common_pkg_lib.common_pkg.ALL;
63
USE dp_pkg_lib.dp_stream_pkg.ALL;
64
USE technology_lib.technology_select_pkg.ALL;
65
 
66
ENTITY dp_fifo_fill_core IS
67
  GENERIC (
68
    g_technology     : NATURAL := c_tech_select_default;
69
    g_use_dual_clock : BOOLEAN := FALSE;
70
    g_data_w         : NATURAL := 16;
71
    g_bsn_w          : NATURAL := 1;
72
    g_empty_w        : NATURAL := 1;
73
    g_channel_w      : NATURAL := 1;
74
    g_error_w        : NATURAL := 1;
75
    g_use_bsn        : BOOLEAN := FALSE;
76
    g_use_empty      : BOOLEAN := FALSE;
77
    g_use_channel    : BOOLEAN := FALSE;
78
    g_use_error      : BOOLEAN := FALSE;
79
    g_use_sync       : BOOLEAN := FALSE;
80
    g_use_complex    : BOOLEAN := FALSE;  -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
81
    g_fifo_fill      : NATURAL := 0;
82
    g_fifo_size      : NATURAL := 256;    -- (32+2) * 256 = 1 M9K, g_data_w+2 for sop and eop
83
    g_fifo_af_margin : NATURAL := 4;      -- Nof words below max (full) at which fifo is considered almost full
84
    g_fifo_rl        : NATURAL := 1       -- use RL=0 for internal show ahead FIFO, default use RL=1 for internal normal FIFO
85
  );
86
  PORT (
87
    wr_rst      : IN  STD_LOGIC;
88
    wr_clk      : IN  STD_LOGIC;
89
    rd_rst      : IN  STD_LOGIC;
90
    rd_clk      : IN  STD_LOGIC;
91
    -- Monitor FIFO filling
92
    wr_ful      : OUT STD_LOGIC;  -- corresponds to the carry bit of wr_usedw when FIFO is full
93
    wr_usedw    : OUT STD_LOGIC_VECTOR(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2))-1 DOWNTO 0);  -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
94
    rd_usedw    : OUT STD_LOGIC_VECTOR(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2))-1 DOWNTO 0);  -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
95
    rd_emp      : OUT STD_LOGIC;
96
    -- MM control FIFO filling (assume 32 bit MM interface)
97
    wr_usedw_32b : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);  -- = wr_usedw
98
    rd_usedw_32b : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);  -- = rd_usedw
99
    rd_fill_32b  : IN  STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0) := TO_UVEC(g_fifo_fill, c_word_w);
100
    -- ST sink
101
    snk_out     : OUT t_dp_siso;
102
    snk_in      : IN  t_dp_sosi;
103
    -- ST source
104
    src_in      : IN  t_dp_siso;
105
    src_out     : OUT t_dp_sosi
106
  );
107
END dp_fifo_fill_core;
108
 
109
 
110
ARCHITECTURE rtl OF dp_fifo_fill_core IS
111
 
112
  CONSTANT c_fifo_rl          : NATURAL := sel_a_b(g_fifo_fill=0, 1, g_fifo_rl);
113
  CONSTANT c_fifo_fill_margin : NATURAL := g_fifo_af_margin + 2;  -- add +2 extra margin, with tb_dp_fifo_fill it follows that +1 is also enough to avoid almost full when fifo is operating near g_fifo_fill level
114
  CONSTANT c_fifo_size        : NATURAL := largest(g_fifo_size, g_fifo_fill + c_fifo_fill_margin);
115
  CONSTANT c_fifo_size_w      : NATURAL := ceil_log2(c_fifo_size);    -- = wr_usedw'LENGTH = rd_usedw'LENGTH
116
 
117
  -- The FIFO filling relies on framed data, so contrary to dp_fifo_sc the sop and eop need to be used.
118
  CONSTANT c_use_ctrl  : BOOLEAN := TRUE;
119
 
120
  -- Define t_state as slv to avoid Modelsim warning "Nonresolved signal 'nxt_state' may have multiple sources". Due to that g_fifo_rl = 0 or 1 ar both supported.
121
  --TYPE t_state IS (s_idle, s_fill, s_output, s_xoff);
122
  CONSTANT s_idle    : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
123
  CONSTANT s_fill    : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01";
124
  CONSTANT s_output  : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10";
125
  CONSTANT s_xoff    : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11";
126
 
127
  SIGNAL state       : STD_LOGIC_VECTOR(1 DOWNTO 0);  -- t_state
128
  SIGNAL nxt_state   : STD_LOGIC_VECTOR(1 DOWNTO 0);  -- t_state
129
 
130
  SIGNAL xon_reg     : STD_LOGIC;
131
  SIGNAL nxt_xon_reg : STD_LOGIC;
132
 
133
  SIGNAL rd_siso     : t_dp_siso;
134
  SIGNAL rd_sosi     : t_dp_sosi := c_dp_sosi_rst;  -- initialize default values for unused sosi fields;
135
 
136
  SIGNAL wr_fifo_usedw  : STD_LOGIC_VECTOR(c_fifo_size_w-1 DOWNTO 0);  -- = wr_usedw'RANGE
137
  SIGNAL rd_fifo_usedw  : STD_LOGIC_VECTOR(c_fifo_size_w-1 DOWNTO 0);  -- = rd_usedw'RANGE
138
  SIGNAL rd_fill_ctrl   : STD_LOGIC_VECTOR(c_fifo_size_w-1 DOWNTO 0);  -- used to resize rd_fill_32b to actual maximum width
139
 
140
  SIGNAL i_src_out   : t_dp_sosi;
141
  SIGNAL nxt_src_out : t_dp_sosi;
142
 
143
  -- Signals for g_fifo_rl=1
144
  SIGNAL hold_src_in  : t_dp_siso;
145
  SIGNAL pend_src_out : t_dp_sosi;
146
 
147
BEGIN
148
 
149
  -- Output monitor FIFO filling
150
  wr_usedw <= wr_fifo_usedw;
151
  rd_usedw <= rd_fifo_usedw;
152
 
153
  -- Control FIFO fill level
154
  wr_usedw_32b <= RESIZE_UVEC(wr_fifo_usedw, c_word_w);
155
  rd_usedw_32b <= RESIZE_UVEC(rd_fifo_usedw, c_word_w);
156
 
157
  rd_fill_ctrl <= rd_fill_32b(c_fifo_size_w-1 DOWNTO 0);
158
 
159
  gen_dp_fifo_sc : IF g_use_dual_clock=FALSE GENERATE
160
    u_dp_fifo_sc : ENTITY work.dp_fifo_sc
161
    GENERIC MAP (
162
      g_technology     => g_technology,
163
      g_data_w         => g_data_w,
164
      g_bsn_w          => g_bsn_w,
165
      g_empty_w        => g_empty_w,
166
      g_channel_w      => g_channel_w,
167
      g_error_w        => g_error_w,
168
      g_use_bsn        => g_use_bsn,
169
      g_use_empty      => g_use_empty,
170
      g_use_channel    => g_use_channel,
171
      g_use_error      => g_use_error,
172
      g_use_sync       => g_use_sync,
173
      g_use_ctrl       => c_use_ctrl,
174
      g_use_complex    => g_use_complex,
175
      g_fifo_size      => c_fifo_size,
176
      g_fifo_af_margin => g_fifo_af_margin,
177
      g_fifo_rl        => c_fifo_rl
178
    )
179
    PORT MAP (
180
      rst         => rd_rst,
181
      clk         => rd_clk,
182
      -- Monitor FIFO filling
183
      wr_ful      => wr_ful,
184
      usedw       => rd_fifo_usedw,
185
      rd_emp      => rd_emp,
186
      -- ST sink
187
      snk_out     => snk_out,
188
      snk_in      => snk_in,
189
      -- ST source
190
      src_in      => rd_siso,  -- for RL = 0 rd_siso.ready acts as read acknowledge, for RL = 1 rd_siso.ready acts as read request
191
      src_out     => rd_sosi
192
    );
193
 
194
    wr_fifo_usedw <= rd_fifo_usedw;
195
  END GENERATE;
196
 
197
  gen_dp_fifo_dc : IF g_use_dual_clock=TRUE GENERATE
198
    u_dp_fifo_dc : ENTITY work.dp_fifo_dc
199
    GENERIC MAP (
200
      g_technology     => g_technology,
201
      g_data_w         => g_data_w,
202
      g_bsn_w          => g_bsn_w,
203
      g_empty_w        => g_empty_w,
204
      g_channel_w      => g_channel_w,
205
      g_error_w        => g_error_w,
206
      g_use_bsn        => g_use_bsn,
207
      g_use_empty      => g_use_empty,
208
      g_use_channel    => g_use_channel,
209
      g_use_error      => g_use_error,
210
      g_use_sync       => g_use_sync,
211
      g_use_ctrl       => c_use_ctrl,
212
      --g_use_complex    => g_use_complex,
213
      g_fifo_size      => c_fifo_size,
214
      g_fifo_af_margin => g_fifo_af_margin,
215
      g_fifo_rl        => c_fifo_rl
216
    )
217
    PORT MAP (
218
      wr_rst      => wr_rst,
219
      wr_clk      => wr_clk,
220
      rd_rst      => rd_rst,
221
      rd_clk      => rd_clk,
222
      -- Monitor FIFO filling
223
      wr_ful      => wr_ful,
224
      wr_usedw    => wr_fifo_usedw,
225
      rd_usedw    => rd_fifo_usedw,
226
      rd_emp      => rd_emp,
227
      -- ST sink
228
      snk_out     => snk_out,
229
      snk_in      => snk_in,
230
      -- ST source
231
      src_in      => rd_siso,  -- for RL = 0 rd_siso.ready acts as read acknowledge, -- for RL = 1 rd_siso.ready acts as read request
232
      src_out     => rd_sosi
233
    );
234
  END GENERATE;
235
 
236
  no_fill : IF g_fifo_fill=0 GENERATE
237
    rd_siso <= src_in;   -- SISO
238
    src_out <= rd_sosi;  -- SOSI
239
  END GENERATE;  -- no_fill
240
 
241
  gen_fill : IF g_fifo_fill>0 GENERATE
242
 
243
    src_out <= i_src_out;
244
 
245
    p_rd_clk: PROCESS(rd_clk, rd_rst)
246
    BEGIN
247
      IF rd_rst='1' THEN
248
        xon_reg   <= '0';
249
        state     <= s_idle;
250
        i_src_out <= c_dp_sosi_rst;
251
      ELSIF rising_edge(rd_clk) THEN
252
        xon_reg   <= nxt_xon_reg;
253
        state     <= nxt_state;
254
        i_src_out <= nxt_src_out;
255
      END IF;
256
    END PROCESS;
257
 
258
    nxt_xon_reg <= src_in.xon;  -- register xon to easy timing closure
259
 
260
    gen_rl_0 : IF g_fifo_rl=0 GENERATE
261
      p_state : PROCESS(state, rd_sosi, src_in, xon_reg, rd_fifo_usedw, rd_fill_ctrl)
262
      BEGIN
263
        nxt_state <= state;
264
 
265
        rd_siso <= src_in;  -- default acknowledge (RL=1) this input when output is ready
266
 
267
        -- The output register stage increase RL=0 to 1, so it matches RL = 1 for src_in.ready
268
        nxt_src_out       <= rd_sosi;
269
        nxt_src_out.valid <= '0';   -- default no output
270
        nxt_src_out.sop   <= '0';
271
        nxt_src_out.eop   <= '0';
272
        nxt_src_out.sync  <= '0';
273
 
274
        CASE state IS
275
          WHEN s_idle =>
276
            IF xon_reg='0' THEN
277
              nxt_state <= s_xoff;
278
            ELSE
279
              -- read the FIFO until the sop is pending at the output, so discard any valid data between eop and sop
280
              IF rd_sosi.sop='0' THEN
281
                rd_siso <= c_dp_siso_rdy;   -- acknowledge (RL=0) this input independent of output ready
282
              ELSE
283
                rd_siso <= c_dp_siso_hold;  -- stop the input, hold the rd_sosi.sop at FIFO output (RL=0)
284
                nxt_state <= s_fill;
285
              END IF;
286
            END IF;
287
          WHEN s_fill =>
288
            IF xon_reg='0' THEN
289
              nxt_state <= s_xoff;
290
            ELSE
291
              -- stop reading until the FIFO has been filled sufficiently
292
              IF UNSIGNED(rd_fifo_usedw)<UNSIGNED(rd_fill_ctrl) THEN
293
                rd_siso <= c_dp_siso_hold;  -- stop the input, hold the pend_src_out.sop
294
              ELSE
295
                -- if the output is ready, then start outputting the frame
296
                IF src_in.ready='1' THEN
297
                  nxt_src_out <= rd_sosi;  -- output sop that is still at FIFO output (RL=0)
298
                  nxt_state <= s_output;
299
                END IF;
300
              END IF;
301
            END IF;
302
          WHEN s_output =>
303
            -- if the output is ready continue outputting the frame, ignore xon_reg during this frame
304
            IF src_in.ready='1' THEN
305
              nxt_src_out <= rd_sosi;  -- output valid
306
              IF rd_sosi.eop='1' THEN
307
                nxt_state <= s_idle;   -- output eop, so stop reading the FIFO
308
              END IF;
309
            END IF;
310
          WHEN OTHERS => -- s_xoff
311
            -- Flush the fill FIFO when xon='0'
312
            rd_siso <= c_dp_siso_flush;
313
            IF xon_reg='1' THEN
314
              nxt_state <= s_idle;
315
            END IF;
316
        END CASE;
317
 
318
        -- Pass on frame level flow control
319
        rd_siso.xon <= src_in.xon;
320
      END PROCESS;
321
    END GENERATE;  -- gen_rl_0
322
 
323
    gen_rl_1 : IF g_fifo_rl=1 GENERATE
324
      -- Use dp_hold_input to get equivalent implementation with default RL=1 FIFO.
325
 
326
      -- Hold the sink input for source output
327
      u_snk : ENTITY dp_components_lib.dp_hold_input
328
      PORT MAP (
329
        rst          => rd_rst,
330
        clk          => rd_clk,
331
        -- ST sink
332
        snk_out      => rd_siso,       -- SISO ready
333
        snk_in       => rd_sosi,       -- SOSI
334
        -- ST source
335
        src_in       => hold_src_in,   -- SISO ready
336
        next_src_out => OPEN,          -- SOSI
337
        pend_src_out => pend_src_out,
338
        src_out_reg  => i_src_out
339
      );
340
 
341
      p_state : PROCESS(state, src_in, xon_reg, pend_src_out, rd_fifo_usedw, rd_fill_ctrl)
342
      BEGIN
343
        nxt_state <= state;
344
 
345
        hold_src_in <= src_in;  -- default request (RL=1) new input when output is ready
346
 
347
        -- The output register stage matches RL = 1 for src_in.ready
348
        nxt_src_out       <= pend_src_out;
349
        nxt_src_out.valid <= '0';          -- default no output
350
        nxt_src_out.sop   <= '0';
351
        nxt_src_out.eop   <= '0';
352
        nxt_src_out.sync  <= '0';
353
 
354
        CASE state IS
355
          WHEN s_idle =>
356
            IF xon_reg='0' THEN
357
              nxt_state <= s_xoff;
358
            ELSE
359
              -- read the FIFO until the sop is pending at the output, so discard any valid data between eop and sop
360
              IF pend_src_out.sop='0' THEN
361
                hold_src_in <= c_dp_siso_rdy;   -- request (RL=1) new input independent of output ready
362
              ELSE
363
                hold_src_in <= c_dp_siso_hold;  -- stop the input, hold the pend_src_out.sop in dp_hold_input
364
                nxt_state <= s_fill;
365
              END IF;
366
            END IF;
367
          WHEN s_fill =>
368
            IF xon_reg='0' THEN
369
              nxt_state <= s_xoff;
370
            ELSE
371
              -- stop reading until the FIFO has been filled sufficiently
372
              IF UNSIGNED(rd_fifo_usedw)<UNSIGNED(rd_fill_ctrl) THEN
373
                hold_src_in <= c_dp_siso_hold;  -- stop the input, hold the pend_src_out.sop
374
              ELSE
375
                -- if the output is ready, then start outputting the input frame
376
                IF src_in.ready='1' THEN
377
                  nxt_src_out <= pend_src_out;  -- output sop that is still pending in dp_hold_input
378
                  nxt_state <= s_output;
379
                END IF;
380
              END IF;
381
            END IF;
382
          WHEN s_output =>
383
            -- if the output is ready continue outputting the input frame, ignore xon_reg during this frame
384
            IF src_in.ready='1' THEN
385
              nxt_src_out <= pend_src_out;  -- output valid
386
              IF pend_src_out.eop='1' THEN
387
                nxt_state <= s_idle;        -- output eop, so stop reading the FIFO
388
              END IF;
389
            END IF;
390
          WHEN OTHERS => -- s_xon
391
            -- Flush the fill FIFO when xon='0'
392
            hold_src_in <= c_dp_siso_flush;
393
            IF xon_reg='1' THEN
394
              nxt_state <= s_idle;
395
            END IF;
396
        END CASE;
397
 
398
        -- Pass on frame level flow control
399
        hold_src_in.xon <= src_in.xon;
400
      END PROCESS;
401
    END GENERATE;  -- gen_rl_1
402
 
403
  END GENERATE;  -- gen_fill
404
END rtl;

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