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[/] [astron_fifo/] [trunk/] [tech_fifo_component_pkg.vhd] - Blame information for rev 3

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1 2 danv 
-------------------------------------------------------------------------------
2 
--
3 3 danv 
-- Copyright 2020
4 2 danv 
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
6 3 danv 
--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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--     http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
18 2 danv 
--
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-------------------------------------------------------------------------------
20 
 
21 
-- Purpose: IP components declarations for various devices that get wrapped by the tech components
22 
 
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LIBRARY IEEE, technology_lib;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE technology_lib.technology_pkg.ALL;
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PACKAGE tech_fifo_component_pkg IS
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  -----------------------------------------------------------------------------
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  -- ip_stratixiv
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  -----------------------------------------------------------------------------
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  COMPONENT ip_stratixiv_fifo_sc IS
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  GENERIC (
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    g_use_eab    : STRING := "ON";
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    g_dat_w      : NATURAL;
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    g_nof_words  : NATURAL
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  );
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  PORT (
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    aclr  : IN STD_LOGIC;
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    clock : IN STD_LOGIC;
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    data  : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
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    rdreq : IN STD_LOGIC;
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    wrreq : IN STD_LOGIC;
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    empty : OUT STD_LOGIC;
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    full  : OUT STD_LOGIC;
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    q     : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
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    usedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
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  );
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  END COMPONENT;
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  COMPONENT ip_stratixiv_fifo_dc IS
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  GENERIC (
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    g_dat_w      : NATURAL;
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    g_nof_words  : NATURAL
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  );
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  PORT (
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    aclr    : IN STD_LOGIC  := '0';
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    data    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
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    rdclk   : IN STD_LOGIC;
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    rdreq   : IN STD_LOGIC;
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    wrclk   : IN STD_LOGIC;
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    wrreq   : IN STD_LOGIC;
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    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
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    rdempty : OUT STD_LOGIC;
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    rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
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    wrfull  : OUT STD_LOGIC;
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    wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
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  );
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  END COMPONENT;
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  COMPONENT ip_stratixiv_fifo_dc_mixed_widths IS
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  GENERIC (
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    g_nof_words  : NATURAL;  -- FIFO size in nof wr_dat words
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    g_wrdat_w    : NATURAL;
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    g_rddat_w    : NATURAL
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  );
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  PORT (
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    aclr    : IN STD_LOGIC  := '0';
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    data    : IN STD_LOGIC_VECTOR (g_wrdat_w-1 DOWNTO 0);
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    rdclk   : IN STD_LOGIC;
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    rdreq   : IN STD_LOGIC;
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    wrclk   : IN STD_LOGIC;
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    wrreq   : IN STD_LOGIC;
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    q       : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
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    rdempty : OUT STD_LOGIC;
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    rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
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    wrfull  : OUT STD_LOGIC;
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    wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
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  );
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  END COMPONENT;
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93 
 
94 
--  -----------------------------------------------------------------------------
95 
--  -- ip_arria10
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--  -----------------------------------------------------------------------------
97 
--
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--  COMPONENT ip_arria10_fifo_sc IS
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--  GENERIC (
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--    g_use_eab   : STRING := "ON";
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--    g_dat_w     : NATURAL := 20;
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--    g_nof_words : NATURAL := 1024
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--  );
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--  PORT (
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--    aclr    : IN STD_LOGIC ;
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--    clock   : IN STD_LOGIC ;
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--    data    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
108 
--    rdreq   : IN STD_LOGIC ;
109 
--    wrreq   : IN STD_LOGIC ;
110 
--    empty   : OUT STD_LOGIC ;
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--    full    : OUT STD_LOGIC ;
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--    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
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--    usedw   : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
114 
--  );
115 
--  END COMPONENT;
116 
--
117 
--  COMPONENT ip_arria10_fifo_dc IS
118 
--  GENERIC (
119 
--    g_use_eab   : STRING := "ON";
120 
--    g_dat_w     : NATURAL := 20;
121 
--    g_nof_words : NATURAL := 1024
122 
--  );
123 
--  PORT (
124 
--    aclr    : IN STD_LOGIC  := '0';
125 
--    data    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
126 
--    rdclk   : IN STD_LOGIC ;
127 
--    rdreq   : IN STD_LOGIC ;
128 
--    wrclk   : IN STD_LOGIC ;
129 
--    wrreq   : IN STD_LOGIC ;
130 
--    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
131 
--    rdempty : OUT STD_LOGIC ;
132 
--    rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
133 
--    wrfull  : OUT STD_LOGIC ;
134 
--    wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
135 
--  );
136 
--  END COMPONENT;
137 
--
138 
--  COMPONENT ip_arria10_fifo_dc_mixed_widths IS
139 
--  GENERIC (
140 
--    g_nof_words : NATURAL := 1024;  -- FIFO size in nof wr_dat words
141 
--    g_wrdat_w   : NATURAL := 20;
142 
--    g_rddat_w   : NATURAL := 10
143 
--  );
144 
--  PORT (
145 
--    aclr    : IN STD_LOGIC  := '0';
146 
--    data    : IN STD_LOGIC_VECTOR (g_wrdat_w-1 DOWNTO 0);
147 
--    rdclk   : IN STD_LOGIC ;
148 
--    rdreq   : IN STD_LOGIC ;
149 
--    wrclk   : IN STD_LOGIC ;
150 
--    wrreq   : IN STD_LOGIC ;
151 
--    q       : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
152 
--    rdempty : OUT STD_LOGIC ;
153 
--    rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
154 
--    wrfull  : OUT STD_LOGIC ;
155 
--    wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
156 
--  );
157 
--  END COMPONENT;
158 
--
159 
--  -----------------------------------------------------------------------------
160 
--  -- ip_arria10_e3sge3
161 
--  -----------------------------------------------------------------------------
162 
--
163 
--  COMPONENT ip_arria10_e3sge3_fifo_sc IS
164 
--  GENERIC (
165 
--    g_use_eab   : STRING := "ON";
166 
--    g_dat_w     : NATURAL := 20;
167 
--    g_nof_words : NATURAL := 1024
168 
--  );
169 
--  PORT (
170 
--    aclr    : IN STD_LOGIC ;
171 
--    clock   : IN STD_LOGIC ;
172 
--    data    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
173 
--    rdreq   : IN STD_LOGIC ;
174 
--    wrreq   : IN STD_LOGIC ;
175 
--    empty   : OUT STD_LOGIC ;
176 
--    full    : OUT STD_LOGIC ;
177 
--    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
178 
--    usedw   : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
179 
--  );
180 
--  END COMPONENT;
181 
--
182 
--  COMPONENT ip_arria10_e3sge3_fifo_dc IS
183 
--  GENERIC (
184 
--    g_use_eab   : STRING := "ON";
185 
--    g_dat_w     : NATURAL := 20;
186 
--    g_nof_words : NATURAL := 1024
187 
--  );
188 
--  PORT (
189 
--    aclr    : IN STD_LOGIC  := '0';
190 
--    data    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
191 
--    rdclk   : IN STD_LOGIC ;
192 
--    rdreq   : IN STD_LOGIC ;
193 
--    wrclk   : IN STD_LOGIC ;
194 
--    wrreq   : IN STD_LOGIC ;
195 
--    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
196 
--    rdempty : OUT STD_LOGIC ;
197 
--    rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
198 
--    wrfull  : OUT STD_LOGIC ;
199 
--    wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
200 
--  );
201 
--  END COMPONENT;
202 
--
203 
--  COMPONENT ip_arria10_e3sge3_fifo_dc_mixed_widths IS
204 
--  GENERIC (
205 
--    g_nof_words : NATURAL := 1024;  -- FIFO size in nof wr_dat words
206 
--    g_wrdat_w   : NATURAL := 20;
207 
--    g_rddat_w   : NATURAL := 10
208 
--  );
209 
--  PORT (
210 
--    aclr    : IN STD_LOGIC  := '0';
211 
--    data    : IN STD_LOGIC_VECTOR (g_wrdat_w-1 DOWNTO 0);
212 
--    rdclk   : IN STD_LOGIC ;
213 
--    rdreq   : IN STD_LOGIC ;
214 
--    wrclk   : IN STD_LOGIC ;
215 
--    wrreq   : IN STD_LOGIC ;
216 
--    q       : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
217 
--    rdempty : OUT STD_LOGIC ;
218 
--    rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
219 
--    wrfull  : OUT STD_LOGIC ;
220 
--    wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
221 
--  );
222 
--  END COMPONENT;
223 
--
224 
--  -----------------------------------------------------------------------------
225 
--  -- ip_arria10_e1sg
226 
--  -----------------------------------------------------------------------------
227 
--
228 
--  COMPONENT ip_arria10_e1sg_fifo_sc IS
229 
--  GENERIC (
230 
--    g_use_eab   : STRING := "ON";
231 
--    g_dat_w     : NATURAL := 20;
232 
--    g_nof_words : NATURAL := 1024
233 
--  );
234 
--  PORT (
235 
--    aclr    : IN STD_LOGIC ;
236 
--    clock   : IN STD_LOGIC ;
237 
--    data    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
238 
--    rdreq   : IN STD_LOGIC ;
239 
--    wrreq   : IN STD_LOGIC ;
240 
--    empty   : OUT STD_LOGIC ;
241 
--    full    : OUT STD_LOGIC ;
242 
--    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
243 
--    usedw   : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
244 
--  );
245 
--  END COMPONENT;
246 
--
247 
--  COMPONENT ip_arria10_e1sg_fifo_dc IS
248 
--  GENERIC (
249 
--    g_use_eab   : STRING := "ON";
250 
--    g_dat_w     : NATURAL := 20;
251 
--    g_nof_words : NATURAL := 1024
252 
--  );
253 
--  PORT (
254 
--    aclr    : IN STD_LOGIC  := '0';
255 
--    data    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
256 
--    rdclk   : IN STD_LOGIC ;
257 
--    rdreq   : IN STD_LOGIC ;
258 
--    wrclk   : IN STD_LOGIC ;
259 
--    wrreq   : IN STD_LOGIC ;
260 
--    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
261 
--    rdempty : OUT STD_LOGIC ;
262 
--    rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
263 
--    wrfull  : OUT STD_LOGIC ;
264 
--    wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
265 
--  );
266 
--  END COMPONENT;
267 
--
268 
--  COMPONENT ip_arria10_e1sg_fifo_dc_mixed_widths IS
269 
--  GENERIC (
270 
--    g_nof_words : NATURAL := 1024;  -- FIFO size in nof wr_dat words
271 
--    g_wrdat_w   : NATURAL := 20;
272 
--    g_rddat_w   : NATURAL := 10
273 
--  );
274 
--  PORT (
275 
--    aclr    : IN STD_LOGIC  := '0';
276 
--    data    : IN STD_LOGIC_VECTOR (g_wrdat_w-1 DOWNTO 0);
277 
--    rdclk   : IN STD_LOGIC ;
278 
--    rdreq   : IN STD_LOGIC ;
279 
--    wrclk   : IN STD_LOGIC ;
280 
--    wrreq   : IN STD_LOGIC ;
281 
--    q       : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
282 
--    rdempty : OUT STD_LOGIC ;
283 
--    rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
284 
--    wrfull  : OUT STD_LOGIC ;
285 
--    wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
286 
--  );
287 
--  END COMPONENT;
288 
 
289 
 
290 
END tech_fifo_component_pkg;

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