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-------------------------------------------------------------------------------
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--
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-- Copyright (C) 2009
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-------------------------------------------------------------------------------
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-- Purpose: Controlling the data streams for the filter units
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--
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-- Description: This unit prepairs the data streams for the ppf_filter
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-- unit. Incoming data (in_dat) is combined with stored
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-- data (taps_in_vec) to generate a new vector that is
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-- offered to the filter unit: taps_out_vec.
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--
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-- It also delays the in_val signal in order to generate
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-- the out_val that is proper alligned with the output data
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-- that is coming from the filter unit.
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--
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library IEEE, common_pkg_lib;
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use IEEE.std_logic_1164.ALL;
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use IEEE.numeric_std.ALL;
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use common_pkg_lib.common_pkg.ALL;
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use work.fil_pkg.ALL;
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entity fil_ppf_ctrl is
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generic (
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g_fil_ppf : t_fil_ppf;
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g_fil_ppf_pipeline : t_fil_ppf_pipeline
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);
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port (
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rst : in std_logic := '0';
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clk : in std_logic;
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in_dat : in std_logic_vector;
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in_val : in std_logic;
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taps_in_vec : in std_logic_vector;
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taps_rdaddr : out std_logic_vector;
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taps_wraddr : out std_logic_vector;
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taps_wren : out std_logic;
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taps_out_vec: out std_logic_vector;
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out_val : out std_logic
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);
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end fil_ppf_ctrl;
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architecture rtl of fil_ppf_ctrl is
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type t_in_dat_delay is array (g_fil_ppf_pipeline.mem_delay downto 0) of std_logic_vector(g_fil_ppf.in_dat_w*g_fil_ppf.nof_streams-1 downto 0);
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constant c_addr_w : natural := ceil_log2(g_fil_ppf.nof_bands * (2**g_fil_ppf.nof_chan));
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constant c_ctrl_latency : natural := 1; -- due to taps_out_vec register
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constant c_mult_latency : natural := g_fil_ppf_pipeline.mult_input + g_fil_ppf_pipeline.mult_product + g_fil_ppf_pipeline.mult_output;
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constant c_adder_latency : natural := ceil_log2(g_fil_ppf.nof_taps) * g_fil_ppf_pipeline.adder_stage;
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constant c_filter_zdly : natural := g_fil_ppf.nof_bands * (2**g_fil_ppf.nof_chan);
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constant c_tot_latency : natural := g_fil_ppf_pipeline.mem_delay + c_ctrl_latency + c_mult_latency +
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c_adder_latency + g_fil_ppf_pipeline.requant_remove_lsb +
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g_fil_ppf_pipeline.requant_remove_msb;
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constant c_single_taps_vec_w : natural := g_fil_ppf.in_dat_w*g_fil_ppf.nof_taps;
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constant c_taps_vec_w : natural := c_single_taps_vec_w*g_fil_ppf.nof_streams;
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type reg_type is record
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in_dat_arr : t_in_dat_delay; -- Input register for the data
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init_dly_cnt : integer range 0 to c_filter_zdly; -- Counter used to overcome the settling time of the filter.
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val_dly : std_logic_vector(c_tot_latency-1 downto 0); -- Delay register for the valid signal
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rd_addr : std_logic_vector(c_addr_w-1 downto 0); -- The read address
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wr_addr : std_logic_vector(c_addr_w-1 downto 0); -- The write address
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wr_en : std_logic; -- Write enable signal for the taps memory
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taps_out_vec : std_logic_vector(c_taps_vec_w-1 downto 0); -- Output register containing the next taps data
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out_val_ena : std_logic; -- Output enable
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end record;
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signal r, rin : reg_type;
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begin
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comb : process(r, rst, in_val, in_dat, taps_in_vec)
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variable v : reg_type;
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begin
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v := r;
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v.wr_en := '0';
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-- Perform the shifting for the shiftregister for the valid signal and the input data:
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v.val_dly(0) := in_val;
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v.val_dly(c_tot_latency-1 downto 1) := r.val_dly(c_tot_latency-2 downto 0);
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v.in_dat_arr(0) := RESIZE_SVEC(in_dat, r.in_dat_arr(0)'LENGTH);
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v.in_dat_arr(g_fil_ppf_pipeline.mem_delay downto 1) := r.in_dat_arr(g_fil_ppf_pipeline.mem_delay-1 downto 0);
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if(r.val_dly(0) = '1') then -- Wait for incoming data
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v.rd_addr := INCR_UVEC(r.rd_addr, 1);
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end if;
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if(r.val_dly(c_tot_latency-2) = '1') then -- Wait for incoming data
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if(r.init_dly_cnt < c_filter_zdly) then
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v.init_dly_cnt := r.init_dly_cnt + 1;
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v.out_val_ena := '0';
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else
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v.out_val_ena := '1';
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end if;
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end if;
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if(r.val_dly(g_fil_ppf_pipeline.mem_delay+1) = '1') then
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v.wr_addr := INCR_UVEC(r.wr_addr, 1);
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end if;
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if(r.val_dly(g_fil_ppf_pipeline.mem_delay) = '1') then
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for I in 0 to g_fil_ppf.nof_streams-1 loop
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v.taps_out_vec((I+1)*c_single_taps_vec_w-1 downto I*c_single_taps_vec_w) := taps_in_vec((I+1)*c_single_taps_vec_w - g_fil_ppf.in_dat_w -1 downto I*c_single_taps_vec_w) & r.in_dat_arr(g_fil_ppf_pipeline.mem_delay)((I+1)*g_fil_ppf.in_dat_w-1 downto I*g_fil_ppf.in_dat_w);
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end loop;
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--v.taps_out_vec := taps_in_vec(taps_in_vec'HIGH - g_fil_ppf.in_dat_w downto 0) & r.in_dat_arr(g_fil_ppf_pipeline.mem_delay);
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v.wr_en := '1';
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end if;
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if(rst = '1') then
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v.init_dly_cnt := 0;
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v.in_dat_arr := (others => (others => '0'));
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v.val_dly := (others => '0');
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v.rd_addr := (others => '0');
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v.wr_addr := (others => '0');
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v.wr_en := '0';
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v.taps_out_vec := (others => '0');
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v.out_val_ena := '0';
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end if;
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rin <= v;
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end process comb;
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regs : process(clk)
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begin
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if rising_edge(clk) then
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r <= rin;
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end if;
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end process;
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taps_rdaddr <= r.rd_addr;
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taps_wraddr <= r.wr_addr;
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taps_wren <= r.wr_en;
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taps_out_vec <= r.taps_out_vec;
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out_val <= r.val_dly(c_tot_latency-1) AND r.out_val_ena;
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end rtl;
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