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-------------------------------------------------------------------------------
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--
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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-------------------------------------------------------------------------------
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LIBRARY IEEE, common_pkg_lib, dp_pkg_lib;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE dp_pkg_lib.dp_stream_pkg.ALL;
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USE dp_pkg_lib.tb_dp_pkg.ALL;
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ENTITY tb_dp_pipeline IS
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GENERIC (
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g_pipeline : NATURAL := 5
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);
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END tb_dp_pipeline;
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ARCHITECTURE tb OF tb_dp_pipeline IS
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-- See tb_dp_pkg.vhd for explanation and run time
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-- DUT ready latency
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CONSTANT c_dut_latency : NATURAL := 1; -- fixed 1 for dp_pipeline
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CONSTANT c_tx_latency : NATURAL := c_dut_latency; -- TX ready latency of TB
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CONSTANT c_tx_void : NATURAL := sel_a_b(c_tx_latency, 1, 0); -- used to avoid empty range VHDL warnings when c_tx_latency=0
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CONSTANT c_tx_offset_sop : NATURAL := 3;
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CONSTANT c_tx_period_sop : NATURAL := 7; -- sop in data valid cycle 3, 10, 17, ...
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CONSTANT c_tx_offset_eop : NATURAL := 5; -- eop in data valid cycle 5, 12, 19, ...
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CONSTANT c_tx_period_eop : NATURAL := c_tx_period_sop;
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CONSTANT c_tx_offset_sync : NATURAL := 3; -- sync in data valid cycle 3, 20, 37, ...
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CONSTANT c_tx_period_sync : NATURAL := 17;
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CONSTANT c_rx_latency : NATURAL := c_dut_latency; -- RX ready latency from DUT
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CONSTANT c_verify_en_wait : NATURAL := 4+g_pipeline; -- wait some cycles before asserting verify enable
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CONSTANT c_random_w : NATURAL := 19;
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SIGNAL tb_end : STD_LOGIC := '0';
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SIGNAL clk : STD_LOGIC := '0';
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SIGNAL rst : STD_LOGIC;
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SIGNAL sync : STD_LOGIC;
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SIGNAL lfsr1 : STD_LOGIC_VECTOR(c_random_w-1 DOWNTO 0) := (OTHERS=>'0');
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SIGNAL lfsr2 : STD_LOGIC_VECTOR(c_random_w DOWNTO 0) := (OTHERS=>'0');
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SIGNAL cnt_dat : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0);
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SIGNAL cnt_val : STD_LOGIC;
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SIGNAL cnt_en : STD_LOGIC;
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SIGNAL tx_data : t_dp_data_arr(0 TO c_tx_latency + c_tx_void) := (OTHERS=>(OTHERS=>'0'));
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SIGNAL tx_val : STD_LOGIC_VECTOR(0 TO c_tx_latency + c_tx_void) := (OTHERS=>'0');
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SIGNAL in_ready : STD_LOGIC;
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SIGNAL in_data : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := (OTHERS=>'0');
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SIGNAL in_sync : STD_LOGIC;
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SIGNAL in_val : STD_LOGIC;
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SIGNAL in_sop : STD_LOGIC;
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SIGNAL in_eop : STD_LOGIC;
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SIGNAL in_siso : t_dp_siso;
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SIGNAL in_sosi : t_dp_sosi := c_dp_sosi_rst;
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SIGNAL out_siso : t_dp_siso;
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SIGNAL out_sosi : t_dp_sosi;
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SIGNAL out_ready : STD_LOGIC;
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SIGNAL prev_out_ready : STD_LOGIC_VECTOR(0 TO c_rx_latency);
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SIGNAL out_data : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0);
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SIGNAL out_sync : STD_LOGIC;
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SIGNAL out_val : STD_LOGIC;
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SIGNAL out_sop : STD_LOGIC;
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SIGNAL out_eop : STD_LOGIC;
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SIGNAL hold_out_sop : STD_LOGIC;
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SIGNAL prev_out_data : STD_LOGIC_VECTOR(out_data'RANGE);
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SIGNAL state : t_dp_state_enum;
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SIGNAL verify_en : STD_LOGIC;
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SIGNAL verify_done : STD_LOGIC;
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SIGNAL exp_data : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := TO_UVEC(sel_a_b(g_pipeline=0, 18953, 18952), c_dp_data_w);
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BEGIN
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clk <= NOT clk OR tb_end AFTER clk_period/2;
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rst <= '1', '0' AFTER clk_period*7;
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-- Sync interval
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proc_dp_sync_interval(clk, sync);
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-- Input data
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cnt_val <= in_ready AND cnt_en;
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proc_dp_cnt_dat(rst, clk, cnt_val, cnt_dat);
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proc_dp_tx_data(c_tx_latency, rst, clk, cnt_val, cnt_dat, tx_data, tx_val, in_data, in_val);
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proc_dp_tx_ctrl(c_tx_offset_sync, c_tx_period_sync, in_data, in_val, in_sync);
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proc_dp_tx_ctrl(c_tx_offset_sop, c_tx_period_sop, in_data, in_val, in_sop);
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proc_dp_tx_ctrl(c_tx_offset_eop, c_tx_period_eop, in_data, in_val, in_eop);
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-- Stimuli control
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proc_dp_count_en(rst, clk, sync, lfsr1, state, verify_done, tb_end, cnt_en);
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proc_dp_out_ready(rst, clk, sync, lfsr2, out_ready);
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-- Output verify
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proc_dp_verify_en(c_verify_en_wait, rst, clk, sync, verify_en);
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proc_dp_verify_data("out_sosi.data", c_rx_latency, clk, verify_en, out_ready, out_val, out_data, prev_out_data);
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proc_dp_verify_valid(c_rx_latency, clk, verify_en, out_ready, prev_out_ready, out_val);
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proc_dp_verify_sop_and_eop(c_rx_latency, FALSE, clk, out_val, out_val, out_sop, out_eop, hold_out_sop); -- Verify that sop and eop come in pairs, no check on valid between eop and sop
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proc_dp_verify_ctrl(c_tx_offset_sync, c_tx_period_sync, "sync", clk, verify_en, out_data, out_val, out_sync);
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proc_dp_verify_ctrl(c_tx_offset_sop, c_tx_period_sop, "sop", clk, verify_en, out_data, out_val, out_sop);
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proc_dp_verify_ctrl(c_tx_offset_eop, c_tx_period_eop, "eop", clk, verify_en, out_data, out_val, out_eop);
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-- Check that the test has ran at all
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proc_dp_verify_value(e_equal, clk, verify_done, exp_data, out_data);
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------------------------------------------------------------------------------
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-- DUT dp_pipeline
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------------------------------------------------------------------------------
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-- map sl, slv to record
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in_ready <= in_siso.ready; -- SISO
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in_sosi.data(c_dp_data_w-1 DOWNTO 0) <= in_data; -- SOSI
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in_sosi.sync <= in_sync;
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in_sosi.valid <= in_val;
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in_sosi.sop <= in_sop;
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in_sosi.eop <= in_eop;
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out_siso.ready <= out_ready; -- SISO
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out_data <= out_sosi.data(c_dp_data_w-1 DOWNTO 0); -- SOSI
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out_sync <= out_sosi.sync;
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out_val <= out_sosi.valid;
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out_sop <= out_sosi.sop;
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out_eop <= out_sosi.eop;
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dut : ENTITY work.dp_pipeline
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GENERIC MAP (
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g_pipeline => g_pipeline
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)
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PORT MAP (
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rst => rst,
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clk => clk,
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snk_out => in_siso, -- OUT = request to upstream ST source
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snk_in => in_sosi,
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src_in => out_siso, -- IN = request from downstream ST sink
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src_out => out_sosi
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);
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END tb;
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