Subversion Repositories ata

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<B><FONT FACE="Helvetica,Arial" SIZE=+2 COLOR="#bf0000"><P>Project Name: OCIDEC (OpenCores IDE Controller)</P>

</FONT><U><FONT SIZE=4><P> Description:</B></U></FONT> </P>

<P>ATA (AT attachment) interface core, also known as the IDE (Integrated Drive Electronics) interface.<BR>

The ATA interface provides a simple interface to (low cost) non-volatile memories, like harddisk drives, DVD players, CD(ROM) players/writers and  CompactFlash and PC-CARD devices.</P>

<B><U><FONT SIZE=4><P>Development goals:</B></U></FONT> </P>

<P>The development of a range of software and function backward compatible cores with a growing set of features. Software can detect which version of the core is implemented by reading the Device-ID and Revision-Number from the status register, thus making it possible to use a single device driver to handle all cores. This gives designers/system integraters the ability to trade off complexity/resource usage to available feature set/performance. All cores are designed according to the latest ATA/ATAPI specs.</P>

<P>Currently three cores are available:</P>

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<P>Device</TD>

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<P>OCIDEC-1</TD>

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<P>Features</TD>

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<P>Smallest core.<BR>

PIO transfer support only.<BR>

Single timing register for all accesses to the connected devices.</TD>

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<P>Intended use</TD>

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<P>Single PIO only devices (PC-CARDs, CompactFlash).<BR>

Designs requiring ATA capabilities, without the need for a complex feature set.</TD>

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<P>Gate usage</TD>

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<P>Approximately 4Kgates.</TD>

</TR>

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<P>Device</TD>

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<P>OCIDEC-2</TD>

</TR>

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<P>Features</TD>

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<P>Small core.<BR>

PIO transfer support only.<BR>

Common timing register for all compatible accesses to the connected devices.<BR>

Separate timing register per device for fast DataPort accesses.</TD>

</TR>

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<P>Intended use</TD>

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<P>Dual PIO only devices (PC-CARDs, CompactFlash).<BR>

Designs requiring fast ATA capabilities, without DMA transfers.</TD>

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<P>Gate usage</TD>

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<P>Approximately 4.6Kgates.</TD>

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</TABLE>

<P><BR>

</P>

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<P>Device</TD>

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<P>OCIDEC-3</TD>

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<P>Features</TD>

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<P>PIO, Single-Word DMA and Multi-Word DMA transfer support.<BR>

Common timing register for all PIO compatible accesses to the connected devices.<BR>

Separate timing registers per device for fast PIO DataPort accesses.<BR>

Separate timing registers per device for DMA transfers.<BR>

PIO write access ping-pong.<BR>

WISHBONE Retry cycles for PIO accesses while controller busy.</TD>

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<P>Intended use</TD>

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<P>High speed ATA devices (Hard disks, CDROMs)<BR>

Designs requiring full featured ATA capabilities.</TD>

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<P>Gate usage</TD>

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<P>Approximately 14Kgates.</TD>

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<P>All cores feature a WISHBONE rev.B2 compliant interface, but can be addapted for any other kind of bus easy.<br>

See the on-line <A HREF="http://www.opencores.org/cores/ata/preliminary_ata_core.pdf">documentation</A> for more information. Note: This is a preliminary version. No official release.</P>

<B><U><FONT SIZE=4><P>Current Status:</B></U></FONT> </P>

<UL>

<LI>Three cores are available in VHDL and Verilog from OpenCores CVS via <A HREF="http://www.opencores.org/cvsweb.shtml/">cvsweb</A> or via <A HREF="/cvsmodule.shtml">cvsget</A>.</LI>

<LI>ToDo: </LI>

<UL>

<LI>Write documentation</LI>

<LI>Start development of OCIDEC-4, featuring UltraDMA support</LI></UL>

</UL>

<B><U><FONT SIZE=4><P>Author & Maintainer(s):</B></U></FONT> </P><DIR>

<P><A HREF="mailto:rherveille@opencores.org_NOSPAM">Richard Herveille</A><BR>

 </P></DIR>

<B><U><FONT SIZE=4><P>Mailing-list:</B></U></FONT> </P><DIR>

<P><A HREF="mailto:cores@opencores.org_NOSPAM">cores@opencores.org_NOSPAM</A></P></DIR>

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