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[/] [attiny_atmega_xmega_core/] [doc/] [README.md] - Blame information for rev 13

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# XMEGA_CORE_IP_V2
 
This is an optimized IP of the Atmel MEGA and XMEGA processor, that is very simple to use.
 
* The ROM address BUS and RAM address BUS length are parametrized but not less than 8bit each address BUS.
* The watchdog counter size is aparametrized, if you set 0 counter length the core will not use the watchdog.
* The number of lines of the interrupt controller is parametrized and if number of lines is set to 0 the interrupt controller is not used.
 
Now I add support for this core on CPP-SDK https://git.morgothdisk.com/C-CPP/MULTIPLATFORM-CPP-SDK/tree/master/ExampleXmega_FPGA .
 
 
Utilization report from implementation for CORE_TYPE_XMEGA with default settings:
 
|Resource | Utilization | Available | Utilization % |
|:--------|------------:|----------:|--------------:|
|`LUT`    | ~1166       |  20800    |  ~0.87        |
|`LUTRAM` |    32       |  46200    |   0.07        |
|`FF`     |   137       |  41600    |   0.05        |
|`BRAM`   |   2.5       |    365    |   0.68        |
|`IO`     |    13       |    285    |   4.56        |
|`PLL`    |     1       |     10    |     10        |
 
This results is with one parametrized paralel port connected to onboard LED's, 1KBytes of RAM, 4KWords * 16bit of ROM ( the configuration is setup to emulate one Xmega8E5 ) without watchdog and without interrupt module.
 
**********************************************************************************************************************
 
Utilization report from implementation for CORE_TYPE_XMEGA with default settings:
 
|Resource | Utilization | Available | Utilization % |
|:--------|------------:|----------:|--------------:|
|`LUT`    | ~1277       |  20800    |  ~0.95        |
|`LUTRAM` |    32       |  46200    |   0.07        |
|`FF`     |   263       |  41600    |   0.10        |
|`BRAM`   |   2.5       |    365    |   0.68        |
|`IO`     |    18       |    285    |   6.32        |
|`PLL`    |     1       |     10    |     10        |
 
This results is with two paralel ports, one input fully software configurable port and one output parametrized port connected to onboard LED's, 1KBytes of RAM, 4KWords * 16bit of ROM ( the configuration is setup to emulate one Xmega8E5 ) 1 interrupt source from port A.
 
**********************************************************************************************************************
 
Utilization report from implementation for CORE_TYPE_MINIMAL with default settings:
 
|Resource | Utilization | Available | Utilization % |
|:--------|------------:|----------:|--------------:|
|`LUT`    |  ~695       |  20800    |  ~0.52        |
|`LUTRAM` |    32       |  46200    |   0.07        |
|`FF`     |    98       |  41600    |   0.04        |
|`BRAM`   |   1.5       |    365    |   0.27        |
|`IO`     |    13       |    285    |   6.32        |
|`PLL`    |     1       |     10    |     10        |
 
This results is with one parametrized paralel port connected to onboard LED's, 128Bytes of RAM, 1KWords * 16bit of ROM ( the configuration is setup to emulate one Attiny26 ) without watchdog and without interrupt module.
 
**********************************************************************************************************************
 
Utilization report from implementation for CORE_TYPE_MINIMAL with default settings:
 
|Resource | Utilization | Available | Utilization % |
|:--------|------------:|----------:|--------------:|
|`LUT`    |  ~825       |  20800    |  ~0.62        |
|`LUTRAM` |    32       |  46200    |   0.07        |
|`FF`     |   226       |  41600    |   0.08        |
|`BRAM`   |   1.5       |    365    |   0.41        |
|`IO`     |    18       |    285    |   6.32        |
|`PLL`    |     1       |     10    |     10        |
 
This results is with two paralel ports, one input fully software configurable port and one output parametrized port connected to onboard LED's, 128Bytes of RAM, 1KWords * 16bit of ROM ( the configuration is setup to emulate one Attiny26 ) 1 interrupt source from port A.
 
**********************************************************************************************************************
 
More details about instruction set implementation of different core type you can read here: https://en.wikipedia.org/wiki/Atmel_AVR_instruction_set
 
The core is configurable from minimal core to XMEGA core using one CORE_TYPE parameter.
 
 
|Family|Members|Arithmetic|Branches|Transfers|Bit-Wise|
|:-----|:------|:---------|:-------|:--------|:-------|
|Minimal AVR1 Core|AT90S1200, ATtiny11, ATtiny12, ATtiny15, ATtiny28|ADD ADC SUB SUBI SBC SBCI AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER|RJMP RCALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID|LD ST MOV LDI IN OUT LPM (not in AT90S1200)|SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH NOP SLEEP WDR|
|Classic Core up to 8K Program Space|AT90S2313, AT90S2323, ATtiny22, AT90S2333, AT90S2343, AT90S4414, AT90S4433, AT90S4434, AT90S8515, AT90C8534, AT90S8535, ATtiny26|new instructions: ADIW SBIW|new instructions: IJMP ICALL|new instructions: LD (now 9 modes) LDD LDS ST (9 modes) STD STS PUSH POP|(nothing new)|
|Classic Core with up to 128K|ATmega103, ATmega603, AT43USB320, AT76C711|(nothing new)|new instructions: JMP CALL|new instructions: ELPM|(nothing new)|
|Enhanced Core with up to 8K|ATmega8, ATmega83, ATmega85, ATmega8515|new instructions:MUL MULS MULSU FMUL FMULS FMULSU[2]|(nothing new)|new instructions: MOVW LPM(3modes) SPM|(nothing new)|
|Enhanced Core with up to 128K|ATmega16, ATmega161, ATmega163, ATmega32, ATmega323, ATmega64, ATmega128, AT43USB355, AT94 (FPSLIC), AT90CAN series, AT90PWM series, ATmega48, ATmega88, ATmega168, ATmega162, ATtiny13, ATtiny25, ATtiny45, ATtiny85, ATtiny2313, ATmega164, ATmega324, ATmega328, ATmega644, ATmega165, ATmega169, ATmega325, ATmega3250, ATmega645, ATmega6450, ATmega406|(nothing new)|(nothing new)|(nothing new)|new instructions: BREAK|
|Enhanced Core with up to 4M|ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561|(nothing new)|new instructions:EIJMP EICALL|(nothing new)|(nothing new)|
|XMEGA Core|ATxmega series|new instructions:DES|(nothing new)|new instructions:(from second revision silicon - AU,B,C parts) XCH LAS LAC LAT|(nothing new)|
|Reduced AVRtiny Core|ATtiny40, ATtiny20, ATtiny10, ATtiny9, ATtiny5, ATtiny4|(Identical to minimal core, except for reduced CPU register set)|(Identical to classic core with up to 8K, except for reduced CPU register set)|Identical to classic core with up to 8K, with the following exceptions: LPM(removed) LDD(removed) STD(removed) LD(also accesses program memory) LDS(different bit pattern) STS(different bit pattern) Reduced CPU register set|(Identical to enhanced core with up to 128K, except for reduced CPU register set)|
 
 
 
At this moment has implemented the next instructions:
 
One clock cycle instructions:
 
* LDI
* MOVW
* MUL
* MULS
* FMUL
* FMULS
* MULSU
* FMULSU
* INC
* DEC
* ASR
* LSR
* ROR
* SUB
* SBC
* ADD
* ADC
* SWAP
* AND
* EOR
* OR
* MOV
* BLD
* SUBI
* SBCI
* ORI_SBR
* ANDI_CBR
* COM
* NEG
* ADIW
* SBIW
 
Two clock cycle instructions:
 
* JMP
* IJMP
* RCALL
* CALL
* ICALL
* PUSH
* POP
* LDS16
* STS
* STD
* ST_X
* ST_XP
* OUT
* IN
* CBI
* SBI
* LPM_R
 
Three clock cycle instructions:
 
* CPSE
* SBRC
* SBRS
* SBIC
* SBIS
* LDS
* LDD
* LD_YZP
* LD_YZN
* ST_YZN
* LD_X
* LD_XP
* LD_XN
* ST_XN
* LPM_R
* LPM_R_P
 
Four clock cycle instructions:
 
* RET
* RETI
 
******** Some changes has been made to the instruction execution timings and may differ from the above table.
 
**********************************************************************************************************************
 
The implementation project is made for NexysVideo from Digilent and core setup is XMEGA.
 
The next IO are connected to RAM bus:
 
* RTC IP located at addr 0x40, this can generate a period interrupt and is connected to line 0 of the interrupt controller.
* PIO IP port located at addr 0x60 input 5 buttons port, this port is parametrized to be dinamically configured by thru software commands and has connected and can generate one interrupt that is connected to line 1 of the interrupt controller.
* PIO IP port located at addr 0x80 switch inputs port, this port is parametrized to be configured using parameters and has connected and can generate one interrupt that is connected to line 2 of the interrupt controller.
* PIO IP port located at addr 0xA0 output port for LED's, this port is parametrized to be configured using parameters and has connected and can generate one interrupt that is connected to line 3 of the interrupt controller.
* PIO IP port located at addr 0xC0 this PIO is connected on the JA PMOD connector and can generate an interrupt that is connected to the line 4 of the interrupt controller.
* PIO IP port located at addr 0xE0 this PIO is connected on the JB PMOD connector and can generate an interrupt that is connected to the line 5 of the interrupt controller..
* PIO IP port located at addr 0x100 this PIO is connected on the JC PMOD connector and can generate an interrupt that is connected to the line 6 of the interrupt controller..
* SPI IP that is connected at addr 0x600, this module drive the Nexus Video onboard OLED display and can generate one interrupt that is connected to the line 7 of the interrupt controller.
* UART IP that is connected at addr 0x400, this module is parametrized to be dinamically configured thru software that has connected and can generate three interrupts: UART_RXC (Uart RX complete), UART_TXC (Uart TX complete), UART_DRE (Tx data register empty) that are connected to line 8, 9 and 10 of the interrupt controller.
* TWI IP that is connected at addr 0x800, this module is connected on JC1=SDA & JC3=SCL connector of the Nexis Video where is connected the PmodNAV board, The CppSDK example application read the LSM9DS1 device and dislay the results on onboard OLED display..
* GFX 2D simple accelerator at addr 0x300, this IP paint filled rectangles and single pixels with a speed of one pixel oc core clock.
* LCD IP pannel controller that has the BRAM VRAM configured in 8bit/color and is starting from address 0 of the microcontroller RAM, the LCD controller IP is parametrized to drive a 1440x900 display pannel at ~60Hz.
* HDMI IP serializer that is connected to the HDMI output connector of the NEXIS VIDEO board is drived by the LCD IP.
 
On this configuration if a PMODNAV 9-axis from Digilent is connected to JC PMOD connector it will display the values of the LSM9DS1 temperature, acceleration, giroscope and compass if the SW0 is down, and it will display the LPS25HB temperature and pressure if SW0 is up, on Onboard OLED display and on a HDMI display parametrized for a resolution of 1440x900 at 60HZ.
 
The current configuration is:
 
Clocks:
*    ~100Mhz core clock.
*    533.333Mhz HDMI IP clock that generate 106.666Mhz LCD IP clock.
 
Core configuration:
*   Configuration MEGA_XMEGA_1
*   Interrupt controller 11 lines.
 
Memory configuration:
*   ROM use Block RAM with 14 bit address bus length(32KB, 16KWords).
*   RAM use Block RAM with 12 bit address bus length(4KB).
 
RTC:
*   Address 0x40.
*   Counter size 32bit.
 
PIOA:
*   Address 0x60.
*   Dinamically configured by the microcontroller and connected to 5 onboard push buttons.
*   Connected to the five push buttons of Nexus Video board.
 
PIOB:
*   Address 0x80.
*   Statically configured like input PIO and connected to 8 onboard switches.
*   Connected to the eight switches of the Nexus Video board.
 
PIOC:
*   Address 0xA0.
*   Statically configured like output PIO and connected to 8 onboard LED's.
*   Connected to the eight LED's of the Nexus Video board.
 
PIOD:
*   Address 0xC0.
*   Dinamically configured by the microcontroller.
*   Connected to the JA PMOD connector of the Nexis Video board.
 
PIOE:
*   Address 0xE0.
*   Dinamically configured by the microcontroller.
*   Connected to the JB PMOD connector of the Nexis Video board.
 
PIOF:
*   Address 0x100.
*   Dinamically configured by the microcontroller.
*   Connected to the JC PMOD connector of the Nexis Video board.
 
PIOG:
*   Address 0x120.
*   Statically configured like output PIO.
*   Connected to the four wires (VDD, VBAT, RES, DC) of the onboard OLED display of the Nexus Video board.
 
UARTA:
*   Address 0x400.
*   Dinamically configured by the microcontroller.
*   Default UART pins of the Nexus Video board.
 
SPIA:
*   Address 0x600.
*   Dinamically configured by the microcontroller.
*   SCLK & SDIN of the onboard OLED dissplay pins of the Nexus Video board.
 
TWIA:
*   Address 0x800.
*   Dinamically configured by the microcontroller.
*   JC3=SCL, JC1=SDA on PMOD connector of the Nexus Video board.
 
2D Controller:
*   Address 0x300.
 
LCD Contoller:
*   Address is the 2D accelerator + 0x10.
*   Thru gfx_accel IP (2D Controller).
*   Resolution 1440*900 60Hz.
*   Pixel color is 8 bit (automatically converted from 24bit color space to 8bit color space).
 
HDMI Controller:
*   Driven by the LCD IP.
*   Connected to the HDMI out of the Nexus Video board.
 
Utilization report from implementation for MEGA_XMEGA_1 with default settings:
 
In this configuration the resource needed from Nexus Video board is:
 
|Resource | Utilization | Available | Utilization % |
|:--------|------------:|----------:|--------------:|
|`LUT`    | ~3803       | 133800    |  ~2.84        |
|`LUTRAM` |    32       |  46200    |   0.07        |
|`FF`     |  1656       | 267600    |   0.62        |
|`BRAM`   |   329       |    365    |  90.14        |
|`DSP`    |     2       |    740    |   0.27        |
|`IO`     |    65       |    285    |  22.81        |
|`PLL`    |     1       |     10    |  10.00        |
 
 
**********************************************************************************************************************
 
# To do:
 
* Add a HALT signal to the processor to facilitate DMA access.
* Add a DMA controller IP.
* Add a external SDRAM/DDR/DDR2/DDR3 controller IP with all glue necessary IP's.
 
 
 
![AVR Instruction set manual](https://git.morgothdisk.com/VERILOG/VERILOG-XMEGA-CORE-V3/raw/master/avr-instruction-set-manual.pdf)
 
![Atmel AVR Instruction set overview](https://git.morgothdisk.com/VERILOG/VERILOG-XMEGA-CORE-V3/raw/master/Atmel_AVR_Instruction_set_overview.png)
 
![XmegaFpgaTopImplementation](https://git.morgothdisk.com/VERILOG/VERILOG-XMEGA-CORE-V3/raw/master/XmegaFpgaTopImplementation.png)
 
 

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Subversion Repositories attiny_atmega_xmega_core

[/] [attiny_atmega_xmega_core/] [doc/] [README.md] - Blame information for rev 13

Line No.	Rev	Author	Line
1	13	morgothcre	`# XMEGA_CORE_IP_V2`
2
3			`This is an optimized IP of the Atmel MEGA and XMEGA processor, that is very simple to use.`
4
5			`* The ROM address BUS and RAM address BUS length are parametrized but not less than 8bit each address BUS.`
6			`* The watchdog counter size is aparametrized, if you set 0 counter length the core will not use the watchdog.`
7			`* The number of lines of the interrupt controller is parametrized and if number of lines is set to 0 the interrupt controller is not used.`
8
9			`Now I add support for this core on CPP-SDK https://git.morgothdisk.com/C-CPP/MULTIPLATFORM-CPP-SDK/tree/master/ExampleXmega_FPGA .`
10
11
12			`Utilization report from implementation for CORE_TYPE_XMEGA with default settings:`
13
14			`\|Resource \| Utilization \| Available \| Utilization % \|`
15			`\|:--------\|------------:\|----------:\|--------------:\|`
16			\|`LUT` \| ~1166 \| 20800 \| ~0.87 \|
17			\|`LUTRAM` \| 32 \| 46200 \| 0.07 \|
18			\|`FF` \| 137 \| 41600 \| 0.05 \|
19			\|`BRAM` \| 2.5 \| 365 \| 0.68 \|
20			\|`IO` \| 13 \| 285 \| 4.56 \|
21			\|`PLL` \| 1 \| 10 \| 10 \|
22
23			`This results is with one parametrized paralel port connected to onboard LED's, 1KBytes of RAM, 4KWords * 16bit of ROM ( the configuration is setup to emulate one Xmega8E5 ) without watchdog and without interrupt module.`
24
25			`**********************************************************************************************************************`
26
27			`Utilization report from implementation for CORE_TYPE_XMEGA with default settings:`
28
29			`\|Resource \| Utilization \| Available \| Utilization % \|`
30			`\|:--------\|------------:\|----------:\|--------------:\|`
31			\|`LUT` \| ~1277 \| 20800 \| ~0.95 \|
32			\|`LUTRAM` \| 32 \| 46200 \| 0.07 \|
33			\|`FF` \| 263 \| 41600 \| 0.10 \|
34			\|`BRAM` \| 2.5 \| 365 \| 0.68 \|
35			\|`IO` \| 18 \| 285 \| 6.32 \|
36			\|`PLL` \| 1 \| 10 \| 10 \|
37
38			`This results is with two paralel ports, one input fully software configurable port and one output parametrized port connected to onboard LED's, 1KBytes of RAM, 4KWords * 16bit of ROM ( the configuration is setup to emulate one Xmega8E5 ) 1 interrupt source from port A.`
39
40			`**********************************************************************************************************************`
41
42			`Utilization report from implementation for CORE_TYPE_MINIMAL with default settings:`
43
44			`\|Resource \| Utilization \| Available \| Utilization % \|`
45			`\|:--------\|------------:\|----------:\|--------------:\|`
46			\|`LUT` \| ~695 \| 20800 \| ~0.52 \|
47			\|`LUTRAM` \| 32 \| 46200 \| 0.07 \|
48			\|`FF` \| 98 \| 41600 \| 0.04 \|
49			\|`BRAM` \| 1.5 \| 365 \| 0.27 \|
50			\|`IO` \| 13 \| 285 \| 6.32 \|
51			\|`PLL` \| 1 \| 10 \| 10 \|
52
53			`This results is with one parametrized paralel port connected to onboard LED's, 128Bytes of RAM, 1KWords * 16bit of ROM ( the configuration is setup to emulate one Attiny26 ) without watchdog and without interrupt module.`
54
55			`**********************************************************************************************************************`
56
57			`Utilization report from implementation for CORE_TYPE_MINIMAL with default settings:`
58
59			`\|Resource \| Utilization \| Available \| Utilization % \|`
60			`\|:--------\|------------:\|----------:\|--------------:\|`
61			\|`LUT` \| ~825 \| 20800 \| ~0.62 \|
62			\|`LUTRAM` \| 32 \| 46200 \| 0.07 \|
63			\|`FF` \| 226 \| 41600 \| 0.08 \|
64			\|`BRAM` \| 1.5 \| 365 \| 0.41 \|
65			\|`IO` \| 18 \| 285 \| 6.32 \|
66			\|`PLL` \| 1 \| 10 \| 10 \|
67
68			`This results is with two paralel ports, one input fully software configurable port and one output parametrized port connected to onboard LED's, 128Bytes of RAM, 1KWords * 16bit of ROM ( the configuration is setup to emulate one Attiny26 ) 1 interrupt source from port A.`
69
70			`**********************************************************************************************************************`
71
72			`More details about instruction set implementation of different core type you can read here: https://en.wikipedia.org/wiki/Atmel_AVR_instruction_set`
73
74			`The core is configurable from minimal core to XMEGA core using one CORE_TYPE parameter.`
75
76
77			`\|Family\|Members\|Arithmetic\|Branches\|Transfers\|Bit-Wise\|`
78			`\|:-----\|:------\|:---------\|:-------\|:--------\|:-------\|`
79			`\|Minimal AVR1 Core\|AT90S1200, ATtiny11, ATtiny12, ATtiny15, ATtiny28\|ADD ADC SUB SUBI SBC SBCI AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER\|RJMP RCALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID\|LD ST MOV LDI IN OUT LPM (not in AT90S1200)\|SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH NOP SLEEP WDR\|`
80			`\|Classic Core up to 8K Program Space\|AT90S2313, AT90S2323, ATtiny22, AT90S2333, AT90S2343, AT90S4414, AT90S4433, AT90S4434, AT90S8515, AT90C8534, AT90S8535, ATtiny26\|new instructions: ADIW SBIW\|new instructions: IJMP ICALL\|new instructions: LD (now 9 modes) LDD LDS ST (9 modes) STD STS PUSH POP\|(nothing new)\|`
81			`\|Classic Core with up to 128K\|ATmega103, ATmega603, AT43USB320, AT76C711\|(nothing new)\|new instructions: JMP CALL\|new instructions: ELPM\|(nothing new)\|`
82			`\|Enhanced Core with up to 8K\|ATmega8, ATmega83, ATmega85, ATmega8515\|new instructions:MUL MULS MULSU FMUL FMULS FMULSU[2]\|(nothing new)\|new instructions: MOVW LPM(3modes) SPM\|(nothing new)\|`
83			`\|Enhanced Core with up to 128K\|ATmega16, ATmega161, ATmega163, ATmega32, ATmega323, ATmega64, ATmega128, AT43USB355, AT94 (FPSLIC), AT90CAN series, AT90PWM series, ATmega48, ATmega88, ATmega168, ATmega162, ATtiny13, ATtiny25, ATtiny45, ATtiny85, ATtiny2313, ATmega164, ATmega324, ATmega328, ATmega644, ATmega165, ATmega169, ATmega325, ATmega3250, ATmega645, ATmega6450, ATmega406\|(nothing new)\|(nothing new)\|(nothing new)\|new instructions: BREAK\|`
84			`\|Enhanced Core with up to 4M\|ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561\|(nothing new)\|new instructions:EIJMP EICALL\|(nothing new)\|(nothing new)\|`
85			`\|XMEGA Core\|ATxmega series\|new instructions:DES\|(nothing new)\|new instructions:(from second revision silicon - AU,B,C parts) XCH LAS LAC LAT\|(nothing new)\|`
86			\|Reduced AVRtiny Core\|ATtiny40, ATtiny20, ATtiny10, ATtiny9, ATtiny5, ATtiny4\|(Identical to minimal core, except for reduced CPU register set)\|(Identical to classic core with up to 8K, except for reduced CPU register set)\|Identical to classic core with up to 8K, with the following exceptions: LPM(removed) LDD(removed) STD(removed) LD(also accesses program memory) LDS(different bit pattern) STS(different bit pattern) Reduced CPU register set\|(Identical to enhanced core with up to 128K, except for reduced CPU register set)\|
87
88
89
90			`At this moment has implemented the next instructions:`
91
92			`One clock cycle instructions:`
93
94			`* LDI`
95			`* MOVW`
96			`* MUL`
97			`* MULS`
98			`* FMUL`
99			`* FMULS`
100			`* MULSU`
101			`* FMULSU`
102			`* INC`
103			`* DEC`
104			`* ASR`
105			`* LSR`
106			`* ROR`
107			`* SUB`
108			`* SBC`
109			`* ADD`
110			`* ADC`
111			`* SWAP`
112			`* AND`
113			`* EOR`
114			`* OR`
115			`* MOV`
116			`* BLD`
117			`* SUBI`
118			`* SBCI`
119			`* ORI_SBR`
120			`* ANDI_CBR`
121			`* COM`
122			`* NEG`
123			`* ADIW`
124			`* SBIW`
125
126			`Two clock cycle instructions:`
127
128			`* JMP`
129			`* IJMP`
130			`* RCALL`
131			`* CALL`
132			`* ICALL`
133			`* PUSH`
134			`* POP`
135			`* LDS16`
136			`* STS`
137			`* STD`
138			`* ST_X`
139			`* ST_XP`
140			`* OUT`
141			`* IN`
142			`* CBI`
143			`* SBI`
144			`* LPM_R`
145
146			`Three clock cycle instructions:`
147
148			`* CPSE`
149			`* SBRC`
150			`* SBRS`
151			`* SBIC`
152			`* SBIS`
153			`* LDS`
154			`* LDD`
155			`* LD_YZP`
156			`* LD_YZN`
157			`* ST_YZN`
158			`* LD_X`
159			`* LD_XP`
160			`* LD_XN`
161			`* ST_XN`
162			`* LPM_R`
163			`* LPM_R_P`
164
165			`Four clock cycle instructions:`
166
167			`* RET`
168			`* RETI`
169
170			`******** Some changes has been made to the instruction execution timings and may differ from the above table.`
171
172			`**********************************************************************************************************************`
173
174			`The implementation project is made for NexysVideo from Digilent and core setup is XMEGA.`
175
176			`The next IO are connected to RAM bus:`
177
178			`* RTC IP located at addr 0x40, this can generate a period interrupt and is connected to line 0 of the interrupt controller.`
179			`* PIO IP port located at addr 0x60 input 5 buttons port, this port is parametrized to be dinamically configured by thru software commands and has connected and can generate one interrupt that is connected to line 1 of the interrupt controller.`
180			`* PIO IP port located at addr 0x80 switch inputs port, this port is parametrized to be configured using parameters and has connected and can generate one interrupt that is connected to line 2 of the interrupt controller.`
181			`* PIO IP port located at addr 0xA0 output port for LED's, this port is parametrized to be configured using parameters and has connected and can generate one interrupt that is connected to line 3 of the interrupt controller.`
182			`* PIO IP port located at addr 0xC0 this PIO is connected on the JA PMOD connector and can generate an interrupt that is connected to the line 4 of the interrupt controller.`
183			`* PIO IP port located at addr 0xE0 this PIO is connected on the JB PMOD connector and can generate an interrupt that is connected to the line 5 of the interrupt controller..`
184			`* PIO IP port located at addr 0x100 this PIO is connected on the JC PMOD connector and can generate an interrupt that is connected to the line 6 of the interrupt controller..`
185			`* SPI IP that is connected at addr 0x600, this module drive the Nexus Video onboard OLED display and can generate one interrupt that is connected to the line 7 of the interrupt controller.`
186			`* UART IP that is connected at addr 0x400, this module is parametrized to be dinamically configured thru software that has connected and can generate three interrupts: UART_RXC (Uart RX complete), UART_TXC (Uart TX complete), UART_DRE (Tx data register empty) that are connected to line 8, 9 and 10 of the interrupt controller.`
187			`* TWI IP that is connected at addr 0x800, this module is connected on JC1=SDA & JC3=SCL connector of the Nexis Video where is connected the PmodNAV board, The CppSDK example application read the LSM9DS1 device and dislay the results on onboard OLED display..`
188			`* GFX 2D simple accelerator at addr 0x300, this IP paint filled rectangles and single pixels with a speed of one pixel oc core clock.`
189			`* LCD IP pannel controller that has the BRAM VRAM configured in 8bit/color and is starting from address 0 of the microcontroller RAM, the LCD controller IP is parametrized to drive a 1440x900 display pannel at ~60Hz.`
190			`* HDMI IP serializer that is connected to the HDMI output connector of the NEXIS VIDEO board is drived by the LCD IP.`
191
192			`On this configuration if a PMODNAV 9-axis from Digilent is connected to JC PMOD connector it will display the values of the LSM9DS1 temperature, acceleration, giroscope and compass if the SW0 is down, and it will display the LPS25HB temperature and pressure if SW0 is up, on Onboard OLED display and on a HDMI display parametrized for a resolution of 1440x900 at 60HZ.`
193
194			`The current configuration is:`
195
196			`Clocks:`
197			`* ~100Mhz core clock.`
198			`* 533.333Mhz HDMI IP clock that generate 106.666Mhz LCD IP clock.`
199
200			`Core configuration:`
201			`* Configuration MEGA_XMEGA_1`
202			`* Interrupt controller 11 lines.`
203
204			`Memory configuration:`
205			`* ROM use Block RAM with 14 bit address bus length(32KB, 16KWords).`
206			`* RAM use Block RAM with 12 bit address bus length(4KB).`
207
208			`RTC:`
209			`* Address 0x40.`
210			`* Counter size 32bit.`
211
212			`PIOA:`
213			`* Address 0x60.`
214			`* Dinamically configured by the microcontroller and connected to 5 onboard push buttons.`
215			`* Connected to the five push buttons of Nexus Video board.`
216
217			`PIOB:`
218			`* Address 0x80.`
219			`* Statically configured like input PIO and connected to 8 onboard switches.`
220			`* Connected to the eight switches of the Nexus Video board.`
221
222			`PIOC:`
223			`* Address 0xA0.`
224			`* Statically configured like output PIO and connected to 8 onboard LED's.`
225			`* Connected to the eight LED's of the Nexus Video board.`
226
227			`PIOD:`
228			`* Address 0xC0.`
229			`* Dinamically configured by the microcontroller.`
230			`* Connected to the JA PMOD connector of the Nexis Video board.`
231
232			`PIOE:`
233			`* Address 0xE0.`
234			`* Dinamically configured by the microcontroller.`
235			`* Connected to the JB PMOD connector of the Nexis Video board.`
236
237			`PIOF:`
238			`* Address 0x100.`
239			`* Dinamically configured by the microcontroller.`
240			`* Connected to the JC PMOD connector of the Nexis Video board.`
241
242			`PIOG:`
243			`* Address 0x120.`
244			`* Statically configured like output PIO.`
245			`* Connected to the four wires (VDD, VBAT, RES, DC) of the onboard OLED display of the Nexus Video board.`
246
247			`UARTA:`
248			`* Address 0x400.`
249			`* Dinamically configured by the microcontroller.`
250			`* Default UART pins of the Nexus Video board.`
251
252			`SPIA:`
253			`* Address 0x600.`
254			`* Dinamically configured by the microcontroller.`
255			`* SCLK & SDIN of the onboard OLED dissplay pins of the Nexus Video board.`
256
257			`TWIA:`
258			`* Address 0x800.`
259			`* Dinamically configured by the microcontroller.`
260			`* JC3=SCL, JC1=SDA on PMOD connector of the Nexus Video board.`
261
262			`2D Controller:`
263			`* Address 0x300.`
264
265			`LCD Contoller:`
266			`* Address is the 2D accelerator + 0x10.`
267			`* Thru gfx_accel IP (2D Controller).`
268			`* Resolution 1440*900 60Hz.`
269			`* Pixel color is 8 bit (automatically converted from 24bit color space to 8bit color space).`
270
271			`HDMI Controller:`
272			`* Driven by the LCD IP.`
273			`* Connected to the HDMI out of the Nexus Video board.`
274
275			`Utilization report from implementation for MEGA_XMEGA_1 with default settings:`
276
277			`In this configuration the resource needed from Nexus Video board is:`
278
279			`\|Resource \| Utilization \| Available \| Utilization % \|`
280			`\|:--------\|------------:\|----------:\|--------------:\|`
281			\|`LUT` \| ~3803 \| 133800 \| ~2.84 \|
282			\|`LUTRAM` \| 32 \| 46200 \| 0.07 \|
283			\|`FF` \| 1656 \| 267600 \| 0.62 \|
284			\|`BRAM` \| 329 \| 365 \| 90.14 \|
285			\|`DSP` \| 2 \| 740 \| 0.27 \|
286			\|`IO` \| 65 \| 285 \| 22.81 \|
287			\|`PLL` \| 1 \| 10 \| 10.00 \|
288
289
290			`**********************************************************************************************************************`
291
292			`# To do:`
293
294			`* Add a HALT signal to the processor to facilitate DMA access.`
295			`* Add a DMA controller IP.`
296			`* Add a external SDRAM/DDR/DDR2/DDR3 controller IP with all glue necessary IP's.`
297
298
299
300			`![AVR Instruction set manual](https://git.morgothdisk.com/VERILOG/VERILOG-XMEGA-CORE-V3/raw/master/avr-instruction-set-manual.pdf)`
301
302			`![Atmel AVR Instruction set overview](https://git.morgothdisk.com/VERILOG/VERILOG-XMEGA-CORE-V3/raw/master/Atmel_AVR_Instruction_set_overview.png)`
303
304			`![XmegaFpgaTopImplementation](https://git.morgothdisk.com/VERILOG/VERILOG-XMEGA-CORE-V3/raw/master/XmegaFpgaTopImplementation.png)`
305
306