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[/] [attiny_atmega_xmega_core/] [trunk/] [rtl/] [sim_uc.v] - Blame information for rev 15

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/*
 * This is the simulation file for Atmel XMEGA CPU IP.
 *
 * Copyright (C) 2017  Iulian Gheorghiu
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 */
 
`timescale 1ns / 1ps
//`include "ddr3_v.v"
/* For Attiny 26 */
//`define BUS_ADDR_PGM_LEN_SIM          11 /* < in address lines 2KWords */
//`define BUS_ADDR_DATA_LEN_SIM         8 /* < in address lines 256Bytes data address space */
//`define DATA_MEM_SIZE_LEN_SIM         7  /* < in address lines 128Bytes */
//`define DATA_ADDR_RESERVED_AT_BOTTOM_SIM      'd128  /* < in bytes ( 128 bytes to let space for IO usage )*/
 
/* For ATXmega */
`define BUS_ADDR_PGM_LEN_SIM            16 /* < in address lines 64KWords */
`define BUS_ADDR_DATA_LEN_SIM           16 /* < in address lines 64KBytes data address space */
`define DATA_MEM_SIZE_LEN_SIM           12  /* < in address lines 4KByte */
`define DATA_ADDR_RESERVED_AT_BOTTOM_SIM        'd8192  /* < in bytes ( 8192 bytes is the standard atxmega reserved address for IO usage )*/
 
`define USE_HDMI_OUTPUT
 
`define DDR3_ADDR_BUS_LEN               15
 
module sim_uc(
//`DDR3_TOP
    );
 
//`DDR3_IO
 
reg rst = 0;
 
/*ddr3 ddr3_inst(
        `DDR3_CONNECT
);*/
reg int1 = 0;
reg int2 = 0;
reg int3 = 0;
wire _int1 = int1;
wire _int2 = int2;
wire _int3 = int3;
wire [4:0]int = 0;
 
wire sys_rst;
 
wire [7:0]port_out;
wire [7:0]port_in = port_out;
wire UART_TXD;
wire UART_RXD = UART_TXD;
 
wire hdmi_tx_cec;
wire hdmi_tx_clk_n;
wire hdmi_tx_clk_p;
wire hdmi_tx_hpd;
wire hdmi_tx_rscl;
wire hdmi_tx_rsda;
wire [2:0]hdmi_tx_n;
wire [2:0]hdmi_tx_p;
 
 
 
reg core_clk = 0;
reg ram_clk = 0;
always  #(1)    ram_clk <=      ~ram_clk;       //      clocking        device
always @ (posedge ram_clk)
begin
        core_clk <= ~core_clk;
end
 
wire lcd_clk = core_clk;
//wire pgm_re;
wire [`BUS_ADDR_PGM_LEN_SIM-1:0] pgm_addr;
wire [15:0] pgm_data;
wire data_re;
wire data_we;
wire [`BUS_ADDR_DATA_LEN_SIM-1:0] data_addr;
wire [7:0]data_in;
wire [7:0]data_out;
 
wire io_re;
wire io_we;
wire [5:0] io_addr;
wire [7:0] io_in;
wire [7:0] io_out;
 
//assign data_addr = data_re | data_we ? 'bz : 0;
wire ram_data_sel = data_addr >= `DATA_ADDR_RESERVED_AT_BOTTOM_SIM;
wire [`BUS_ADDR_DATA_LEN_SIM-1:0]ram_offset = `DATA_ADDR_RESERVED_AT_BOTTOM_SIM;
wire [`DATA_MEM_SIZE_LEN_SIM-1:0]ram_addr_bus = data_addr - ram_offset;
 
wire rtc_int;
wire int_pio_a;
wire int_pio_b;
wire int_pio_c;
wire int_pio_d;
wire int_pio_e;
wire int_pio_f;
wire int_uart_a_rx_rcv;
wire int_uart_a_tx_compl;
wire int_uart_a_tx_buff_empty;
wire int_spi_a;
wire [10:0]int_rst;
 
initial begin
        rst = 0;
        #1;
        rst = 1;
        #1;
        rst = 0;
 
        //port_out = 8'haa;
        #110000;
        int1 = 1;
        //int2 = 1;
        //int3 = 1;
        #20;
        int1 = 0;
        int2 = 0;
        int3 = 0;
        #1200000;
        $finish;
end
 
 
rtc_s # (
        .ADDRESS('h40),
        .BUS_ADDR_DATA_LEN(`BUS_ADDR_DATA_LEN_SIM),
        .CNT_SIZE(32)
        ) rtc (
        .rst(sys_rst),
        .clk(core_clk),
        .addr(data_addr),
        .wr(data_we),
        .rd(data_re),
        .bus_in(data_out),
        .bus_out(data_in),
        .int(rtc_int),
        .int_rst(int_rst[0])
        );
 
pio_s  # (
        .DINAMIC_IN_OUT_CONFIG("TRUE"),
        .IN_OUT_MASK_CONFIG(8'h00),
        .USE_INTERRUPTS("TRUE"),
        .DINAMIC_INTERRUPT_CONFIG("TRUE"),
        .INTERRUPT_MASK_CONFIG(8'h07),
        .INTERRUPT_UP_DN_EDGE_DETECT(8'h07),
        .INTERRUPT_BOTH_EDGES_DETECT_MASK(8'h00),
        .BUS_KEPPER_EN_MASK(8'b00000000),
        .BUS_PULL_UP_EN_MASK(8'b00000000),
        .BUS_PULL_DN_EN_MASK(8'b00000000),
        .ADDRESS('h60),
        .BUS_ADDR_DATA_LEN(`BUS_ADDR_DATA_LEN_SIM)
        ) pio_port_A (
        .rst(sys_rst),
        .clk(core_clk),
        .addr(data_addr),
        .wr(data_we),
        .rd(data_re),
        .bus_in(data_out),
        .bus_out(data_in),
        .io({int, _int3, _int2, _int1}),
        .int(int_pio_a),
        .int_rst(int_rst[1])
);
 
pio_s  # (
        .DINAMIC_IN_OUT_CONFIG("FALSE"),
        .IN_OUT_MASK_CONFIG(8'h00),
        .USE_INTERRUPTS("FALSE"),
        .DINAMIC_INTERRUPT_CONFIG("FALSE"),
        .INTERRUPT_MASK_CONFIG(8'h00),
        .INTERRUPT_UP_DN_EDGE_DETECT(8'h00),
        .INTERRUPT_BOTH_EDGES_DETECT_MASK(8'h00),
        .BUS_KEPPER_EN_MASK(8'b00000000),
        .BUS_PULL_UP_EN_MASK(8'b00000000),
        .BUS_PULL_DN_EN_MASK(8'b00000000),
        .ADDRESS('h80),
        .BUS_ADDR_DATA_LEN(`BUS_ADDR_DATA_LEN_SIM)
        ) pio_port_B (
        .rst(sys_rst),
        .clk(core_clk),
        .addr(data_addr),
        .wr(data_we),
        .rd(data_re),
        .bus_in(data_out),
        .bus_out(data_in),
        .io(port_in),
        .int(int_pio_b),
        .int_rst(int_rst[2])
);
 
pio_s # (
        .DINAMIC_IN_OUT_CONFIG("FALSE"),
        .IN_OUT_MASK_CONFIG(8'hFF),
        .USE_INTERRUPTS("FALSE"),
        .DINAMIC_INTERRUPT_CONFIG("FALSE"),
        .INTERRUPT_MASK_CONFIG(8'h00),
        .INTERRUPT_UP_DN_EDGE_DETECT(8'h00),
        .INTERRUPT_BOTH_EDGES_DETECT_MASK(8'h00),
        .BUS_KEPPER_EN_MASK(8'b00000000),
        .BUS_PULL_UP_EN_MASK(8'b00000000),
        .BUS_PULL_DN_EN_MASK(8'b00000000),
        .ADDRESS('hA0),
        .BUS_ADDR_DATA_LEN(`BUS_ADDR_DATA_LEN_SIM)
        ) pio_port_C (
        .rst(sys_rst),
        .clk(core_clk),
        .addr(data_addr),
        .wr(data_we),
        .rd(data_re),
        .bus_in(data_out),
        .bus_out(data_in),
        .io(port_out),
        .int(int_pio_c),
        .int_rst(int_rst[3])
);
//`ifdef _0_
uart_s # (
        .BAUDRATE_COUNTER_LENGTH(12),
        .DINAMIC_BAUDRATE("TRUE"),
        .BAUDRATE_DIVIDER((1000 / 24) / 16 / 19200),
        .ADDRESS('hC0),
        .BUS_ADDR_DATA_LEN(`BUS_ADDR_DATA_LEN_SIM)
        ) uart_A (
        .rst(sys_rst),
        .clk(core_clk),
        .addr(data_addr),
        .wr(data_we),
        .rd(data_re),
        .bus_in(data_out),
        .bus_out(data_in),
        .int_rx_rcv(int_uart_a_rx_rcv),
        .int_tx_compl(int_uart_a_tx_compl),
        .int_tx_buff_empty(int_uart_a_tx_buff_empty),
        .tx(UART_TXD),
        .rx(UART_RXD)
        );
 
wire oled_sclk;
wire oled_sdin;
 
spi_s #(
        .DINAMIC_BAUDRATE("TRUE"),
        .BAUDRATE_DIVIDER(8),
        .ADDRESS('h600),
        .BUS_ADDR_DATA_LEN(`BUS_ADDR_DATA_LEN_SIM)
    )spi_A(
        .rst(sys_rst),
        .clk(core_clk),
        .addr(data_addr),
        .wr(data_we),
        .rd(data_re),
        .bus_in(data_out),
        .bus_out(data_in),
        .int(int_spi_a),
 
        .sck(oled_sclk),/* SPI 'sck' signal (output) */
        .mosi(oled_sdin),/* SPI 'mosi' signal (output) */
        .miso(1'b1),/* SPI 'miso' signal (input) */
        .ss()/* SPI 'ss' signal (if send buffer is maintained full the ss signal will not go high between between transmit chars)(output) */
    );
 
wire ja_scl;
wire ja_sda;
 
twi_s #(
    .DINAMIC_BAUDRATE("TRUE"),
    .BAUDRATE_DIVIDER(255),
    .ADDRESS('h800),
    .BUS_ADDR_DATA_LEN(`BUS_ADDR_DATA_LEN_SIM)
    )twi_inst(
    .rst(sys_rst),
    .clk(core_clk),
    .addr(data_addr),
    .wr(data_we),
    .rd(data_re),
    .bus_in(data_out),
    .bus_out(data_in),
    .int_tx_cmpl(),
    .int_rx_cmpl(),
    .int_tx_rst(),
    .int_rx_rst(),
 
    .scl(ja_scl),
    .sda(ja_sda)
    );
wire lcd_h_int;
wire lcd_v_int;
wire lcd_de;
wire [7:0]ja_int;
wire [7:0]jb_int;
wire [7:0]jc_int;
wire lcd_clk_10;
`ifndef USE_HDMI_OUTPUT
assign ja = {ja_int[7:1], lcd_clk_10};
assign jb = {jb_int[7:1], lcd_h_int};
assign jc = {jc_int[7:1], lcd_v_int};
`endif
 
lcd # (
        .MASTER("TRUE"),
        .DEBUG(""),//"PATERN_RASTER"
        .DISPLAY_CFG("1280_720_60_DISPLAY_74_25_Mhz"),
 
        .ADDRESS('hE0),
        .BUS_VRAM_ADDR_LEN(24),
        .BUS_VRAM_DATA_LEN(8),
        .BUS_ADDR_DATA_LEN(16),
 
        .DINAMIC_CONFIG("FALSE"),
        .VRAM_BASE_ADDRESS_CONF(0),
        /* This timings are for AT070TN92 LCD display module but is not tacken in account because we will load a default setup with DISPLAY_CFG parameter.*/
        .H_RES_CONF(720),
        .H_BACK_PORCH_CONF(138),
        .H_FRONT_PORCH_CONF(16),
        .H_PULSE_WIDTH_CONF(62),
        .V_RES_CONF(480),
        .V_BACK_PORCH_CONF(45),
        .V_FRONT_PORCH_CONF(9),
        .V_PULSE_WIDTH_CONF(6),
        .PIXEL_SIZE_CONF(16),
        .HSYNK_INVERTED_CONF(1'b0),
        .VSYNK_INVERTED_CONF(1'b0),
        .DATA_ENABLE_INVERTED_CONF(1'b0),
        .DEDICATED_VRAM_SIZE(800 * 480)
        )lcd_inst(
        .rst(sys_rst),
        .ctrl_clk(core_clk),
    .ctrl_addr(data_addr),
        .ctrl_wr(data_we),
        .ctrl_rd(data_re),
        .ctrl_data_in(data_out),
        .ctrl_data_out(data_in),
 
        .vmem_addr(ram_addr_bus),
        .vmem_in(data_out),
        .vmem_out(data_in),
        .vmem_rd(1'b0),
        .vmem_wr(data_we & ram_data_sel),
 
`ifdef USE_HDMI_OUTPUT
        .lcd_clk(lcd_clk_10),
`else
        .lcd_clk(lcd_clk),
`endif
        .lcd_h_synk(lcd_h_int),
        .lcd_v_synk(lcd_v_int),
        .lcd_r(ja_int),
        .lcd_g(jb_int),
        .lcd_b(jc_int),
        .lcd_de(lcd_de)
);
 
`ifdef USE_HDMI_OUTPUT
hdmi_out # (
        .PLATFORM("XILINX_ARTIX_7")
)hdmi_out_inst(
        .rst(sys_rst),
        .clk(lcd_clk),
        .hdmi_tx_cec(hdmi_tx_cec),
        .hdmi_tx_clk_n(hdmi_tx_clk_n),
        .hdmi_tx_clk_p(hdmi_tx_clk_p),
        .hdmi_tx_hpd(hdmi_tx_hpd),
        .hdmi_tx_rscl(hdmi_tx_rscl),
        .hdmi_tx_rsda(hdmi_tx_rsda),
        .hdmi_tx_n(hdmi_tx_n),
        .hdmi_tx_p(hdmi_tx_p),
 
        .lcd_clk_out(lcd_clk_10),
        .lcd_h_synk(lcd_h_int),
        .lcd_v_synk(lcd_v_int),
        .lcd_r('hAA),
        .lcd_g('hDB),
        .lcd_b('h24),
        .lcd_de(lcd_de)
        );
`endif
//`endif //!_0_
 
rom  #(
.ADDR_ROM_BUS_WIDTH(`BUS_ADDR_PGM_LEN_SIM),
.ROM_PATH("core1ROM.mem"),
.SYNCHRONOUS("FALSE")
)rom(
        .clk(core_clk),
        .a(pgm_addr),
        .d(pgm_data)
);
 
ram  #(
.ADDR_BUS_WIDTH(`DATA_MEM_SIZE_LEN_SIM),
.RAM_PATH(""),
.SYNCHRONOUS("TRUE")
)ram(
        .clk(core_clk),
        .re(data_re & ram_data_sel),
        .we(data_we & ram_data_sel),
        .a(ram_addr_bus),
        .d_in(data_out),
        .d_out(data_in)
);
 
mega_core #(
        .CORE_CONFIG("XMEGA"),// Supported: "REDUCED", "MINIMAL", "CLASSIC_8K", "CLASSIC_128K", "ENHANCED_8K", "ENHANCED_128K", "ENHANCED_4M", "XMEGA"
        .BUS_ADDR_PGM_WIDTH(`BUS_ADDR_PGM_LEN_SIM),
        .BUS_ADDR_DATA_WIDTH(`BUS_ADDR_DATA_LEN_SIM),
        .USE_BRAM_ROM("FALSE"),
        .WATCHDOG_CNT_WIDTH(21),/* If is 0 the watchdog is disabled */
        .VECTOR_INT_TABLE_SIZE(10),
        .STORE_INTERUPTS("FALSE"),
        .MAP_REGS_IN_TO_SRAM_SECTION("FALSE")
)core(
        .rst(rst),
        .sys_rst(sys_rst),/* Output reset provided by core thru watchdog to the rest of the system */
        .clk(core_clk),
        .clk_wdt(core_clk),
 
        .pgm_addr(pgm_addr),
        .pgm_data(pgm_data),
 
        .data_re(data_re),
        .data_we(data_we),
        .data_addr(data_addr),
        .data_in(data_in),
        .data_out(data_out),
 
        .io_re(io_re),
        .io_we(io_we),
        .io_addr(io_addr),
        .io_in(io_in),
        .io_out(io_out),
 
        .int_sig({int_uart_a_tx_buff_empty, int_uart_a_tx_compl, int_uart_a_rx_rcv, int_spi_a, int_pio_f, int_pio_e, int_pio_d, int_pio_c, int_pio_b, int_pio_a, rtc_int}),
        .int_rst(int_rst),
        .wdt_rst_out()
);
 
 
endmodule
 
 

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[/] [attiny_atmega_xmega_core/] [trunk/] [rtl/] [sim_uc.v] - Blame information for rev 15

Line No.	Rev	Author	Line
1	2	morgothcre	`/*`
2			`* This is the simulation file for Atmel XMEGA CPU IP.`
3			`*`
4			`* Copyright (C) 2017 Iulian Gheorghiu`
5			`*`
6			`* This program is free software; you can redistribute it and/or`
7			`* modify it under the terms of the GNU General Public License`
8			`* as published by the Free Software Foundation; either version 2`
9			`* of the License, or (at your option) any later version.`
10			`*`
11			`* This program is distributed in the hope that it will be useful,`
12			`* but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
14			`* GNU General Public License for more details.`
15			`*`
16			`* You should have received a copy of the GNU General Public License`
17			`* along with this program; if not, write to the Free Software`
18			`* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.`
19			`*/`
20
21			`timescale 1ns / 1ps
22			//`include "ddr3_v.v"
23			`/* For Attiny 26 */`
24			//`define BUS_ADDR_PGM_LEN_SIM 11 /* < in address lines 2KWords */
25			//`define BUS_ADDR_DATA_LEN_SIM 8 /* < in address lines 256Bytes data address space */
26			//`define DATA_MEM_SIZE_LEN_SIM 7 /* < in address lines 128Bytes */
27			//`define DATA_ADDR_RESERVED_AT_BOTTOM_SIM 'd128 /* < in bytes ( 128 bytes to let space for IO usage )*/
28
29			`/* For ATXmega */`
30			`define BUS_ADDR_PGM_LEN_SIM 16 /* < in address lines 64KWords */
31			`define BUS_ADDR_DATA_LEN_SIM 16 /* < in address lines 64KBytes data address space */
32			`define DATA_MEM_SIZE_LEN_SIM 12 /* < in address lines 4KByte */
33			`define DATA_ADDR_RESERVED_AT_BOTTOM_SIM 'd8192 /* < in bytes ( 8192 bytes is the standard atxmega reserved address for IO usage )*/
34
35			`define USE_HDMI_OUTPUT
36
37			`define DDR3_ADDR_BUS_LEN 15
38
39			`module sim_uc(`
40			//`DDR3_TOP
41			`);`
42
43			//`DDR3_IO
44
45			`reg rst = 0;`
46
47			`/*ddr3 ddr3_inst(`
48			`DDR3_CONNECT
49			`);*/`
50			`reg int1 = 0;`
51			`reg int2 = 0;`
52			`reg int3 = 0;`
53			`wire _int1 = int1;`
54			`wire _int2 = int2;`
55			`wire _int3 = int3;`
56			`wire [4:0]int = 0;`
57
58			`wire sys_rst;`
59
60			`wire [7:0]port_out;`
61			`wire [7:0]port_in = port_out;`
62			`wire UART_TXD;`
63			`wire UART_RXD = UART_TXD;`
64
65			`wire hdmi_tx_cec;`
66			`wire hdmi_tx_clk_n;`
67			`wire hdmi_tx_clk_p;`
68			`wire hdmi_tx_hpd;`
69			`wire hdmi_tx_rscl;`
70			`wire hdmi_tx_rsda;`
71			`wire [2:0]hdmi_tx_n;`
72			`wire [2:0]hdmi_tx_p;`
73
74
75
76			`reg core_clk = 0;`
77			`reg ram_clk = 0;`
78			`always #(1) ram_clk <= ~ram_clk; // clocking device`
79			`always @ (posedge ram_clk)`
80			`begin`
81			`core_clk <= ~core_clk;`
82			`end`
83
84			`wire lcd_clk = core_clk;`
85			`//wire pgm_re;`
86			wire [`BUS_ADDR_PGM_LEN_SIM-1:0] pgm_addr;
87			`wire [15:0] pgm_data;`
88			`wire data_re;`
89			`wire data_we;`
90			wire [`BUS_ADDR_DATA_LEN_SIM-1:0] data_addr;
91			`wire [7:0]data_in;`
92			`wire [7:0]data_out;`
93
94			`wire io_re;`
95			`wire io_we;`
96			`wire [5:0] io_addr;`
97			`wire [7:0] io_in;`
98			`wire [7:0] io_out;`
99
100			`//assign data_addr = data_re \| data_we ? 'bz : 0;`
101			wire ram_data_sel = data_addr >= `DATA_ADDR_RESERVED_AT_BOTTOM_SIM;
102			wire [`BUS_ADDR_DATA_LEN_SIM-1:0]ram_offset = `DATA_ADDR_RESERVED_AT_BOTTOM_SIM;
103			wire [`DATA_MEM_SIZE_LEN_SIM-1:0]ram_addr_bus = data_addr - ram_offset;
104
105			`wire rtc_int;`
106			`wire int_pio_a;`
107			`wire int_pio_b;`
108			`wire int_pio_c;`
109			`wire int_pio_d;`
110			`wire int_pio_e;`
111			`wire int_pio_f;`
112			`wire int_uart_a_rx_rcv;`
113			`wire int_uart_a_tx_compl;`
114			`wire int_uart_a_tx_buff_empty;`
115			`wire int_spi_a;`
116			`wire [10:0]int_rst;`
117
118			`initial begin`
119			`rst = 0;`
120			`#1;`
121			`rst = 1;`
122			`#1;`
123			`rst = 0;`
124
125			`//port_out = 8'haa;`
126			`#110000;`
127			`int1 = 1;`
128			`//int2 = 1;`
129			`//int3 = 1;`
130			`#20;`
131			`int1 = 0;`
132			`int2 = 0;`
133			`int3 = 0;`
134			`#1200000;`
135			`$finish;`
136			`end`
137
138
139			`rtc_s # (`
140			`.ADDRESS('h40),`
141			.BUS_ADDR_DATA_LEN(`BUS_ADDR_DATA_LEN_SIM),
142			`.CNT_SIZE(32)`
143			`) rtc (`
144			`.rst(sys_rst),`
145			`.clk(core_clk),`
146			`.addr(data_addr),`
147			`.wr(data_we),`
148			`.rd(data_re),`
149			`.bus_in(data_out),`
150			`.bus_out(data_in),`
151			`.int(rtc_int),`
152			`.int_rst(int_rst[0])`
153			`);`
154
155			`pio_s # (`
156			`.DINAMIC_IN_OUT_CONFIG("TRUE"),`
157			`.IN_OUT_MASK_CONFIG(8'h00),`
158			`.USE_INTERRUPTS("TRUE"),`
159			`.DINAMIC_INTERRUPT_CONFIG("TRUE"),`
160			`.INTERRUPT_MASK_CONFIG(8'h07),`
161			`.INTERRUPT_UP_DN_EDGE_DETECT(8'h07),`
162			`.INTERRUPT_BOTH_EDGES_DETECT_MASK(8'h00),`
163			`.BUS_KEPPER_EN_MASK(8'b00000000),`
164			`.BUS_PULL_UP_EN_MASK(8'b00000000),`
165			`.BUS_PULL_DN_EN_MASK(8'b00000000),`
166			`.ADDRESS('h60),`
167			.BUS_ADDR_DATA_LEN(`BUS_ADDR_DATA_LEN_SIM)
168			`) pio_port_A (`
169			`.rst(sys_rst),`
170			`.clk(core_clk),`
171			`.addr(data_addr),`
172			`.wr(data_we),`
173			`.rd(data_re),`
174			`.bus_in(data_out),`
175			`.bus_out(data_in),`
176			`.io({int, _int3, _int2, _int1}),`
177			`.int(int_pio_a),`
178			`.int_rst(int_rst[1])`
179			`);`
180
181			`pio_s # (`
182			`.DINAMIC_IN_OUT_CONFIG("FALSE"),`
183			`.IN_OUT_MASK_CONFIG(8'h00),`
184			`.USE_INTERRUPTS("FALSE"),`
185			`.DINAMIC_INTERRUPT_CONFIG("FALSE"),`
186			`.INTERRUPT_MASK_CONFIG(8'h00),`
187			`.INTERRUPT_UP_DN_EDGE_DETECT(8'h00),`
188			`.INTERRUPT_BOTH_EDGES_DETECT_MASK(8'h00),`
189			`.BUS_KEPPER_EN_MASK(8'b00000000),`
190			`.BUS_PULL_UP_EN_MASK(8'b00000000),`
191			`.BUS_PULL_DN_EN_MASK(8'b00000000),`
192			`.ADDRESS('h80),`
193			.BUS_ADDR_DATA_LEN(`BUS_ADDR_DATA_LEN_SIM)
194			`) pio_port_B (`
195			`.rst(sys_rst),`
196			`.clk(core_clk),`
197			`.addr(data_addr),`
198			`.wr(data_we),`
199			`.rd(data_re),`
200			`.bus_in(data_out),`
201			`.bus_out(data_in),`
202			`.io(port_in),`
203			`.int(int_pio_b),`
204			`.int_rst(int_rst[2])`
205			`);`
206
207			`pio_s # (`
208			`.DINAMIC_IN_OUT_CONFIG("FALSE"),`
209			`.IN_OUT_MASK_CONFIG(8'hFF),`
210			`.USE_INTERRUPTS("FALSE"),`
211			`.DINAMIC_INTERRUPT_CONFIG("FALSE"),`
212			`.INTERRUPT_MASK_CONFIG(8'h00),`
213			`.INTERRUPT_UP_DN_EDGE_DETECT(8'h00),`
214			`.INTERRUPT_BOTH_EDGES_DETECT_MASK(8'h00),`
215			`.BUS_KEPPER_EN_MASK(8'b00000000),`
216			`.BUS_PULL_UP_EN_MASK(8'b00000000),`
217			`.BUS_PULL_DN_EN_MASK(8'b00000000),`
218			`.ADDRESS('hA0),`
219			.BUS_ADDR_DATA_LEN(`BUS_ADDR_DATA_LEN_SIM)
220			`) pio_port_C (`
221			`.rst(sys_rst),`
222			`.clk(core_clk),`
223			`.addr(data_addr),`
224			`.wr(data_we),`
225			`.rd(data_re),`
226			`.bus_in(data_out),`
227			`.bus_out(data_in),`
228			`.io(port_out),`
229			`.int(int_pio_c),`
230			`.int_rst(int_rst[3])`
231			`);`
232			//`ifdef _0_
233			`uart_s # (`
234			`.BAUDRATE_COUNTER_LENGTH(12),`
235			`.DINAMIC_BAUDRATE("TRUE"),`
236			`.BAUDRATE_DIVIDER((1000 / 24) / 16 / 19200),`
237			`.ADDRESS('hC0),`
238			.BUS_ADDR_DATA_LEN(`BUS_ADDR_DATA_LEN_SIM)
239			`) uart_A (`
240			`.rst(sys_rst),`
241			`.clk(core_clk),`
242			`.addr(data_addr),`
243			`.wr(data_we),`
244			`.rd(data_re),`
245			`.bus_in(data_out),`
246			`.bus_out(data_in),`
247			`.int_rx_rcv(int_uart_a_rx_rcv),`
248			`.int_tx_compl(int_uart_a_tx_compl),`
249			`.int_tx_buff_empty(int_uart_a_tx_buff_empty),`
250			`.tx(UART_TXD),`
251			`.rx(UART_RXD)`
252			`);`
253
254			`wire oled_sclk;`
255			`wire oled_sdin;`
256
257			`spi_s #(`
258			`.DINAMIC_BAUDRATE("TRUE"),`
259			`.BAUDRATE_DIVIDER(8),`
260			`.ADDRESS('h600),`
261			.BUS_ADDR_DATA_LEN(`BUS_ADDR_DATA_LEN_SIM)
262			`)spi_A(`
263			`.rst(sys_rst),`
264			`.clk(core_clk),`
265			`.addr(data_addr),`
266			`.wr(data_we),`
267			`.rd(data_re),`
268			`.bus_in(data_out),`
269			`.bus_out(data_in),`
270			`.int(int_spi_a),`
271
272			`.sck(oled_sclk),/* SPI 'sck' signal (output) */`
273			`.mosi(oled_sdin),/* SPI 'mosi' signal (output) */`
274			`.miso(1'b1),/* SPI 'miso' signal (input) */`
275			`.ss()/* SPI 'ss' signal (if send buffer is maintained full the ss signal will not go high between between transmit chars)(output) */`
276			`);`
277
278			`wire ja_scl;`
279			`wire ja_sda;`
280
281			`twi_s #(`
282			`.DINAMIC_BAUDRATE("TRUE"),`
283			`.BAUDRATE_DIVIDER(255),`
284			`.ADDRESS('h800),`
285			.BUS_ADDR_DATA_LEN(`BUS_ADDR_DATA_LEN_SIM)
286			`)twi_inst(`
287			`.rst(sys_rst),`
288			`.clk(core_clk),`
289			`.addr(data_addr),`
290			`.wr(data_we),`
291			`.rd(data_re),`
292			`.bus_in(data_out),`
293			`.bus_out(data_in),`
294			`.int_tx_cmpl(),`
295			`.int_rx_cmpl(),`
296			`.int_tx_rst(),`
297			`.int_rx_rst(),`
298
299			`.scl(ja_scl),`
300			`.sda(ja_sda)`
301			`);`
302			`wire lcd_h_int;`
303			`wire lcd_v_int;`
304			`wire lcd_de;`
305			`wire [7:0]ja_int;`
306			`wire [7:0]jb_int;`
307			`wire [7:0]jc_int;`
308			`wire lcd_clk_10;`
309			`ifndef USE_HDMI_OUTPUT
310			`assign ja = {ja_int[7:1], lcd_clk_10};`
311			`assign jb = {jb_int[7:1], lcd_h_int};`
312			`assign jc = {jc_int[7:1], lcd_v_int};`
313			`endif
314
315			`lcd # (`
316			`.MASTER("TRUE"),`
317			`.DEBUG(""),//"PATERN_RASTER"`
318			`.DISPLAY_CFG("1280_720_60_DISPLAY_74_25_Mhz"),`
319
320			`.ADDRESS('hE0),`
321			`.BUS_VRAM_ADDR_LEN(24),`
322			`.BUS_VRAM_DATA_LEN(8),`
323			`.BUS_ADDR_DATA_LEN(16),`
324
325			`.DINAMIC_CONFIG("FALSE"),`
326			`.VRAM_BASE_ADDRESS_CONF(0),`
327			`/* This timings are for AT070TN92 LCD display module but is not tacken in account because we will load a default setup with DISPLAY_CFG parameter.*/`
328			`.H_RES_CONF(720),`
329			`.H_BACK_PORCH_CONF(138),`
330			`.H_FRONT_PORCH_CONF(16),`
331			`.H_PULSE_WIDTH_CONF(62),`
332			`.V_RES_CONF(480),`
333			`.V_BACK_PORCH_CONF(45),`
334			`.V_FRONT_PORCH_CONF(9),`
335			`.V_PULSE_WIDTH_CONF(6),`
336			`.PIXEL_SIZE_CONF(16),`
337			`.HSYNK_INVERTED_CONF(1'b0),`
338			`.VSYNK_INVERTED_CONF(1'b0),`
339			`.DATA_ENABLE_INVERTED_CONF(1'b0),`
340			`.DEDICATED_VRAM_SIZE(800 * 480)`
341			`)lcd_inst(`
342			`.rst(sys_rst),`
343			`.ctrl_clk(core_clk),`
344			`.ctrl_addr(data_addr),`
345			`.ctrl_wr(data_we),`
346			`.ctrl_rd(data_re),`
347			`.ctrl_data_in(data_out),`
348			`.ctrl_data_out(data_in),`
349
350			`.vmem_addr(ram_addr_bus),`
351			`.vmem_in(data_out),`
352			`.vmem_out(data_in),`
353			`.vmem_rd(1'b0),`
354			`.vmem_wr(data_we & ram_data_sel),`
355
356			`ifdef USE_HDMI_OUTPUT
357			`.lcd_clk(lcd_clk_10),`
358			`else
359			`.lcd_clk(lcd_clk),`
360			`endif
361			`.lcd_h_synk(lcd_h_int),`
362			`.lcd_v_synk(lcd_v_int),`
363			`.lcd_r(ja_int),`
364			`.lcd_g(jb_int),`
365			`.lcd_b(jc_int),`
366			`.lcd_de(lcd_de)`
367			`);`
368
369			`ifdef USE_HDMI_OUTPUT
370			`hdmi_out # (`
371			`.PLATFORM("XILINX_ARTIX_7")`
372			`)hdmi_out_inst(`
373			`.rst(sys_rst),`
374			`.clk(lcd_clk),`
375			`.hdmi_tx_cec(hdmi_tx_cec),`
376			`.hdmi_tx_clk_n(hdmi_tx_clk_n),`
377			`.hdmi_tx_clk_p(hdmi_tx_clk_p),`
378			`.hdmi_tx_hpd(hdmi_tx_hpd),`
379			`.hdmi_tx_rscl(hdmi_tx_rscl),`
380			`.hdmi_tx_rsda(hdmi_tx_rsda),`
381			`.hdmi_tx_n(hdmi_tx_n),`
382			`.hdmi_tx_p(hdmi_tx_p),`
383
384			`.lcd_clk_out(lcd_clk_10),`
385			`.lcd_h_synk(lcd_h_int),`
386			`.lcd_v_synk(lcd_v_int),`
387			`.lcd_r('hAA),`
388			`.lcd_g('hDB),`
389			`.lcd_b('h24),`
390			`.lcd_de(lcd_de)`
391			`);`
392			`endif
393			//`endif //!_0_
394
395			`rom #(`
396			.ADDR_ROM_BUS_WIDTH(`BUS_ADDR_PGM_LEN_SIM),
397			`.ROM_PATH("core1ROM.mem"),`
398			`.SYNCHRONOUS("FALSE")`
399			`)rom(`
400			`.clk(core_clk),`
401			`.a(pgm_addr),`
402			`.d(pgm_data)`
403			`);`
404
405			`ram #(`
406			.ADDR_BUS_WIDTH(`DATA_MEM_SIZE_LEN_SIM),
407			`.RAM_PATH(""),`
408			`.SYNCHRONOUS("TRUE")`
409			`)ram(`
410			`.clk(core_clk),`
411			`.re(data_re & ram_data_sel),`
412			`.we(data_we & ram_data_sel),`
413			`.a(ram_addr_bus),`
414			`.d_in(data_out),`
415			`.d_out(data_in)`
416			`);`
417
418			`mega_core #(`
419			`.CORE_CONFIG("XMEGA"),// Supported: "REDUCED", "MINIMAL", "CLASSIC_8K", "CLASSIC_128K", "ENHANCED_8K", "ENHANCED_128K", "ENHANCED_4M", "XMEGA"`
420			.BUS_ADDR_PGM_WIDTH(`BUS_ADDR_PGM_LEN_SIM),
421			.BUS_ADDR_DATA_WIDTH(`BUS_ADDR_DATA_LEN_SIM),
422			`.USE_BRAM_ROM("FALSE"),`
423			`.WATCHDOG_CNT_WIDTH(21),/* If is 0 the watchdog is disabled */`
424			`.VECTOR_INT_TABLE_SIZE(10),`
425			`.STORE_INTERUPTS("FALSE"),`
426			`.MAP_REGS_IN_TO_SRAM_SECTION("FALSE")`
427			`)core(`
428			`.rst(rst),`
429			`.sys_rst(sys_rst),/* Output reset provided by core thru watchdog to the rest of the system */`
430			`.clk(core_clk),`
431			`.clk_wdt(core_clk),`
432
433			`.pgm_addr(pgm_addr),`
434			`.pgm_data(pgm_data),`
435
436			`.data_re(data_re),`
437			`.data_we(data_we),`
438			`.data_addr(data_addr),`
439			`.data_in(data_in),`
440			`.data_out(data_out),`
441
442			`.io_re(io_re),`
443			`.io_we(io_we),`
444			`.io_addr(io_addr),`
445			`.io_in(io_in),`
446			`.io_out(io_out),`
447
448			`.int_sig({int_uart_a_tx_buff_empty, int_uart_a_tx_compl, int_uart_a_rx_rcv, int_spi_a, int_pio_f, int_pio_e, int_pio_d, int_pio_c, int_pio_b, int_pio_a, rtc_int}),`
449			`.int_rst(int_rst),`
450			`.wdt_rst_out()`
451			`);`
452
453
454			`endmodule`
455
456