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[/] [audio/] [trunk/] [HD_ADPCM/] [HD_ADPCM_1Bit_Stereo_Decoder/] [HD_ADPCM_Codec.eda.rpt] - Blame information for rev 6

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Line No. Rev Author Line
1 6 ashematian
EDA Netlist Writer report for HD_ADPCM_Codec
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Tue May 11 23:50:10 2010
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Quartus II Version 9.0 Build 132 02/25/2009 SJ Web Edition
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---------------------
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; Table of Contents ;
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---------------------
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  1. Legal Notice
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  2. EDA Netlist Writer Summary
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  3. Simulation Settings
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  4. Simulation Generated Files
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  5. EDA Netlist Writer Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 1991-2009 Altera Corporation
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, Altera MegaCore Function License
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Agreement, or other applicable license agreement, including,
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without limitation, that your use is for the sole purpose of
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programming logic devices manufactured by Altera and sold by
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Altera or its authorized distributors.  Please refer to the
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applicable agreement for further details.
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+-------------------------------------------------------------------+
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; EDA Netlist Writer Summary                                        ;
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+---------------------------+---------------------------------------+
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; EDA Netlist Writer Status ; Successful - Tue May 11 23:50:10 2010 ;
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; Revision Name             ; HD_ADPCM_Codec                        ;
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; Top-level Entity Name     ; HD_ADPCM_Codec                        ;
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; Family                    ; Cyclone II                            ;
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; Simulation Files Creation ; Successful                            ;
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+---------------------------+---------------------------------------+
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+---------------------------------------------------------------------------------------------------------------------+
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; Simulation Settings                                                                                                 ;
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+---------------------------------------------------------------------------------------------------+-----------------+
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; Option                                                                                            ; Setting         ;
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+---------------------------------------------------------------------------------------------------+-----------------+
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; Tool Name                                                                                         ; ModelSim (VHDL) ;
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; Generate netlist for functional simulation only                                                   ; Off             ;
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; Time scale                                                                                        ; 1 ps            ;
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; Truncate long hierarchy paths                                                                     ; Off             ;
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; Map illegal HDL characters                                                                        ; Off             ;
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; Flatten buses into individual nodes                                                               ; Off             ;
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; Maintain hierarchy                                                                                ; Off             ;
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; Bring out device-wide set/reset signals as ports                                                  ; Off             ;
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; Enable glitch filtering                                                                           ; Off             ;
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; Do not write top level VHDL entity                                                                ; Off             ;
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; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off             ;
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; Architecture name in VHDL output netlist                                                          ; structure       ;
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; Generate third-party EDA tool command script for RTL functional simulation                        ; Off             ;
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; Generate third-party EDA tool command script for gate-level simulation                            ; Off             ;
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+---------------------------------------------------------------------------------------------------+-----------------+
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+-------------------------------------------------------------------------------------+
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; Simulation Generated Files                                                          ;
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+-------------------------------------------------------------------------------------+
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; Generated Files                                                                     ;
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+-------------------------------------------------------------------------------------+
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; D:/HD_ADPCM/HD_ADPCM_1Bit_Stereo_Decoder/simulation/modelsim/HD_ADPCM_Codec.vho     ;
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; D:/HD_ADPCM/HD_ADPCM_1Bit_Stereo_Decoder/simulation/modelsim/HD_ADPCM_Codec_vhd.sdo ;
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+-------------------------------------------------------------------------------------+
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+-----------------------------+
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; EDA Netlist Writer Messages ;
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+-----------------------------+
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Info: *******************************************************************
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Info: Running Quartus II EDA Netlist Writer
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    Info: Version 9.0 Build 132 02/25/2009 SJ Web Edition
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    Info: Processing started: Tue May 11 23:50:08 2010
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Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off HD_ADPCM_Codec -c HD_ADPCM_Codec
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Info: Generated files "HD_ADPCM_Codec.vho" and "HD_ADPCM_Codec_vhd.sdo" in directory "D:/HD_ADPCM/HD_ADPCM_1Bit_Stereo_Decoder/simulation/modelsim/" for EDA simulation tool
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Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings
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    Info: Peak virtual memory: 139 megabytes
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    Info: Processing ended: Tue May 11 23:50:10 2010
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    Info: Elapsed time: 00:00:02
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    Info: Total CPU time (on all processors): 00:00:02
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