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[/] [avs_aes/] [trunk/] [rtl/] [VHDL/] [memory_word.vhd] - Blame information for rev 11

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-- This file is part of the project      avs_aes
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-- see: http://opencores.org/project,avs_aes
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--
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-- description: Register - nothing special
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--
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-------------------------------------------------------------------------------
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--
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-- Author(s):
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--         Thomas Ruschival -- ruschi@opencores.org (www.ruschival.de)
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--
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--------------------------------------------------------------------------------
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-- Copyright (c) 2009, Authors and opencores.org
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without modification,
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-- are permitted provided that the following conditions are met:
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--        * Redistributions of source code must retain the above copyright notice,
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--        this list of conditions and the following disclaimer.
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--        * Redistributions in binary form must reproduce the above copyright notice,
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--        this list of conditions and the following disclaimer in the documentation
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--        and/or other materials provided with the distribution.
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--        * Neither the name of the organization nor the names of its contributors
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--        may be used to endorse or promote products derived from this software without
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--        specific prior written permission.
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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-- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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-- THE POSSIBILITY OF SUCH DAMAGE
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-------------------------------------------------------------------------------
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-- version management:
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-- $Author$
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-- $Date$
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-- $Revision$                   
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity memory_word is
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        generic (
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                IOwidth : POSITIVE := 1);               -- width in bits
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        port (
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                data_in  : in  STD_LOGIC_VECTOR(IOwidth-1 downto 0);
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                data_out : out STD_LOGIC_VECTOR(IOwidth-1 downto 0);
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                res_n    : in  STD_LOGIC;               -- system reset active low
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                ena              : in  STD_LOGIC;               -- enable write
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                clk              : in  STD_LOGIC);              -- system clock
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end entity memory_word;
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architecture arch1 of memory_word is
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        signal data : STD_LOGIC_VECTOR(IOwidth-1 downto 0);       -- storage
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begin  -- architecture arch1
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        -- purpose: write data to register at clock edge if enabled
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        -- type   : sequential
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        -- inputs : clk, res_n, data_in,ena
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        write_mem : process (clk, res_n) is
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        begin  -- process write_mem
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                if res_n = '0' then
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                        data <= (others => '0');
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                elsif rising_edge(clk) then
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                        if ena = '1' then
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                                data <= data_in;
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                        end if;
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                end if;
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        end process write_mem;
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        -- data can always be read
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        data_out <= data;
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end architecture arch1;

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