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[/] [avs_aes/] [trunk/] [rtl/] [VHDL/] [shiftrow_inv.vhd] - Blame information for rev 20

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--------------------------------------------------------------------------------
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-- This file is part of the project  avs_aes
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-- see: http://opencores.org/project,avs_aes
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--
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-- description: DECRYPTION implementation of Shift row.
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-- Shift Row rotates the Rows of the AES Block
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-- This module takes the whole Rijdael state as input, extracts the rows,
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-- shifts them and rebuilts the state.
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--
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-------------------------------------------------------------------------------
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--
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-- Author(s):
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--         Thomas Ruschival -- ruschi@opencores.org (www.ruschival.de)
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--
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--------------------------------------------------------------------------------
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-- Copyright (c) 2009, Authors and opencores.org
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without modification,
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-- are permitted provided that the following conditions are met:
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--    * Redistributions of source code must retain the above copyright notice,
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--    this list of conditions and the following disclaimer.
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--    * Redistributions in binary form must reproduce the above copyright notice,
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--    this list of conditions and the following disclaimer in the documentation
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--    and/or other materials provided with the distribution.
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--    * Neither the name of the organization nor the names of its contributors
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--    may be used to endorse or promote products derived from this software without
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--    specific prior written permission.
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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-- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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-- THE POSSIBILITY OF SUCH DAMAGE
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-------------------------------------------------------------------------------
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-- version management:
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-- $Author::                                         $
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-- $Date::                                           $
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-- $Revision::                                       $
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.numeric_std.all;
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use IEEE.std_logic_1164.all;
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library avs_aes_lib;
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use avs_aes_lib.avs_aes_pkg.all;
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architecture inv of Shiftrow is
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        -- type of converting the columns into rows
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        subtype ROW is BYTEARRAY(0 to 3);
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        -- Row signal for easier handling of the shift operations
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        signal row1_in  : Row;                          -- 1st row
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        signal row2_in  : Row;                          -- 2nd row
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        signal row3_in  : Row;                          -- 3rd row
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        signal row4_in  : Row;                          -- 4th row
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        -- single rows after shift operation
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        -- row1 of the shifted state = row1 of unshifted state 
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        signal row2_out : Row;                          -- 2nd row
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        signal row3_out : Row;                          -- 3rd row
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        signal row4_out : Row;                          -- 4th row
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begin  -- architecture arch1
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        -- purpose: build the temorary internal signals for easier handling
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        -- type   : combinational
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        -- inputs : state_in
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        -- outputs: state_out
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        build_in : process (state_in) is
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        begin  -- process build_in
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                -- state is a DWORD array with 32 Byte in 4 columns
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                -- thus we loop through the columns and slice the column in its bytes
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                for col_cnt in 0 to (state_in'high) loop
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                        row1_in(col_cnt) <= state_in(col_cnt)(31 downto 24);
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                        row2_in(col_cnt) <= state_in(col_cnt)(23 downto 16);
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                        row3_in(col_cnt) <= state_in(col_cnt)(15 downto 8);
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                        row4_in(col_cnt) <= state_in(col_cnt)(7 downto 0);
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                end loop;  -- col_cnt
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        end process build_in;
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        -- purpose: Undo the shifting of rows
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        -- type   : combinational
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        -- inputs : row(1 to 4)_in
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        -- outputs: row(1 to 4)_out
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        shifter : process (row2_in, row3_in, row4_in) is
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        begin
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                -- row2 is always shifted by one cell
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                row2_out <= row2_in(row2_in'right) & row2_in(row2_in'left to row2_in'right-1);
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                -- row3 is shifted by two
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                row3_out <= row3_in(row3_in'right-1 to row3_in'right) & row3_in(row3_in'left to row3_in'right-2);
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                -- rotate by 3 right
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                row4_out <= row4_in(row4_in'right-2 to row4_in'right) & row4_in(row4_in'left to row4_in'right-3);
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        end process shifter;
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        -- purpose: rebuilt the state form the shifted rows
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        -- type   : combinational
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        -- inputs : row1_out, row2_out, row3_out, row4_out
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        -- outputs: state_out
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        rebuilt_state : process (row1_in, row2_out, row3_out, row4_out) is
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        begin  -- process rebuilt_state 
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                for col_cnt in 0 to state_out'high loop   -- works because 15/4=3
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                        state_out(col_cnt)(31 downto 24) <= row1_in(col_cnt);
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                        state_out(col_cnt)(23 downto 16) <= row2_out(col_cnt);
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                        state_out(col_cnt)(15 downto 8)  <= row3_out(col_cnt);
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                        state_out(col_cnt)(7 downto 0)    <= row4_out(col_cnt);
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                end loop;  -- col_cnt           
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        end process rebuilt_state;
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end architecture inv;

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