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1 2 eyalhoc
/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  Author: Eyal Hochberg                                      ////
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////          eyal@provartec.com                                 ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org                  ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2010 Provartec LTD                            ////
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//// www.provartec.com                                           ////
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//// info@provartec.com                                          ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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//// This source file is free software; you can redistribute it  ////
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//// and/or modify it under the terms of the GNU Lesser General  ////
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//// Public License as published by the Free Software Foundation.////
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////                                                             ////
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//// This source is distributed in the hope that it will be      ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
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//// PURPOSE.  See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html              ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
29 6 eyalhoc
 
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//////////////////////////////////////
31
//
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// General:
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//   The AXI master has an internal master per ID. 
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//   These internal masters work simultaniously and an interconnect matrix connets them. 
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// 
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//
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// I/F :
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//   idle - all internal masters emptied their command FIFOs
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//   scrbrd_empty - all scoreboard checks have been completed (for random testing)
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//
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//
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// Tasks:
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//
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// enable(input master_num)
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//   Description: Enables master
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//   Parameters: master_num - number of internal master
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//
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// enable_all()  
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//   Description: Enables all masters
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//
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// write_single(input master_num, input addr, input wdata)
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//   Description: write a single AXI burst (1 data cycle)
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//   Parameters: master_num - number of internal master
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//           addr  - address
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//           wdata - write data
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// 
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// read_single(input master_num, input addr, output rdata)
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//   Description: read a single AXI burst (1 data cycle)
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//   Parameters: master_num - number of internal master
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//               addr  - address
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//               rdata - return read data
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//
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// check_single(input master_num, input addr, input expected)
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//   Description: read a single AXI burst and gives an error if the data read does not match expected
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//   Parameters: master_num - number of internal master
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//               addr  - address
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//               expected - expected read data
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//
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// write_and_check_single(input master_num, input addr, input data)
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//   Description: write a single AXI burst read it back and compare the write and read data
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//   Parameters: master_num - number of internal master
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//               addr  - address
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//               data - data to write and expect on read
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//
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// insert_wr_cmd(input master_num, input addr, input len, input size)
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//   Description: add an AXI write burst to command FIFO
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//   Parameters: master_num - number of internal master
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//               addr - address
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//               len - AXI LEN (data strobe number)
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//               size - AXI SIZE (data width)
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//  
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// insert_rd_cmd(input master_num, input addr, input len, input size)
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//   Description: add an AXI read burst to command FIFO
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//   Parameters: master_num - number of internal master
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//               addr - address
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//               len - AXI LEN (data strobe number)
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//               size - AXI SIZE (data width)
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//  
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// insert_wr_data(input master_num, input wdata)
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//   Description: add a single data to data FIFO (to be used in write bursts)
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//   Parameters: master_num - number of internal master
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//               wdata - write data
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//  
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// insert_wr_incr_data(input master_num, input addr, input len, input size)
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//   Description: add an AXI write burst to command FIFO will use incremental data (no need to use insert_wr_data)
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//   Parameters: master_num - number of internal master
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//               addr - address
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//               len - AXI LEN (data strobe number)
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//               size - AXI SIZE (data width)
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//  
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// insert_rand_chk(input master_num, input burst_num)
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//   Description: add multiple commands to command FIFO. Each command writes incremental data to a random address, reads the data back and checks the data. Useful for random testing.
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//   Parameters: master_num - number of internal master
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//               burst_num - total number of bursts to check
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//  
106 9 eyalhoc
// insert_rand(input burst_num)
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//   Description: disperces burst_num between internal masters and calls insert_rand_chk for each master
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//   Parameters:  burst_num - total number of bursts to check (combined)
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//
110 6 eyalhoc
//  
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//  Parameters:
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//  
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//    For random testing: (changing these values automatically update interanl masters)
114 10 eyalhoc
//      ahb_bursts - if set, bursts will only be of length 1, 4, 8 or 16.
115 6 eyalhoc
//      len_min  - minimum burst AXI LEN (length)
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//      len_max  - maximum burst AXI LEN (length)
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//      size_min - minimum burst AXI SIZE (width)
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//      size_max - maximum burst AXI SIZE (width)
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//      addr_min - minimum address (in bytes)
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//      addr_max - maximum address (in bytes)
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//  
122
//////////////////////////////////////
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124
OUTFILE PREFIX.v
125
 
126
INCLUDE def_axi_master.txt
127
 
128 14 eyalhoc
ITER IDX ID_NUM
129 6 eyalhoc
module PREFIX(PORTS);
130
 
131 9 eyalhoc
`include "prgen_rand.v"
132
 
133 6 eyalhoc
   input                               clk;
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   input                               reset;
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136
   port                                GROUP_STUB_AXI;
137
 
138
   output                              idle;
139
   output                              scrbrd_empty;
140
 
141
 
142
   //random parameters
143
   integer                             GROUP_AXI_MASTER_RAND = GROUP_AXI_MASTER_RAND.DEFAULT;
144
 
145 14 eyalhoc
   wire                                GROUP_STUB_AXI_IDX;
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   wire                                idle_IDX;
147
   wire                                scrbrd_empty_IDX;
148 6 eyalhoc
 
149
 
150
   always @(*)
151
     begin
152
        #FFD;
153 14 eyalhoc
        PREFIX_singleIDX.GROUP_AXI_MASTER_RAND = GROUP_AXI_MASTER_RAND;
154 6 eyalhoc
     end
155
 
156 14 eyalhoc
   assign                              idle = CONCAT(idle_IDX &);
157
   assign                              scrbrd_empty = CONCAT(scrbrd_empty_IDX &);
158 6 eyalhoc
 
159
 
160
   CREATE axi_master_single.v
161
 
162 14 eyalhoc
     LOOP IDX ID_NUM
163 17 eyalhoc
   PREFIX_single #(IDX, ID_BITS'bGROUP_AXI_ID[IDX], CMD_DEPTH)
164 14 eyalhoc
   PREFIX_singleIDX(
165 6 eyalhoc
                   .clk(clk),
166
                   .reset(reset),
167 14 eyalhoc
                   .GROUP_STUB_AXI(GROUP_STUB_AXI_IDX),
168
                   .idle(idle_IDX),
169
                   .scrbrd_empty(scrbrd_empty_IDX)
170 6 eyalhoc
                   );
171 9 eyalhoc
 
172 14 eyalhoc
   ENDLOOP IDX
173 6 eyalhoc
 
174
     IFDEF TRUE(ID_NUM==1)
175
 
176
   assign GROUP_STUB_AXI.OUT = GROUP_STUB_AXI_0.OUT;
177
   assign GROUP_STUB_AXI_0.IN = GROUP_STUB_AXI.IN;
178
 
179
     ELSE TRUE(ID_NUM==1)
180
 
181 14 eyalhoc
CREATE ic.v \\
182
DEFCMD(SWAP.GLOBAL CONST(PREFIX) PREFIX) \\
183 9 eyalhoc
DEFCMD(SWAP.GLOBAL MASTER_NUM ID_NUM) \\
184
DEFCMD(SWAP.GLOBAL SLAVE_NUM 1) \\
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DEFCMD(SWAP.GLOBAL CONST(ID_BITS) ID_BITS) \\
186
DEFCMD(SWAP.GLOBAL CONST(CMD_DEPTH) CMD_DEPTH) \\
187
DEFCMD(SWAP.GLOBAL CONST(DATA_BITS) DATA_BITS) \\
188 14 eyalhoc
DEFCMD(SWAP.GLOBAL CONST(ADDR_BITS) ADDR_BITS) \\
189 17 eyalhoc
DEFCMD(DEFINE.GLOBAL UNIQUE_ID) \\
190 14 eyalhoc
DEFCMD(SWAP.GLOBAL CONST(USER_BITS) 0)
191
LOOP IDX ID_NUM
192
  STOMP NEWLINE
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  DEFCMD(GROUP.GLOBAL MIDX_ID overrides { ) \\
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  DEFCMD(GROUP_AXI_ID[IDX]) \\
195
  DEFCMD(})
196
ENDLOOP IDX
197 6 eyalhoc
 
198 14 eyalhoc
 
199 6 eyalhoc
    PREFIX_ic PREFIX_ic(
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                       .clk(clk),
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                       .reset(reset),
202 14 eyalhoc
                       .MIDX_GROUP_STUB_AXI(GROUP_STUB_AXI_IDX),
203 6 eyalhoc
                       .S0_GROUP_STUB_AXI(GROUP_STUB_AXI),
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                       STOMP ,
205
 
206
      );
207
 
208
     ENDIF TRUE(ID_NUM==1)
209
 
210
 
211
 
212
   task check_master_num;
213
      input [24*8-1:0] task_name;
214
      input [31:0] master_num;
215
      begin
216
         if (master_num >= ID_NUM)
217
           begin
218
              $display("FATAL ERROR: task %0s called for master %0d that does not exist.\tTime: %0d ns.", task_name, master_num, $time);
219
           end
220
      end
221
   endtask
222
 
223
   task enable;
224
      input [31:0] master_num;
225
      begin
226
         check_master_num("enable", master_num);
227
         case (master_num)
228 14 eyalhoc
           IDX : PREFIX_singleIDX.enable = 1;
229 6 eyalhoc
         endcase
230
      end
231
   endtask
232
 
233
   task enable_all;
234
      begin
235 14 eyalhoc
         PREFIX_singleIDX.enable = 1;
236 6 eyalhoc
      end
237
   endtask
238
 
239
   task write_single;
240
      input [31:0] master_num;
241
      input [ADDR_BITS-1:0]  addr;
242
      input [DATA_BITS-1:0]  wdata;
243
      begin
244
         check_master_num("write_single", master_num);
245
         case (master_num)
246 14 eyalhoc
           IDX : PREFIX_singleIDX.write_single(addr, wdata);
247 6 eyalhoc
         endcase
248
      end
249
   endtask
250
 
251
   task read_single;
252
      input [31:0] master_num;
253
      input [ADDR_BITS-1:0]  addr;
254
      output [DATA_BITS-1:0]  rdata;
255
      begin
256
         check_master_num("read_single", master_num);
257
         case (master_num)
258 14 eyalhoc
           IDX : PREFIX_singleIDX.read_single(addr, rdata);
259 6 eyalhoc
         endcase
260
      end
261
   endtask
262
 
263
   task check_single;
264
      input [31:0] master_num;
265
      input [ADDR_BITS-1:0]  addr;
266
      input [DATA_BITS-1:0]  expected;
267
      begin
268
         check_master_num("check_single", master_num);
269
         case (master_num)
270 14 eyalhoc
           IDX : PREFIX_singleIDX.check_single(addr, expected);
271 6 eyalhoc
         endcase
272
      end
273
   endtask
274
 
275
   task write_and_check_single;
276
      input [31:0] master_num;
277
      input [ADDR_BITS-1:0]  addr;
278
      input [DATA_BITS-1:0]  data;
279
      begin
280
         check_master_num("write_and_check_single", master_num);
281
         case (master_num)
282 14 eyalhoc
           IDX : PREFIX_singleIDX.write_and_check_single(addr, data);
283 6 eyalhoc
         endcase
284
      end
285
   endtask
286
 
287
   task insert_wr_cmd;
288
      input [31:0] master_num;
289
      input [ADDR_BITS-1:0]  addr;
290
      input [LEN_BITS-1:0]   len;
291
      input [SIZE_BITS-1:0]  size;
292
      begin
293
         check_master_num("insert_wr_cmd", master_num);
294
         case (master_num)
295 14 eyalhoc
           IDX : PREFIX_singleIDX.insert_wr_cmd(addr, len, size);
296 6 eyalhoc
         endcase
297
      end
298
   endtask
299
 
300
   task insert_rd_cmd;
301
      input [31:0] master_num;
302
      input [ADDR_BITS-1:0]  addr;
303
      input [LEN_BITS-1:0]   len;
304
      input [SIZE_BITS-1:0]  size;
305
      begin
306
         check_master_num("insert_rd_cmd", master_num);
307
         case (master_num)
308 14 eyalhoc
           IDX : PREFIX_singleIDX.insert_rd_cmd(addr, len, size);
309 6 eyalhoc
         endcase
310
      end
311
   endtask
312
 
313
   task insert_wr_data;
314
      input [31:0] master_num;
315
      input [DATA_BITS-1:0]  wdata;
316
      begin
317
         check_master_num("insert_wr_data", master_num);
318
         case (master_num)
319 14 eyalhoc
           IDX : PREFIX_singleIDX.insert_wr_data(wdata);
320 6 eyalhoc
         endcase
321
      end
322
   endtask
323
 
324
   task insert_wr_incr_data;
325
      input [31:0] master_num;
326
      input [ADDR_BITS-1:0]  addr;
327
      input [LEN_BITS-1:0]   len;
328
      input [SIZE_BITS-1:0]  size;
329
      begin
330
         check_master_num("insert_wr_incr_data", master_num);
331
         case (master_num)
332 14 eyalhoc
           IDX : PREFIX_singleIDX.insert_wr_incr_data(addr, len, size);
333 6 eyalhoc
         endcase
334
      end
335
   endtask
336
 
337
   task insert_rand_chk;
338
      input [31:0] master_num;
339
      input [31:0] burst_num;
340
      begin
341
         check_master_num("insert_rand_chk", master_num);
342
         case (master_num)
343 14 eyalhoc
           IDX : PREFIX_singleIDX.insert_rand_chk(burst_num);
344 6 eyalhoc
         endcase
345
      end
346
   endtask
347
 
348 9 eyalhoc
   task insert_rand;
349
      input [31:0] burst_num;
350
 
351
      reg [31:0] burst_numIDX;
352
      integer remain;
353
      begin
354
         remain = burst_num;
355
         LOOP IDX ID_NUM
356
         if (remain > 0)
357
           begin
358
              burst_numIDX = rand(1, remain);
359
              remain = remain - burst_numIDX;
360
              insert_rand_chk(IDX, burst_numIDX);
361
           end
362
         ENDLOOP IDX
363
      end
364
   endtask
365 6 eyalhoc
 
366
 
367
endmodule
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