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[/] [axi_master/] [trunk/] [src/] [base/] [def_ic_static.txt] - Blame information for rev 21

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<##//////////////////////////////////////////////////////////////////
////                                                             ////
////  Author: Eyal Hochberg                                      ////
////          eyal@provartec.com                                 ////
////                                                             ////
////  Downloaded from: http://www.opencores.org                  ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2010 Provartec LTD                            ////
//// www.provartec.com                                           ////
//// info@provartec.com                                          ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
//// This source file is free software; you can redistribute it  ////
//// and/or modify it under the terms of the GNU Lesser General  ////
//// Public License as published by the Free Software Foundation.////
////                                                             ////
//// This source is distributed in the hope that it will be      ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
//// PURPOSE.  See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html              ////
////                                                             ////
//////////////////////////////////////////////////////////////////##>
 
VERIFY (DATA_BITS in 32, 64) ##stub supports 32 or 64 bits data bus
VERIFY (SIZE_BITS in 2, 3) ##stub supports 32 or 64 bits data bus
 
VERIFY (MASTER_NUM in 1..8)
VERIFY (SLAVE_NUM in 1..16)
 
SWAP.GLOBAL MODEL_NAME AXI interconnect fabric
 
SWAP MSTRS MASTER_NUM
SWAP SLVS EXPR(SLAVE_NUM+DVAL(DEF_DECERR_SLV))
 
LOOP MX MSTRS
LOOP SX SLVS
 
SWAP MSTR_BITS LOG2(MSTRS)
SWAP SLV_BITS  LOG2(SLVS)
 
SWAP SERR EXPR(SLVS-1)
 
IFDEF UNIQUE_ID
SWAP ID_BITS  MSTR_ID_BITS
SWAP ADD_ID   NULL
ELSE UNIQUE_ID
SWAP ID_BITS  EXPR(MSTR_ID_BITS+EXTRA_BITS)
SWAP ADD_ID   BIN(MX MSTR_BITS NOPRE)_
ENDIF UNIQUE_ID
 
GROUP IC_AXI_A is {
    ID       ID_BITS                input  SON(CHANGE 1)
    ADDR     ADDR_BITS              input
    LEN      4                      input
    SIZE     SIZE_BITS              input
    BURST    2                      input
    CACHE    4                      input
    PROT     3                      input
    LOCK     2                      input
    USER     USER_BITS              input
    VALID    1                      input
    READY    1                      output
}
 
GROUP IC_AXI_W is {
    ID        ID_BITS                input  SON(CHANGE 1)
    DATA      DATA_BITS              input
    STRB      DATA_BITS/8            input
    LAST      1                      input
    USER      USER_BITS              input
    VALID     1                      input
    READY     1                      output
}
 
GROUP IC_AXI_B is {
    ID        ID_BITS                output  SON(CHANGE 1)
    RESP      2                      output
    USER      USER_BITS              output
    VALID     1                      output
    READY     1                      input
}
 
GROUP IC_AXI_R is {
    ID        ID_BITS                output  SON(CHANGE 1)
    DATA      DATA_BITS              output
    RESP      2                      output
    LAST      1                      output
    USER      USER_BITS              output
    VALID     1                      output
    READY     1                      input
}
 
GROUP IC_AXI joins {
    GROUP IC_AXI_A prefix_AW
    GROUP IC_AXI_W prefix_W
    GROUP IC_AXI_B prefix_B
    GROUP IC_AXI_A prefix_AR
    GROUP IC_AXI_R prefix_R
}
 
GROUP IC_AXI_CMD is {
    SLV       SLV_BITS               input
    ID        ID_BITS                input  SON(CHANGE 1)
    VALID     1                      input
    READY     1                      input
}

Line No.	Rev	Author	Line
1	21	eyalhoc	`<##//////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Author: Eyal Hochberg ////`
4			`//// eyal@provartec.com ////`
5			`//// ////`
6			`//// Downloaded from: http://www.opencores.org ////`
7			`/////////////////////////////////////////////////////////////////////`
8			`//// ////`
9			`//// Copyright (C) 2010 Provartec LTD ////`
10			`//// www.provartec.com ////`
11			`//// info@provartec.com ////`
12			`//// ////`
13			`//// This source file may be used and distributed without ////`
14			`//// restriction provided that this copyright statement is not ////`
15			`//// removed from the file and that any derivative work contains ////`
16			`//// the original copyright notice and the associated disclaimer.////`
17			`//// ////`
18			`//// This source file is free software; you can redistribute it ////`
19			`//// and/or modify it under the terms of the GNU Lesser General ////`
20			`//// Public License as published by the Free Software Foundation.////`
21			`//// ////`
22			`//// This source is distributed in the hope that it will be ////`
23			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
24			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
25			`//// PURPOSE. See the GNU Lesser General Public License for more////`
26			`//// details. http://www.gnu.org/licenses/lgpl.html ////`
27			`//// ////`
28			`//////////////////////////////////////////////////////////////////##>`
29	16	eyalhoc
30	20	eyalhoc	`VERIFY (DATA_BITS in 32, 64) ##stub supports 32 or 64 bits data bus`
31			`VERIFY (SIZE_BITS in 2, 3) ##stub supports 32 or 64 bits data bus`
32	21	eyalhoc
33			`VERIFY (MASTER_NUM in 1..8)`
34			`VERIFY (SLAVE_NUM in 1..16)`
35	20	eyalhoc
36	15	eyalhoc	`SWAP.GLOBAL MODEL_NAME AXI interconnect fabric`
37	14	eyalhoc
38	2	eyalhoc	`SWAP MSTRS MASTER_NUM`
39			`SWAP SLVS EXPR(SLAVE_NUM+DVAL(DEF_DECERR_SLV))`
40
41			`LOOP MX MSTRS`
42			`LOOP SX SLVS`
43
44			`SWAP MSTR_BITS LOG2(MSTRS)`
45			`SWAP SLV_BITS LOG2(SLVS)`
46
47			`SWAP SERR EXPR(SLVS-1)`
48
49	17	eyalhoc	`IFDEF UNIQUE_ID`
50			`SWAP ID_BITS MSTR_ID_BITS`
51			`SWAP ADD_ID NULL`
52			`ELSE UNIQUE_ID`
53			`SWAP ID_BITS EXPR(MSTR_ID_BITS+EXTRA_BITS)`
54			`SWAP ADD_ID BIN(MX MSTR_BITS NOPRE)_`
55			`ENDIF UNIQUE_ID`
56
57	2	eyalhoc	`GROUP IC_AXI_A is {`
58	17	eyalhoc	`ID ID_BITS input SON(CHANGE 1)`
59	2	eyalhoc	`ADDR ADDR_BITS input`
60			`LEN 4 input`
61	20	eyalhoc	`SIZE SIZE_BITS input`
62	2	eyalhoc	`BURST 2 input`
63			`CACHE 4 input`
64			`PROT 3 input`
65			`LOCK 2 input`
66			`USER USER_BITS input`
67			`VALID 1 input`
68			`READY 1 output`
69			`}`
70
71			`GROUP IC_AXI_W is {`
72	17	eyalhoc	`ID ID_BITS input SON(CHANGE 1)`
73	2	eyalhoc	`DATA DATA_BITS input`
74			`STRB DATA_BITS/8 input`
75			`LAST 1 input`
76			`USER USER_BITS input`
77			`VALID 1 input`
78			`READY 1 output`
79			`}`
80
81			`GROUP IC_AXI_B is {`
82	17	eyalhoc	`ID ID_BITS output SON(CHANGE 1)`
83	2	eyalhoc	`RESP 2 output`
84			`USER USER_BITS output`
85			`VALID 1 output`
86			`READY 1 input`
87			`}`
88
89			`GROUP IC_AXI_R is {`
90	17	eyalhoc	`ID ID_BITS output SON(CHANGE 1)`
91	2	eyalhoc	`DATA DATA_BITS output`
92			`RESP 2 output`
93			`LAST 1 output`
94			`USER USER_BITS output`
95			`VALID 1 output`
96			`READY 1 input`
97			`}`
98
99			`GROUP IC_AXI joins {`
100			`GROUP IC_AXI_A prefix_AW`
101			`GROUP IC_AXI_W prefix_W`
102			`GROUP IC_AXI_B prefix_B`
103			`GROUP IC_AXI_A prefix_AR`
104			`GROUP IC_AXI_R prefix_R`
105			`}`
106
107			`GROUP IC_AXI_CMD is {`
108			`SLV SLV_BITS input`
109	17	eyalhoc	`ID ID_BITS input SON(CHANGE 1)`
110	2	eyalhoc	`VALID 1 input`
111			`READY 1 input`
112			`}`

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[/] [axi_master/] [trunk/] [src/] [base/] [def_ic_static.txt] - Blame information for rev 21