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[/] [axi_slave/] [trunk/] [src/] [base/] [axi_slave_busy.v] - Blame information for rev 2

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  Author: Eyal Hochberg                                      ////
////          eyal@provartec.com                                 ////
////                                                             ////
////  Downloaded from: http://www.opencores.org                  ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2010 Provartec LTD                            ////
//// www.provartec.com                                           ////
//// info@provartec.com                                          ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
//// This source file is free software; you can redistribute it  ////
//// and/or modify it under the terms of the GNU Lesser General  ////
//// Public License as published by the Free Software Foundation.////
////                                                             ////
//// This source is distributed in the hope that it will be      ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
//// PURPOSE.  See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html              ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
OUTFILE PREFIX_busy.v
 
INCLUDE def_axi_slave.txt
 
module PREFIX_busy(PORTS);
 
`include "prgen_rand.v"
 
   input                      clk;
   input                      reset;
 
   input                      ARREADY_pre;
   input                      RVALID_pre;
   input                      AWREADY_pre;
   input                      WREADY_pre;
   input                      BVALID_pre;
 
   output                     ARREADY;
   output                     RVALID;
   output                     AWREADY;
   output                     WREADY;
   output                     BVALID;
 
   output                     RBUSY;
   output                     BBUSY;
 
 
   reg                        stall_enable    = 1;
 
   integer                    burst_chance    = 1;
   integer                    burst_len       = 10;
   integer                    burst_val       = 90;
 
   integer                    ar_stall_chance = 10;
   integer                    r_stall_chance  = 10;
   integer                    aw_stall_chance = 10;
   integer                    w_stall_chance  = 10;
   integer                    b_stall_chance  = 10;
 
 
   integer                    burst_type;
   reg                        burst_stall;
   integer                    ar_stall_chance_valid;
   integer                    r_stall_chance_valid;
   integer                    aw_stall_chance_valid;
   integer                    w_stall_chance_valid;
   integer                    b_stall_chance_valid;
 
 
   reg                        ARBUSY_pre = 0;
   reg                        RBUSY_pre = 0;
   reg                        AWBUSY_pre = 0;
   reg                        WBUSY_pre = 0;
   reg                        BBUSY_pre = 0;
   reg                        ARBUSY;
   reg                        RBUSY;
   reg                        AWBUSY;
   reg                        WBUSY;
   reg                        BBUSY;
 
 
 
   assign                     ARREADY = ARREADY_pre & (~ARBUSY);
   assign                     RVALID  = RVALID_pre; //in rd_buff
   assign                     AWREADY = AWREADY_pre & (~AWBUSY);
   assign                     WREADY  = WREADY_pre  & (~WBUSY);
   assign                     BVALID  = BVALID_pre; //in wresp
 
 
   task set_stall;
      reg stall;
      begin
         ar_stall_chance_valid = ar_stall_chance;
         r_stall_chance_valid  = r_stall_chance;
         aw_stall_chance_valid = aw_stall_chance;
         w_stall_chance_valid  = w_stall_chance;
         b_stall_chance_valid  = b_stall_chance;
      end
   endtask
 
   initial
     begin
        #FFD;
        set_stall;
 
        if (burst_chance > 0)
          forever
            begin
               burst_stall = rand_chance(burst_chance);
 
               if (burst_stall)
                 begin
                    #FFD;
                    burst_type = rand(1, 5);
 
                    case (burst_type)
                      1 : ar_stall_chance_valid = burst_val;
                      2 : r_stall_chance_valid  = burst_val;
                      3 : aw_stall_chance_valid = burst_val;
                      4 : w_stall_chance_valid  = burst_val;
                      5 : b_stall_chance_valid  = burst_val;
                    endcase
 
                    repeat (burst_len) @(posedge clk);
                    set_stall;
                 end
               else
                 begin
                    @(posedge clk);
                 end
            end
     end
 
   always @(posedge clk)
     begin
        #FFD;
        ARBUSY_pre = rand_chance(ar_stall_chance_valid);
        RBUSY_pre  = rand_chance(r_stall_chance_valid);
        AWBUSY_pre = rand_chance(aw_stall_chance_valid);
        WBUSY_pre  = rand_chance(w_stall_chance_valid);
        BBUSY_pre  = rand_chance(b_stall_chance_valid);
     end
 
   always @(posedge clk or posedge reset)
     if (reset)
       begin
          ARBUSY <= #FFD 1'b0;
          RBUSY  <= #FFD 1'b0;
          AWBUSY <= #FFD 1'b0;
          WBUSY  <= #FFD 1'b0;
          BBUSY  <= #FFD 1'b0;
       end
     else if (stall_enable)
       begin
          ARBUSY <= #FFD ARBUSY_pre;
          RBUSY  <= #FFD RBUSY_pre;
          AWBUSY <= #FFD AWBUSY_pre;
          WBUSY  <= #FFD WBUSY_pre;
          BBUSY  <= #FFD BBUSY_pre;
       end
     else
       begin
          ARBUSY <= #FFD 1'b0;
          RBUSY  <= #FFD 1'b0;
          AWBUSY <= #FFD 1'b0;
          WBUSY  <= #FFD 1'b0;
          BBUSY  <= #FFD 1'b0;
       end
 
endmodule
 
 
 
 
 
 
 
 

Line No.	Rev	Author	Line
1	2	eyalhoc	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Author: Eyal Hochberg ////`
4			`//// eyal@provartec.com ////`
5			`//// ////`
6			`//// Downloaded from: http://www.opencores.org ////`
7			`/////////////////////////////////////////////////////////////////////`
8			`//// ////`
9			`//// Copyright (C) 2010 Provartec LTD ////`
10			`//// www.provartec.com ////`
11			`//// info@provartec.com ////`
12			`//// ////`
13			`//// This source file may be used and distributed without ////`
14			`//// restriction provided that this copyright statement is not ////`
15			`//// removed from the file and that any derivative work contains ////`
16			`//// the original copyright notice and the associated disclaimer.////`
17			`//// ////`
18			`//// This source file is free software; you can redistribute it ////`
19			`//// and/or modify it under the terms of the GNU Lesser General ////`
20			`//// Public License as published by the Free Software Foundation.////`
21			`//// ////`
22			`//// This source is distributed in the hope that it will be ////`
23			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
24			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
25			`//// PURPOSE. See the GNU Lesser General Public License for more////`
26			`//// details. http://www.gnu.org/licenses/lgpl.html ////`
27			`//// ////`
28			`/////////////////////////////////////////////////////////////////////`
29
30			`OUTFILE PREFIX_busy.v`
31
32			`INCLUDE def_axi_slave.txt`
33
34			`module PREFIX_busy(PORTS);`
35
36			`include "prgen_rand.v"
37
38			`input clk;`
39			`input reset;`
40
41			`input ARREADY_pre;`
42			`input RVALID_pre;`
43			`input AWREADY_pre;`
44			`input WREADY_pre;`
45			`input BVALID_pre;`
46
47			`output ARREADY;`
48			`output RVALID;`
49			`output AWREADY;`
50			`output WREADY;`
51			`output BVALID;`
52
53			`output RBUSY;`
54			`output BBUSY;`
55
56
57			`reg stall_enable = 1;`
58
59			`integer burst_chance = 1;`
60			`integer burst_len = 10;`
61			`integer burst_val = 90;`
62
63			`integer ar_stall_chance = 10;`
64			`integer r_stall_chance = 10;`
65			`integer aw_stall_chance = 10;`
66			`integer w_stall_chance = 10;`
67			`integer b_stall_chance = 10;`
68
69
70			`integer burst_type;`
71			`reg burst_stall;`
72			`integer ar_stall_chance_valid;`
73			`integer r_stall_chance_valid;`
74			`integer aw_stall_chance_valid;`
75			`integer w_stall_chance_valid;`
76			`integer b_stall_chance_valid;`
77
78
79			`reg ARBUSY_pre = 0;`
80			`reg RBUSY_pre = 0;`
81			`reg AWBUSY_pre = 0;`
82			`reg WBUSY_pre = 0;`
83			`reg BBUSY_pre = 0;`
84			`reg ARBUSY;`
85			`reg RBUSY;`
86			`reg AWBUSY;`
87			`reg WBUSY;`
88			`reg BBUSY;`
89
90
91
92			`assign ARREADY = ARREADY_pre & (~ARBUSY);`
93			`assign RVALID = RVALID_pre; //in rd_buff`
94			`assign AWREADY = AWREADY_pre & (~AWBUSY);`
95			`assign WREADY = WREADY_pre & (~WBUSY);`
96			`assign BVALID = BVALID_pre; //in wresp`
97
98
99			`task set_stall;`
100			`reg stall;`
101			`begin`
102			`ar_stall_chance_valid = ar_stall_chance;`
103			`r_stall_chance_valid = r_stall_chance;`
104			`aw_stall_chance_valid = aw_stall_chance;`
105			`w_stall_chance_valid = w_stall_chance;`
106			`b_stall_chance_valid = b_stall_chance;`
107			`end`
108			`endtask`
109
110			`initial`
111			`begin`
112			`#FFD;`
113			`set_stall;`
114
115			`if (burst_chance > 0)`
116			`forever`
117			`begin`
118			`burst_stall = rand_chance(burst_chance);`
119
120			`if (burst_stall)`
121			`begin`
122			`#FFD;`
123			`burst_type = rand(1, 5);`
124
125			`case (burst_type)`
126			`1 : ar_stall_chance_valid = burst_val;`
127			`2 : r_stall_chance_valid = burst_val;`
128			`3 : aw_stall_chance_valid = burst_val;`
129			`4 : w_stall_chance_valid = burst_val;`
130			`5 : b_stall_chance_valid = burst_val;`
131			`endcase`
132
133			`repeat (burst_len) @(posedge clk);`
134			`set_stall;`
135			`end`
136			`else`
137			`begin`
138			`@(posedge clk);`
139			`end`
140			`end`
141			`end`
142
143			`always @(posedge clk)`
144			`begin`
145			`#FFD;`
146			`ARBUSY_pre = rand_chance(ar_stall_chance_valid);`
147			`RBUSY_pre = rand_chance(r_stall_chance_valid);`
148			`AWBUSY_pre = rand_chance(aw_stall_chance_valid);`
149			`WBUSY_pre = rand_chance(w_stall_chance_valid);`
150			`BBUSY_pre = rand_chance(b_stall_chance_valid);`
151			`end`
152
153			`always @(posedge clk or posedge reset)`
154			`if (reset)`
155			`begin`
156			`ARBUSY <= #FFD 1'b0;`
157			`RBUSY <= #FFD 1'b0;`
158			`AWBUSY <= #FFD 1'b0;`
159			`WBUSY <= #FFD 1'b0;`
160			`BBUSY <= #FFD 1'b0;`
161			`end`
162			`else if (stall_enable)`
163			`begin`
164			`ARBUSY <= #FFD ARBUSY_pre;`
165			`RBUSY <= #FFD RBUSY_pre;`
166			`AWBUSY <= #FFD AWBUSY_pre;`
167			`WBUSY <= #FFD WBUSY_pre;`
168			`BBUSY <= #FFD BBUSY_pre;`
169			`end`
170			`else`
171			`begin`
172			`ARBUSY <= #FFD 1'b0;`
173			`RBUSY <= #FFD 1'b0;`
174			`AWBUSY <= #FFD 1'b0;`
175			`WBUSY <= #FFD 1'b0;`
176			`BBUSY <= #FFD 1'b0;`
177			`end`
178
179			`endmodule`
180
181
182
183
184
185
186
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[/] [axi_slave/] [trunk/] [src/] [base/] [axi_slave_busy.v] - Blame information for rev 2