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/* ********************************************************************************* */
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/* */
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/* Main module for biquad filter */
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/* */
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/* Author: Chuck Cox (chuck100@home.com) */
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/* */
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/* This filter core uses a wishbone interface for compatibility with other cores: */
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/* */
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/* Wishbone general description: 16x5 register file */
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/* Supported cycles: Slave Read/write, block read/write, RMW */
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/* Data port size: 16 bit */
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/* Data port granularity: 16 bit */
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/* Data port maximum operand size: 16 bit */
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/* */
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/* Addr register */
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/* ---- -------- */
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/* 0x0 Filter coefficient a11 */
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/* 0x1 Filter coefficient a12 */
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/* 0x2 Filter coefficient b10 */
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/* 0x3 Filter coefficient b11 */
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/* 0x4 Filter coefficient b12 */
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/* */
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/* Filter coefficients need to be written as 16 bit twos complement fractional */
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/* numbers. For example: 0100_0000_0000_0001 = 2^-1 + 2^-15 = .500030517578125 */
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/* */
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/* The equation for the filter implemented with this core is */
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/* y[n] = b10 * x[n] + b11 * x[n-1] + b12 * x[n-2] + a11 * y[n-1] + a12 * y[n-2] */
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/* */
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/* This biquad filter is parameterized. If a filter with coefficients less than */
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/* 16 bits in length is selected via parameters then the most significant bits of */
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/* the value written to the filter coefficient register shall be used (ie */
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/* coefficients shall be truncated as required by parameter value COEFWIDTH). */
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/* */
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/* See comments in biquad module for more details on filtering algorthm. */
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/* ********************************************************************************* */
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module bqmain
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(
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clk_i, /* Wishbone clk */
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rst_i, /* Wishbone asynchronous active high reset */
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we_i, /* Wishbone write enable */
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stb_i, /* Wishbone strobe */
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ack_o, /* Wishbone ack */
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dat_i, /* Wishbone input data */
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dat_o, /* Wishbone output data */
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adr_i, /* Wishbone address bus */
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dspclk, /* DSP processing clock */
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nreset, /* active low asynchronous reset for filter block */
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x, /* input data for filter */
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valid, /* data valid input */
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y /* filter output data */
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);
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parameter DATAWIDTH = 8;
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parameter COEFWIDTH = 8;
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input clk_i;
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input rst_i;
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input we_i;
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input stb_i;
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output ack_o;
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input [15:0] dat_i;
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output [15:0] dat_o;
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input [2:0] adr_i;
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input dspclk;
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input nreset;
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input [DATAWIDTH-1:0] x;
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input valid;
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output [DATAWIDTH-1:0] y;
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wire [15:0] a11;
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wire [15:0] a12;
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wire [15:0] b10;
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wire [15:0] b11;
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wire [15:0] b12;
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/* Filter module */
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biquad biquadi
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(
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.clk(dspclk), /* clock */
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.nreset(nreset), /* active low reset */
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.x(x), /* data input */
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.valid(valid), /* input data valid */
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.a11(a11[15:16-COEFWIDTH]), /* filter pole coefficient */
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.a12(a12[15:16-COEFWIDTH]), /* filter pole coefficient */
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.b10(b10[15:16-COEFWIDTH]), /* filter zero coefficient */
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.b11(b11[15:16-COEFWIDTH]), /* filter zero coefficient */
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.b12(b12[15:16-COEFWIDTH]), /* filter zero coefficient */
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.yout(y) /* filter output */
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);
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/* Wishbone interface module */
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coefio coefioi
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(
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.clk_i(clk_i),
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.rst_i(rst_i),
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.we_i(we_i),
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.stb_i(stb_i),
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.ack_o(ack_o),
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.dat_i(dat_i),
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.dat_o(dat_o),
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.adr_i(adr_i),
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.a11(a11),
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.a12(a12),
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.b10(b10),
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.b11(b11),
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.b12(b12)
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);
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endmodule
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