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[/] [bitserial/] [trunk/] [peripherals.vhd] - Blame information for rev 2

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1 2 howe.r.j.8 
-- File:        peripherals.vhd
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-- Author:      Richard James Howe
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-- Repository:  https://github.com/howerj/bit-serial
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-- License:     MIT
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-- Description: Memory and Memory mapped peripherals
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library ieee, work, std;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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use work.util.all;
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use work.uart_pkg.all;
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entity peripherals is
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        generic (
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                g:                common_generics;
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                file_name:        string;
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                baud:             positive;
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                W:                positive;
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                N:                positive;
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                uart_fifo_depth:  natural;
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                uart_use_cfg:     boolean);
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        port (
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                clk:         in std_ulogic;
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                rst:         in std_ulogic;
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                rx:          in std_ulogic;
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                tx:         out std_ulogic;
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                ld:         out std_ulogic_vector(7 downto 0);
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                sw:          in std_ulogic_vector(7 downto 0);
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                i, a:        in std_ulogic;
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                o:          out std_ulogic;
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                oe, ie, ae:  in std_ulogic);
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end;
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architecture rtl of peripherals is
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        constant data_length: positive := N;
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        constant addr_length: positive := W;
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        type registers_t is record
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                r_a:  std_ulogic_vector(N - 1 downto 0);
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                r_i:  std_ulogic_vector(N - 1 downto 0);
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                r_o:  std_ulogic_vector(N - 1 downto 0);
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                r_ld: std_ulogic_vector(ld'range);
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                r_ie: std_ulogic;
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        end record;
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        constant registers_default: registers_t := (
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                r_a  => (others => '0'),
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                r_i  => (others => '0'),
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                r_o  => (others => '0'),
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                r_ld => (others => '0'),
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                r_ie => '0'
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        );
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        signal c, f: registers_t := registers_default;
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        signal io,   write: boolean    := false;
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        signal dwe,    dre: std_ulogic := '0';
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        signal dout: std_ulogic_vector(N - 1 downto 0) := (others => '0');
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        signal tx_fifo_full:  std_ulogic;
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        signal tx_fifo_empty: std_ulogic;
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        signal tx_fifo_we:    std_ulogic;
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        signal tx_fifo_data:  std_ulogic_vector(7 downto 0);
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        signal rx_fifo_full:  std_ulogic;
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        signal rx_fifo_empty: std_ulogic;
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        signal rx_fifo_re:    std_ulogic;
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        signal rx_fifo_data:  std_ulogic_vector(7 downto 0);
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        signal reg:             std_ulogic_vector(15 downto 0);
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        signal clock_reg_tx_we: std_ulogic;
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        signal clock_reg_rx_we: std_ulogic;
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        signal control_reg_we:  std_ulogic;
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        signal io_addr: std_ulogic_vector(2 downto 0);
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begin
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        io           <= c.r_a(c.r_a'high - 1) = '1' and ae = '0' after g.delay;
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        io_addr      <= c.r_a(io_addr'range) after g.delay;
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        write        <= true when (c.r_ie and (c.r_ie xor f.r_ie)) = '1' else false after g.delay;
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        ld           <= c.r_ld                    after g.delay;
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        o            <= c.r_o(0)                  after g.delay;
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        tx_fifo_data <= c.r_i(tx_fifo_data'range) after g.delay;
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        reg          <= c.r_i(reg'range)          after g.delay;
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        uart: entity work.uart_top
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                generic map (
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                        clock_frequency    => g.clock_frequency,
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                        delay              => g.delay,
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                        asynchronous_reset => g.asynchronous_reset,
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                        baud               => baud,
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                        fifo_depth         => uart_fifo_depth,
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                        use_cfg            => uart_use_cfg)
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                port map(
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                        clk => clk, rst => rst,
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                        tx               =>  tx,
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                        tx_fifo_full     =>  tx_fifo_full,
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                        tx_fifo_empty    =>  tx_fifo_empty,
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                        tx_fifo_we       =>  tx_fifo_we,
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                        tx_fifo_data     =>  tx_fifo_data,
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                        rx               =>  rx,
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                        rx_fifo_full     =>  rx_fifo_full,
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                        rx_fifo_empty    =>  rx_fifo_empty,
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                        rx_fifo_re       =>  rx_fifo_re,
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                        rx_fifo_data     =>  rx_fifo_data,
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                        reg              =>  reg,
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                        clock_reg_tx_we  =>  clock_reg_tx_we,
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                        clock_reg_rx_we  =>  clock_reg_rx_we,
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                        control_reg_we   =>  control_reg_we);
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        bram: entity work.single_port_block_ram
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                generic map(
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                        g           => g,
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                        file_name   => file_name,
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                        file_type   => FILE_HEX,
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                        addr_length => addr_length,
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                        data_length => data_length)
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                port map (
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                        clk  => clk,
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                        dwe  => dwe,
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                        addr => f.r_a(addr_length - 1 downto 0),
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                        dre  => dre,
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                        din  => f.r_i,
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                        dout => dout);
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        process (clk, rst)
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        begin
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                if rst = '1' and g.asynchronous_reset then
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                        c <= registers_default after g.delay;
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                elsif rising_edge(clk) then
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                        if rst = '1' and not g.asynchronous_reset then
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                                c <= registers_default after g.delay;
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                        else
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                                c <= f after g.delay;
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                        end if;
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                end if;
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        end process;
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        process (c, i, a, oe, ie, ae, dout, io, write, sw, rx, io_addr,
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                rx_fifo_data, rx_fifo_empty, rx_fifo_full, tx_fifo_empty, tx_fifo_full)
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        begin
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                f               <= c    after g.delay;
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                f.r_o           <= dout after g.delay;
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                f.r_ie          <= ie   after g.delay;
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                dre             <= '1'  after g.delay;
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                dwe             <= '0'  after g.delay;
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                tx_fifo_we      <= '0'  after g.delay;
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                rx_fifo_re      <= '0'  after g.delay;
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                clock_reg_tx_we <= '0'  after g.delay;
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                clock_reg_rx_we <= '0'  after g.delay;
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                control_reg_we  <= '0'  after g.delay;
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                if ae = '1' then f.r_a <= a        & c.r_a(c.r_a'high downto 1) after g.delay; end if;
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                if oe = '1' then f.r_o <= c.r_o(0) & c.r_o(c.r_o'high downto 1) after g.delay; end if;
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                if ie = '1' then f.r_i <= i        & c.r_i(c.r_i'high downto 1) after g.delay; end if;
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                if oe = '0' and ae = '0' then
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                        if io = false then
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                                dre <= '1' after g.delay;
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                        else
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                                f.r_o <= (others => '0') after g.delay;
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                                case io_addr is
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                                when "000" => f.r_o(sw'range) <= sw after g.delay;
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                                when "001" =>
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                                        f.r_o(7 downto 0) <= rx_fifo_data  after g.delay;
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                                        f.r_o(8)          <= rx_fifo_empty after g.delay;
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                                        f.r_o(9)          <= rx_fifo_full  after g.delay;
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                                        f.r_o(11)         <= tx_fifo_empty after g.delay;
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                                        f.r_o(12)         <= tx_fifo_full  after g.delay;
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                                when "010" =>
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                                when "011" =>
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                                when "100" =>
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                                when "101" =>
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                                when "110" =>
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                                when "111" =>
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                                when others =>
180 
                                end case;
181 
                        end if;
182 
                end if;
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                if write and ae = '0' then
185 
                        if io = false then
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                                dwe <= '1' after g.delay;
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                        else
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                                case io_addr is
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                                when "000" => f.r_ld <= c.r_i(c.r_ld'range) after g.delay;
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                                when "001" =>   tx_fifo_we <= c.r_i(13) after g.delay;
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                                                rx_fifo_re <= c.r_i(10) after g.delay;
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                                when "010" => if uart_use_cfg then clock_reg_tx_we <= '1' after g.delay; end if;
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                                when "011" => if uart_use_cfg then clock_reg_rx_we <= '1' after g.delay; end if;
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                                when "100" => if uart_use_cfg then control_reg_we  <= '1' after g.delay; end if;
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                                when "101" =>
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                                when "110" =>
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                                when "111" =>
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                                when others =>
199 
                                end case;
200 
                        end if;
201 
                end if;
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        end process;
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end architecture;
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