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<b><font size=+2 face="Helvetica, Arial" color=#bf0000>Project Name: Bluetooth baseband controller</font></b>

<p>

<font size=+1><b>Preliminary architecture</b></font>

<p>

<b>Interfaces:</b>

<ul>

<li><b>RF interface</b> Several interfaces have been checked such as JTAG and SPI but we are going to implement our standard interface and bild bridges around it for other interfaces</li>

<li><b>CPU interface</b> Wishbone SOC bus is going to be used to access the core. Two DMA channels (RX/TX) can be added </li>

<li><b>HCI</b> OpenCores USB and UART can be used. Messeges and control between host and Baseband are TBD</li>

<li><b>Voice interface</b> Standard PCM interface will be usedand internal codec will be implemented</li>

<li><b>Clocks</b> 1MHz, 13-20MHz (System clock)and 32KHz (low power mode)</li>

</ul>

<b>RF generic interface:</b>

<ul>

<li>This interface should be generic and simple so that it can be bridged to any other RF interfaces</li>

<li>The RF bridge will be responsible for mapping these signals into RF chip registers and signals according to specific RF chips interfaces</li>

<li><b>Clocks</b></li>

<ul>

<li>SysClk : Out : System clock</li>

<li>Clock frequency is TBD but a recommendation is to be

15-20MHz to accomodate any possible delay may be causes by

bridge state machines</li>

<li>Any extra clocks needed by RF should be handled by the

RF bridge</li>

</ul>

<li><b>Register group</b></li>

<ul>

<li>Dout(8) : Out: 8 bit bus to write to RF register</li>

<li>Din(8)  : In : 8 bit bus to read from RF register</li>

<li>Wr      : Out: write signal</li>

<li>Re      : Out: read signal</li>

<li>ReAck   : In : Read acknowledge</li>

<li>WrAck   : Out: Write acknowledge</li>

<li>(we need different buses for read and write because

JTAG interace can read and write at the same time)</li>

</ul>

<li><b>Data transfer</b></li>

<ul>

<li>TxEn  : Out : Tx Enable</li>

<li>TxRdy : in  : Tx Ready (RF got the data bit from

TxData)</li>

<li>Txdata: Out : Tx Data Bit</li>

<li>RxEn  : Out : Rx Enable</li>

<li>RxRdy : in  : Rx Ready (RF set the data bit to

RxData)</li>

<li>Rxdata: Out : Rx Data Bit</li>

</ul>

<li><b>Hop selection</b></li>

<ul>

<li>Hop(7) : Out : 7 bit hop bus</li>

<li>SetHop : Out : Load hop value to RF </li>

</ul>

</ul>

<b>Buffers:</b>

<ul>

<li>Tx and Rx buffers of the maximum packet sizes must be used at the RF side</li>

<li>Tx Buffer will be flushed only when the transmitted packet has acknoledged.</li>

<li>The buffers should be connected to the read/write and link state machines </li>

</ul>

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