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[/] [ccsds_rxtxsoc/] [trunk/] [ccsds_tx_coder.vhd] - Blame information for rev 2

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1 2 zguig52 
-------------------------------
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---- Project: EurySPACE CCSDS RX/TX with wishbone interface
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---- Design Name: ccsds_tx_coder
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---- Version: 1.0.0
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---- Description:
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---- Implementation of standard CCSDS 131.0-B-2
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-------------------------------
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---- Author(s):
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---- Guillaume REMBERT
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-------------------------------
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---- Licence:
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---- MIT
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-------------------------------
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---- Changes list:
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---- 2016/11/05: initial release
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-------------------------------
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-- libraries used
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library ieee;
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use ieee.std_logic_1164.all;
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--=============================================================================
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-- Entity declaration for ccsds_tx / unitary tx coder inputs and outputs
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--=============================================================================
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entity ccsds_tx_coder is
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  generic(
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    constant CCSDS_TX_CODER_ASM_LENGTH: integer; -- Attached Synchronization Marker length / in Bytes
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    constant CCSDS_TX_CODER_DATA_BUS_SIZE: integer; -- in bits
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    constant CCSDS_TX_CODER_DIFFERENTIAL_BITS_PER_CODEWORD: integer; -- Number of bits per codeword (should be equal to bits per symbol of lower link)
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    constant CCSDS_TX_CODER_DIFFERENTIAL_ENABLED: boolean -- Enable differential coder
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  );
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  port(
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    -- inputs
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    clk_i: in std_logic;
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    dat_i: in std_logic_vector(CCSDS_TX_CODER_DATA_BUS_SIZE-1 downto 0);
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    dat_val_i: in std_logic;
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    rst_i: in std_logic;
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    -- outputs
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    dat_o: out std_logic_vector(CCSDS_TX_CODER_DATA_BUS_SIZE+CCSDS_TX_CODER_ASM_LENGTH*8-1 downto 0);
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    dat_val_o: out std_logic
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  );
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end ccsds_tx_coder;
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--=============================================================================
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-- architecture declaration / internal components and connections
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--=============================================================================
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architecture structure of ccsds_tx_coder is
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  component ccsds_tx_coder_differential is
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    generic(
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      CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD: integer;
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      CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE: integer
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    );
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    port(
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      clk_i: in std_logic;
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      dat_i: in std_logic_vector(CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE-1 downto 0);
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      dat_val_i: in std_logic;
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      rst_i: in std_logic;
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      dat_o: out std_logic_vector(CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE-1 downto 0);
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      dat_val_o: out std_logic
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    );
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  end component;
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  component ccsds_tx_randomizer is
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    generic(
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      CCSDS_TX_RANDOMIZER_DATA_BUS_SIZE: integer
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    );
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    port(
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      clk_i: in std_logic;
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      dat_i: in std_logic_vector(CCSDS_TX_RANDOMIZER_DATA_BUS_SIZE-1 downto 0);
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      dat_val_i: in std_logic;
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      rst_i: in std_logic;
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      dat_o: out std_logic_vector(CCSDS_TX_RANDOMIZER_DATA_BUS_SIZE-1 downto 0);
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      dat_val_o: out std_logic
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    );
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  end component;
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  component ccsds_tx_synchronizer is
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    generic(
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      CCSDS_TX_ASM_LENGTH: integer;
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      CCSDS_TX_ASM_DATA_BUS_SIZE: integer
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    );
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    port(
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      clk_i: in std_logic;
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      dat_i: in std_logic_vector(CCSDS_TX_ASM_DATA_BUS_SIZE-1 downto 0);
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      dat_val_i: in std_logic;
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      rst_i: in std_logic;
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      dat_o: out std_logic_vector(CCSDS_TX_ASM_DATA_BUS_SIZE+CCSDS_TX_ASM_LENGTH*8-1 downto 0);
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      dat_val_o: out std_logic
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    );
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  end component;
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-- internal constants
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-- internal variable signals
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  signal wire_coder_diff_dat_o: std_logic_vector(CCSDS_TX_CODER_DATA_BUS_SIZE+CCSDS_TX_CODER_ASM_LENGTH*8-1 downto 0);
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  signal wire_coder_diff_dat_val_o: std_logic;
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  signal wire_randomizer_dat_o: std_logic_vector(CCSDS_TX_CODER_DATA_BUS_SIZE-1 downto 0);
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  signal wire_randomizer_dat_val_o: std_logic;
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  signal wire_synchronizer_dat_o: std_logic_vector(CCSDS_TX_CODER_DATA_BUS_SIZE+CCSDS_TX_CODER_ASM_LENGTH*8-1 downto 0);
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  signal wire_synchronizer_dat_val_o: std_logic;
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-- components instanciation and mapping
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  begin
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  tx_coder_randomizer_0: ccsds_tx_randomizer
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    generic map(
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      CCSDS_TX_RANDOMIZER_DATA_BUS_SIZE => CCSDS_TX_CODER_DATA_BUS_SIZE
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    )
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    port map(
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      clk_i => clk_i,
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      rst_i => rst_i,
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      dat_val_i => dat_val_i,
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      dat_i => dat_i,
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      dat_val_o => wire_randomizer_dat_val_o,
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      dat_o => wire_randomizer_dat_o
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    );
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  NODIFFCODERGENP: if (CCSDS_TX_CODER_DIFFERENTIAL_ENABLED = false) generate
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    tx_coder_synchronizer_0: ccsds_tx_synchronizer
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      generic map(
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        CCSDS_TX_ASM_LENGTH => CCSDS_TX_CODER_ASM_LENGTH,
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        CCSDS_TX_ASM_DATA_BUS_SIZE => CCSDS_TX_CODER_DATA_BUS_SIZE
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      )
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      port map(
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        clk_i => clk_i,
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        rst_i => rst_i,
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        dat_val_i => wire_randomizer_dat_val_o,
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        dat_i => wire_randomizer_dat_o,
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        dat_val_o => dat_val_o,
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        dat_o => dat_o
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      );
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   end generate NODIFFCODERGENP;
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  DIFFCODERGENP: if (CCSDS_TX_CODER_DIFFERENTIAL_ENABLED = true) generate
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    tx_coder_synchronizer_0: ccsds_tx_synchronizer
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      generic map(
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        CCSDS_TX_ASM_LENGTH => CCSDS_TX_CODER_ASM_LENGTH,
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        CCSDS_TX_ASM_DATA_BUS_SIZE => CCSDS_TX_CODER_DATA_BUS_SIZE
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      )
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      port map(
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        clk_i => clk_i,
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        rst_i => rst_i,
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        dat_val_i => wire_randomizer_dat_val_o,
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        dat_i => wire_randomizer_dat_o,
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        dat_val_o => wire_synchronizer_dat_val_o,
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        dat_o => wire_synchronizer_dat_o
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      );
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    tx_coder_differential_0: ccsds_tx_coder_differential
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      generic map(
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        CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD => CCSDS_TX_CODER_DIFFERENTIAL_BITS_PER_CODEWORD,
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        CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE => CCSDS_TX_CODER_DATA_BUS_SIZE+CCSDS_TX_CODER_ASM_LENGTH*8
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      )
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      port map(
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        clk_i => clk_i,
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        rst_i => rst_i,
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        dat_val_i => wire_synchronizer_dat_val_o,
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        dat_i => wire_synchronizer_dat_o,
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        dat_val_o => dat_val_o,
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        dat_o => dat_o
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      );
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   end generate DIFFCODERGENP;
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-- presynthesis checks
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-- internal processing
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end structure;

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