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[/] [cde/] [trunk/] [ip/] [sram/] [rtl/] [xml/] [sram_be.xml] - Blame information for rev 2

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
sram
be
 
 
 
 
 
 
 
 

       
 
 
              
              sim*simulation*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn*synthesis*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              lintlint
 
              Verilog
              
                     
                            fs-lint
                     
              
 
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              *documentation*
              Verilog
              
              
 
 
 
 
      
 
 
 

ADDR0
WIDTH8
WORDS0
WRITETHRU0
DEFAULT{WIDTH{1'bx}}
INIT_FILE"NONE"
INSTANCE_NAME"U1"

 

 
clk
wire
in

 
cs
wire
in

 
wr
wire
in

 
rd
wire
in

 
be
wire
in

 
 
addr
wire
in
ADDR-10

 
 
wdata
wire
in
WIDTH-10

 
rdata
reg
out
WIDTH-10

 
 
 

 

 
 
 
 
 
 

 
 
 
   
      fs-sim
 
       
        dest_dir../verilog/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        dest_dir../verilog/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
   
      fs-lint
 
 
      
        dest_dir../verilog/lint/
        verilogSourcelibraryDir
      
 
   
 
 
 

 
 
 
 
 
 
 


Line No.	Rev	Author	Line
1	2	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`sram`
15			`be`
16
17
18
19
20
21
22
23
24
25
26
27
28
29			`simsimulation`
30
31			`Verilog`
32
33
34			`fs-sim`
35
36
37
38
39			`synsynthesis`
40
41			`Verilog`
42
43
44			`fs-syn`
45
46
47
48
49
50			`lintlint`
51
52			`Verilog`
53
54
55			`fs-lint`
56
57
58
59
60
61
62
63			`doc`
64
65
66			`spirit:library="Testbench"`
67			`spirit:name="toolflow"`
68			`spirit:version="documentation"/>`
69
70			`documentation`
71			`Verilog`
72
73
74
75
76
77
78
79
80
81
82
83			`ADDR0`
84			`WIDTH8`
85			`WORDS0`
86			`WRITETHRU0`
87			`DEFAULT{WIDTH{1'bx}}`
88			`INIT_FILE"NONE"`
89			`INSTANCE_NAME"U1"`
90
91
92
93
94			`clk`
95			`wire`
96			`in`
97
98
99			`cs`
100			`wire`
101			`in`
102
103
104			`wr`
105			`wire`
106			`in`
107
108
109			`rd`
110			`wire`
111			`in`
112
113
114			`be`
115			`wire`
116			`in`
117
118
119
120			`addr`
121			`wire`
122			`in`
123			`ADDR-10`
124
125
126
127			`wdata`
128			`wire`
129			`in`
130			`WIDTH-10`
131
132
133			`rdata`
134			`reg`
135			`out`
136			`WIDTH-10`
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155			`fs-sim`
156
157
158			`dest_dir../verilog/`
159			`verilogSourcelibraryDir`
160
161
162
163
164
165
166			`fs-syn`
167
168
169			`dest_dir../verilog/`
170			`verilogSourcelibraryDir`
171
172
173
174
175
176
177
178
179			`fs-lint`
180
181
182
183			`dest_dir../verilog/lint/`
184			`verilogSourcelibraryDir`
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199

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[/] [cde/] [trunk/] [ip/] [sram/] [rtl/] [xml/] [sram_be.xml] - Blame information for rev 2