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-------------------------------------------------------------------------------
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--
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-- Copyright (C) 2009
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-------------------------------------------------------------------------------
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-- Purpose : Switch output high or low
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-- Description:
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-- . The output goes high when switch_high='1' and low when switch_low='1'.
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-- . If g_or_high is true then the output follows the switch_high immediately,
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-- else it goes high in the next clk cycle.
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-- . If g_and_low is true then the output follows the switch_low immediately,
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-- else it goes low in the next clk cycle.
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-- The g_priority_lo defines which input has priority when switch_high and
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-- switch_low are active simultaneously.
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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ENTITY common_switch IS
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GENERIC (
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g_rst_level : STD_LOGIC := '0'; -- Defines the output level at reset.
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g_priority_lo : BOOLEAN := TRUE; -- When TRUE then input switch_low has priority, else switch_high. Don't care when switch_high and switch_low are pulses that do not occur simultaneously.
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g_or_high : BOOLEAN := FALSE; -- When TRUE and priority hi then the registered switch_level is OR-ed with the input switch_high to get out_level, else out_level is the registered switch_level
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g_and_low : BOOLEAN := FALSE -- When TRUE and priority lo then the registered switch_level is AND-ed with the input switch_low to get out_level, else out_level is the registered switch_level
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);
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PORT (
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rst : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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clken : IN STD_LOGIC := '1';
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switch_high : IN STD_LOGIC; -- A pulse on switch_high makes the out_level go high
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switch_low : IN STD_LOGIC; -- A pulse on switch_low makes the out_level go low
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out_level : OUT STD_LOGIC
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);
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END;
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ARCHITECTURE rtl OF common_switch IS
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SIGNAL switch_level : STD_LOGIC := g_rst_level;
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SIGNAL nxt_switch_level : STD_LOGIC;
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BEGIN
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gen_wire : IF g_or_high=FALSE AND g_and_low=FALSE GENERATE
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out_level <= switch_level;
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END GENERATE;
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gen_or : IF g_or_high=TRUE AND g_and_low=FALSE GENERATE
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out_level <= switch_level OR switch_high;
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END GENERATE;
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gen_and : IF g_or_high=FALSE AND g_and_low=TRUE GENERATE
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out_level <= switch_level AND (NOT switch_low);
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END GENERATE;
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gen_or_and : IF g_or_high=TRUE AND g_and_low=TRUE GENERATE
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out_level <= (switch_level OR switch_high) AND (NOT switch_low);
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END GENERATE;
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p_reg : PROCESS(rst, clk)
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BEGIN
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IF rst='1' THEN
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switch_level <= g_rst_level;
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ELSIF rising_edge(clk) THEN
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IF clken='1' THEN
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switch_level <= nxt_switch_level;
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END IF;
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END IF;
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END PROCESS;
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p_switch_level : PROCESS(switch_level, switch_low, switch_high)
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BEGIN
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nxt_switch_level <= switch_level;
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IF g_priority_lo=TRUE THEN
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IF switch_low='1' THEN
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nxt_switch_level <= '0';
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ELSIF switch_high='1' THEN
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nxt_switch_level <= '1';
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END IF;
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ELSE
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IF switch_high='1' THEN
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nxt_switch_level <= '1';
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ELSIF switch_low='1' THEN
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nxt_switch_level <= '0';
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END IF;
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END IF;
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END PROCESS;
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END rtl;
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