URL https://opencores.org/ocsvn/common_components/common_components/trunk

Subversion Repositories common_components

[/] [common_components/] [trunk/] [hdllib.cfg] - Blame information for rev 5

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hdl_lib_name = common_components
hdl_library_clause_name = common_components_lib
hdl_lib_uses_synth = common_pkg
hdl_lib_uses_sim =
hdl_lib_technology =
 
synth_files =
    common_components_pkg.vhd
    common_switch.vhd
    common_pipeline.vhd
    common_pipeline_sl.vhd
    common_select_symbol.vhd
    common_delay.vhd
    common_bit_delay.vhd
    common_async.vhd
    common_areset.vhd
    common_spulse.vhd
    common_paged_reg.vhd
 
test_bench_files =
    tb_common_switch.vhd
    tb_common_spulse.vhd
 
regression_test_vhdl =
 
[modelsim_project_file]
modelsim_copy_files =
 
[quartus_project_file]
 

Line No.	Rev	Author	Line
1	2	danv	`hdl_lib_name = common_components`
2			`hdl_library_clause_name = common_components_lib`
3	3	danv	`hdl_lib_uses_synth = common_pkg`
4	2	danv	`hdl_lib_uses_sim =`
5			`hdl_lib_technology =`
6
7			`synth_files =`
8	3	danv	`common_components_pkg.vhd`
9	2	danv	`common_switch.vhd`
10	3	danv	`common_pipeline.vhd`
11			`common_pipeline_sl.vhd`
12			`common_select_symbol.vhd`
13			`common_delay.vhd`
14			`common_bit_delay.vhd`
15			`common_async.vhd`
16			`common_areset.vhd`
17			`common_spulse.vhd`
18	5	danv	`common_paged_reg.vhd`
19	3	danv
20	2	danv	`test_bench_files =`
21	3	danv	`tb_common_switch.vhd`
22			`tb_common_spulse.vhd`
23	2	danv
24			`regression_test_vhdl =`
25
26			`[modelsim_project_file]`
27			`modelsim_copy_files =`
28
29			`[quartus_project_file]`
30

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Subversion Repositories common_components

[/] [common_components/] [trunk/] [hdllib.cfg] - Blame information for rev 5